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  • CS - CH 3 Activities

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    Minn Thiha Chit
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    The document describes several activities related to digital logic gates and circuits. It includes tables that show the input and output values for different logic gates - AND, OR, NOT, NOR - as well as more complex circuits with multiple gates. It also describes intermediate values and operations performed in notebooks for some of the activities.

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    CS - Ch 3 Activities

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    The document describes several activities related to digital logic gates and circuits. It includes tables that show the input and output values for different logic gates - AND, OR, NOT, NOR - as well as more complex circuits with multiple gates. It also describes intermediate values and operations performed in notebooks for some of the activities.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    12 views5 pages

    CS - CH 3 Activities

    Uploaded by

    Minn Thiha Chit
    The document describes several activities related to digital logic gates and circuits. It includes tables that show the input and output values for different logic gates - AND, OR, NOT, NOR - as well as more complex circuits with multiple gates. It also describes intermediate values and operations performed in notebooks for some of the activities.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 5

    C 3 Activities

    Activity 3.1

    Activity 3.2

    a.

    Input values Intermediate values Output


    A B C D E X
    0 0 0 0 1 1
    0 0 0 0 1 1
    0 1 0 1 0 0
    0 1 0 1 0 0
    1 0 0 1 0 0
    1 0 0 1 0 0
    1 1 1 1 0 1
    1 1 1 1 0 1

    b.

    Input values Intermediate values Output


    A B C D E F X
    0 0 1 0 0 1 0
    0 0 1 0 0 1 0
    0 1 1 1 1 0 0
    0 1 1 1 1 0 0
    1 0 0 1 0 1 0
    1 0 0 1 0 1 0
    1 1 0 1 0 1 0
    1 1 0 1 0 1 0

    c.

    Input values Intermediate values Output


    A B C D E F X
    0 0 0 0 1 1 1
    0 0 1 0 1 1 1
    0 1 0 1 1 0 0
    0 1 1 1 0 1 1
    1 0 0 1 1 0 0
    1 0 1 1 1 0 1
    1 1 0 1 1 0 0
    1 1 1 1 0 1 1

    d.

    Input values Intermediate values Output


    A B C D E F X
    0 0 0 0 0 1 1
    0 0 1 0 1 1 0
    0 1 0 1 0 0 0
    0 1 1 1 1 0 1
    1 0 0 1 1 0 0
    1 0 1 1 1 0 1
    1 1 0 0 1 1 1
    1 1 1 0 1 1 0

    e.

    Input values Intermediate values Output


    A B C D E F G X
    0 0 0 0 1 1 0 0
    0 0 1 0 0 1 1 0
    0 1 0 1 0 0 0 0
    0 1 1 1 0 0 0 1
    1 0 0 1 1 0 1 1
    1 0 1 1 0 0 0 1
    1 1 0 1 0 0 0 0
    1 1 1 1 0 0 0 1

    Activity 3.3

    (in notebook)

    Activity 3.4

    (in notebook)

    Activity 3.5
    The AND gate:

    Input values Intermediate Output


    values
    A B C
    0 0 1 0
    0 0 1 0
    0 1 1 0
    0 1 1 0
    1 0 1 0
    1 0 1 0
    1 1 0 1
    1 1 0 1

    The OR gate:

    Input values Intermediate Output


    values
    A B C D
    0 0 1 1 0
    0 0 1 1 0
    0 1 1 0 1
    0 1 1 0 1
    1 0 0 1 1
    1 0 0 1 1
    1 1 0 0 1
    1 1 0 0 1

    The NOT gate:

    Input Output
    values
    A
    0 1
    0 1
    0 1
    0 1
    1 0
    1 0
    1 0
    1 0
    Activity 3.6

    Activity 3.7

    NOR gate

    Input values Intermediate values Output


    A B C D E X
    0 0 1 1 0 1
    0 0 1 1 0 1
    0 1 1 0 1 0
    0 1 1 0 1 0
    1 0 0 1 1 0
    1 0 0 1 1 0
    1 1 0 0 1 0
    1 1 0 0 1 0

    Activity 3.8

    Input values Intermediate values Output


    A B C D E X
    0 0 1 0 1 1
    0 0 1 0 1 1
    0 1 1 0 0 0
    0 1 1 0 0 0
    1 0 0 0 0 0
    1 0 0 0 0 0
    1 1 0 0 0 0
    1 1 0 0 0 0

    Activity 3.9

    Input values Intermediate values Output


    P Q R A B C X
    0 0 0 0 0 0 0
    0 0 1 0 1 1 1
    0 1 0 0 1 1 0
    0 1 1 0 1 1 1
    1 0 0 0 1 1 0
    1 0 1 0 1 1 1
    1 1 0 1 1 1 0
    1 1 1 1 1 1 1

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