Hardware Descriptive Language

TECHNOLOGICAL UNIVERSITY OF THE PHILIPPINES

Ayala Blvd. cor San Marcelino St. Ermina, Manila

“DcAdder : 2-bit Parallel Adder using 2x4 and 3x8

Decoder”

CPET7L – 2A
Thursday 7:00AM to 10:00PM

Submitted By:
Almarines, Jerico
Mendoza, Aldrin Daniel G.

Submitted To:
Engr. AIMEE G. ACOBA
CPE Faculty
 Hardware Descriptive Language

Description

The goal of this program is to make a 2-bit Parallel Adder by the use of Decoders. The following circuit is
combined into one to meet up the standard that is being needed for. By that, the outputs of each
combination will light up on specific LED in terms of its input condition. The following outcomes of the
simulation will be accorded onto the table that is being shown below. The process will include a 4-input
that will be containing at least 16 possible outcomes. Thus, this will observe the process of how 2-bit
Parallel Adder works by the other form of circuit design.

Truth Table

A1 A0 B1 B0 CarryIn2 Sum1 Sum0

0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 0 1 1
0 1 1 1 1 0 0
1 0 0 0 0 1 0
1 0 0 1 0 0 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0
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Verilog code

module DcAdderr(A1,B1,A0,B0,C0,CarryIn1,Sum0,Sum1,Carryin2,D0);

input wire A1;

input wire B1;

input wire A0;

input wire B0;

output wire C0;

output wire CarryIn1;

output wire Sum0;

output wire Sum1;

output wire D0;

wire SYNTHESIZED_WIRE_31;

wire SYNTHESIZED_WIRE_32;

wire SYNTHESIZED_WIRE_33;

wire SYNTHESIZED_WIRE_34;

wire SYNTHESIZED_WIRE_35;

wire SYNTHESIZED_WIRE_36;

wire SYNTHESIZED_WIRE_11;

wire SYNTHESIZED_WIRE_12;

wire SYNTHESIZED_WIRE_37;

wire SYNTHESIZED_WIRE_14;

wire SYNTHESIZED_WIRE_21;

wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_24;

wire SYNTHESIZED_WIRE_28;

wire SYNTHESIZED_WIRE_29;

assign CarryIn1 = SYNTHESIZED_WIRE_36;

assign SYNTHESIZED_WIRE_29 = A0 & SYNTHESIZED_WIRE_31;

assign C0 = SYNTHESIZED_WIRE_31 & SYNTHESIZED_WIRE_32;

assign SYNTHESIZED_WIRE_34 = ~B1;

assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_33 & SYNTHESIZED_WIRE_34 & A1;

assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_33 & B1 & SYNTHESIZED_WIRE_35;

assign SYNTHESIZED_WIRE_11 = SYNTHESIZED_WIRE_33 & B1 & A1;

assign SYNTHESIZED_WIRE_22 = SYNTHESIZED_WIRE_36 & SYNTHESIZED_WIRE_34 &

SYNTHESIZED_WIRE_35;

assign SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_36 & SYNTHESIZED_WIRE_34 & A1;

assign SYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_36 & B1 & SYNTHESIZED_WIRE_35;

assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_36 & B1 & A1;

assign SYNTHESIZED_WIRE_28 = B0 & SYNTHESIZED_WIRE_32;

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assign Sum1 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22 | SYNTHESIZED_WIRE_37 |

SYNTHESIZED_WIRE_24;

assign SYNTHESIZED_WIRE_36 = A0 & B0;

assign D0 = SYNTHESIZED_WIRE_33 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_35;

assign SYNTHESIZED_WIRE_31 = ~B0;

assign SYNTHESIZED_WIRE_32 = ~A0;

assign Sum0 = SYNTHESIZED_WIRE_28 | SYNTHESIZED_WIRE_29;

assign SYNTHESIZED_WIRE_35 = ~A1;

assign SYNTHESIZED_WIRE_33 = ~SYNTHESIZED_WIRE_36;

endmodule
 Hardware Descriptive Language

Schematic Design
 Hardware Descriptive Language

Waveform

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