Logic Families

Introduction & Overview

Logic Families
Logic Family : A collection of different IC’s that
have similar circuit characteristics
The circuit design of the basic gate of each logic
family is the same
The most important parameters for evaluating and
comparing logic families include :
Logic Levels
Power Dissipation
Propagation delay
Noise margin
Fan-out ( loading )

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Example Logic Families
General comparison or three commonly available logic
families.

the most important to understand

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Implementing Logic Circuits
There are several varieties of transistors – the
building blocks of logic gates – the most important
are:
BJT (bipolar junction transistors)
one of the first to be invented
FET (field effect transistors)
especially Metal-Oxide Semiconductor types (MOSFET’s)
MOSFET’s are of two types: NMOS and PMOS

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TTL and CMOS
Connecting BJT’s together gives rise to a family of logic gates
known as TTL
Connecting NMOS and PMOS transistors together gives rise
to the CMOS family of logic gates

MOSFET
BJT transistor types
(NMOS, PMOS)

TTL logic gate families CMOS

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Characteristics of logic families
Voltages and Currents
Noise Margin
Power Dissipation
Propagation Delay
Speed-Power Product
Fan-In, Fan-Out
Comparison of Logic Families

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Electrical Characteristics
TTL CMOS
faster (some versions) lower power consumption
strong drive capability simpler to make
rugged greater packing density
better noise immunity

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Voltage & Current
For a High-state gate driving a second gate, we define:
VOH (min), high-level output voltage, the minimum voltage level that a logic
gate will produce as a logic 1 output.
VIH (min), high-level input voltage, the minimum voltage level that a logic
gate will recognize as a logic 1 input. Voltage below this level will not be
accepted as high.
IOH, high-level output current, current that flows from an output in the logic
1 state under specified load conditions.
IIH, high-level input current, current that flows into an input when a logic 1
voltage is applied to that input.

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Voltage & Current

For a Low-state gate driving a second gate, we

define:
VOL (max), low-level output voltage, the maximum voltage level
that a logic gate will produce as a logic 0 output.
VIL (max), low-level input voltage, the maximum voltage level
that a logic gate will recognize as a logic 0 input. Voltage above
this value will not be accepted as low.
IOL , low-level output current, current that flows from an output in
the logic 0 state under specified load conditions.
IIL , low-level input current, current that flows into an input when
a logic 0 voltage is applied to that input.

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Electrical Characteristics

Important characteristics are:

logic 1

VOHmin min value of output recognized as a ‘1’

VIHmin min value input recognized as a ‘1’
indeterminate
input voltage
VILmax max value of input recognized as a ‘0’
VOLmax max value of output recognized as a ‘0’

logic 0 Values outside the given range are not allowed.

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Logic Level & Voltage Range
Typical acceptable voltage ranges for positive logic 1 and logic 0
are shown below
A logic gate with an input at a voltage level within the
‘indeterminate’ range will produce an unpredictable output level.

5.0V 5.0V
Logic 1 Logic 1
3.5V
2.5V Indeterminate
Indeterminate
1.5V
0.8V
Logic 0 Logic 0
0V 0V
TTL CMOS

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Noise Margin
Manufacturers specify voltage limits to represent the logical
0 or 1.
These limits are not the same at the input and output sides.
For example, a particular Gate A may output a voltage of 4.8V when
it is supposed to output a HIGH but, at its input side, it can take a
voltage of 3V as HIGH.
In this way, if any noise should corrupt the signal, there is
some margin for error.

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Noise Margin
If noise in the circuit is high enough
it can push a logic 0 up or drop a
logic 1 down into the indeterminate logic 1
VOHmin

or “illegal” region VIHmin

The magnitude of the voltage

required to reach this level is the indeterminate
noise margin input voltage

Noise margin for logic high is:

NMH = VOHmin – VIHmin VILmax
logic 0
VOLmax

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Noise Margin
Difference between the worst case output voltage of
one stage and worst case input voltage of next stage
Greater the difference, the more unwanted signal that
can be added without causing incorrect gate
operation

NMhigh = VOHmin - VIHmin

NMlow = VILmax - VOLmax

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Worked Example
Given the following parameters, calculate the noise
margin of 74LS series.
Param eter 74LS
VIH(min) 2V
VIL(max) 0.8V
VOH (min
) 2.7V
VOL (max
) 0.4V

Solution:
High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V
Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V

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Noise Margin & Noise Immunity
Noise immunity of a logic circuit refers to the circuit’s ability to
tolerate noise voltages on its inputs.
A quantitative measure of noise immunity is called noise margin
High Level Noise Margin, VNH = VOH (min) - VIH (min)
Low Level Noise Margin, VNL = VIL (max) - VOL (max)

Logic 1 Logic 1
VOH (min)
VNH
VIH (min)

VIL (max)
VNL
VOL (max)
Logic 0
Logic 0
Output Voltage Ranges Input Voltage Ranges
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Further Important Characteristics
The propagation delay (tpd) which is the time
taken for a change at the input to appear at the
output
The fan-out, which is the maximum number of
inputs that can be driven successfully to either
logic level before the output becomes invalid

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Speed: Rise & Fall Times
Rise Time
Time from 10% to 90% of signal, Low to High
Fall Time
Time from 90% to 10% of signal, High to Low

rise time fall time

10% 90% 90% 10% 18

Speed: Propagation Delay
A logic gate always takes some time to change states
tPLH is the delay time before output changes from low to high
tPHL is the delay time before output changes from high to low
both tPLH & tPHL are measured between the 50% points on the
input and output transitions

Input 50%

Output
0
tPHL tPLH 19
Power Dissipation
Static
I2R losses due to passive components, no input signal
Dynamic
I2R losses due to charging and discharging capacitances
through resistances, due to input signal

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Speed-Power Product
Speed (propagation delay) and power consumption
are the two most important performance parameters
of a digital IC.
A simple means for measuring and comparing the
overall performance of an IC family is the speed-
power product (the smaller, the better).
For example, an IC has
an average propagation delay of 10 ns
an average power dissipation of 5 mW
the speed-power product = (10 ns) x (5 mW)
= 50 picoJoules (pJ)

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Comparison of Logic Families

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Fan-In
Number of input signals to a gate
Not an electrical property
Function of the manufacturing process

NAND gate with a

Fan-in of 8

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Fan-Out
A measure of the ability of the output of one gate to
drive the input(s) of subsequent gates
Usually specified as standard loads within a single
family
e.g., an input to an inverter in the same family
May have to compute based on current drive
requirements when mixing families
Although mixing families is not usually recommended

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Fan-Out
An illustration of fan-out and the associated source
and sink currents

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Worked Example
How many 74LS00 NAND gate inputs can be driven
by a 74LS00 NAND gate outputs ?

Solution:
Refer to data sheet of 74LS00, the maximum values of
IOH = 0.4mA, IOL = 8mA, IIH = 20uA, and IIL = 0.4mA
Hence,
fan-out(high) = IOH(max) / IIH (max)=0.4mA/20uA=20
fan-out(low) = IOL(max) / IIL(max)=8mA/0.4mA=20,
the overall fan-out = fan-out(high) or fan-out(low) whichever is lower.
Hence, overall fan-out = 20

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Gate Drive Capability: Fan-Out
A logic gate can supply a maximum output current
IOH(max), in the high state or
IOL(max), in the low state
A logic gate requires a maximum input current
IIH(max), in the high state or
IIL(max), in the low state
Ratio of output and input current decide how many logic
gates can be driven by a logic gate
fan-out(high) = IOH(max) / IIH (max)
fan-out(low) = IOL(max) / IIL(max)
overall fan-out = fan-out(high) or fan-out(low) whichever is lower
A typical figure of fan-out is ten (10)

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Electronic Combinational Logic
Within each of these families there is a large variety of different devices
We can break these into groups based on the number gates per device

Acronym Description No Gates Example

SSI Small-scale integration <12 4 NAND gates
MSI Medium-scale integration 12 – 100 Adder
LSI Large-scale integration 100 – 1000 6800
VLSI Very large-scale integration 1000 – 1M 68000
ULSI Ultra large scale integration > 1M 80486/80586

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7400 Series Evolution
BJT storage time reduction by using a BC Schottky diode.
Schottky diode has a Vfw=0.25V. When BC junction becomes forward
biased Schottky diode will bypass base current.
C

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Characteristics: TTL and MOS
Remember:
TTL stands for Transistor-Transistor Logic
uses BJTs
MOS stands for Metal Oxide Semiconductor
uses FETs
MOS can be classified into three sub-families:
PMOS (P-channel)
NMOS (N-channel)
CMOS (Complementary MOS, most common)

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 TTL Circuit Operation
+Vcc

4K 1.6K 130
R1 R2 R3 A B ICQ1 Q1 Q2 Q3 Q4 Y O/P

Q 0 0 + ON OFF OFF ON 1
4
Q 0 1 + ON OFF OFF ON 1
2
D3
A 1 0 + ON OFF OFF ON 1
B Y O/P
Q 1 1 － OFF ON ON OFF 0
1 I CQ1 Q
D 3
1 D2
1K Table explaining the operation of the
R4 TTL NAND gate circuit

A standard TTL NAND gate circuit

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MOS Circuit Operation
+VDD
S
Q1
D
O/P I/P Q1 Q2 O/P
D
0 ON OFF 1
Q2
I/P S 1 OFF ON 0

Table explaining the operation of

the CMOS inverter circuit
A CMOS inverter circuit

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Comparison of Logic Families

vo

vi

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Comparison of Logic Families

speed power product = a constant

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