Basic Operation Characteristics and Parameters

DIGITAL ELECTRONIC DEVICES

COMPARING LOGIC FAMILIES
Family Propagation delay Power dissipation Speed-power
(ns) (mW) product (pWs)
74 10 10 100
74S 3 20 60
74LS 9 2 18
74ALS 4 1 4
74F 2.7 4 11
4000B(CMOS) 105 1 @ 1MHz 105
74HC (CMOS) 10 1.5 @ 1MHz 15
100K (ECL) 0.8 40 32
DC SUPPLY VOLTAGE
 TTL
 Vcc = +5V ± 10%

 CMOS
 VDD = +3 ~ +15V

 ECL
 VEE = -5.2V
LOGIC LEVEL
 TTL
5 VIH(max) 5 VOH(max)
V LOGIC V LOGIC
1 VOH 1
VIH
2.4V VOH(min)
2 VIH(min)
V unpredictable
unpredictable

0.8V VIL(max) 0.4V VOL(max)

LOGIC LOGIC
VIL VOL
0 0
O VIL(min) O VOL(min)
V Input V Output
LOGIC LEVEL (CONT.)
 CMOS
5 VIH(max) 5 VOH(max)
V LOGIC V LOGIC
VOH
VIH 1 1
4.9V VOH(min)
3.5V VIH(min)
unpredictable
unpredictable

1.5V VIL(max)
LOGIC 0.1V VOL(max)
VIL 0 LOGIC
VOL
O VIL(min) O 0 VOL(min)
V Input V Output
NOISE IMMUNITY
 Noise is unwanted voltage that is induced in
electrical signal and can be present as a threat to
the proper operation of the circuit
 The ability of a gate to ignore voltage noise is its
noise immunity.
NOISE IMMUNITY (CONT.)
 . Noise riding on VIH level

VIH

VIH(min)
2V Unpredictable region

If excessive noise causes

input to go below 2V
NOISE IMMUNITY (CONT.)
 . If excessive noise causes
input to go below 2V

VIL(min) Unpredictable region

0.8V

VIL

Noise riding on VIL level

NOISE MARGIN
 A measure of a circuit’s immunity to noise is
specified by a noise margin voltage
 The greater of the noise margin, the better of the
circuit is able to ignore or be immune to noise
signal
NOISE MARGIN (CONT.)
Input Output
 . Ideal HIGH
5
level
V

VOH(min)
HIGH level
VIH(min) noise margin

VIL(max) LOW level

noise margin
VOL(max)

Ideal LOW level

0
V
NOISE MARGIN (CONT.)
 LOW level noise margin
 The difference between the maximum LOW level
output and input voltage.
 VNL = VIL(max) – VOL(max)
NOISE MARGIN (CONT.)
 HIGH level noise margin
 The difference between the minimum HIGH level
output and input voltage.
 VNH = VOH(min) – VIH(min)
NOISE MARGIN (CONT.)
 Example:
 A TTL gates has the following actual voltage level
values: VIH(min) = 1.5V and VIL(max) = 0.6V. Assuming
its being driven by a gate with VOH(min) = 2.6V and
VOL(max) = 0.4V, determine the high and low level
noise margin?
NOISE MARGIN (CONT.)
 Solution:
 High level noise margin
 VNH = VOH(min) – VIH(min)
 = 2.6V – 1.5V
 = 1.1V

 Low level noise margin

 VNL = VIL(max) – VOL(max)
 = 0.6V – 0.4V
 = 0.2V
POWER DISSIPATION
 Power dissipation = dc supply voltage x average
supply current
 PD = VCC x ICC
+VCC +VCC

ICCH ICCL
LOW HIGH
HIGH LOW
POWER DISSIPATION (CONT.)
 So, average power dissipation
 PD(avg) = VCC ICCL + ICCH mW
 2
 The average power dissipated by each gate
 PD = PD(avg) mW
 N
 Where; N = the number of gates inside the
particular IC
POWER DISSIPATION (CONT.)
 Example:
 An IC operating from VCC = 5V having six inverters
draws a current of ICCH = 1mA and ICCL = 3mA.
Determine the average power dissipation of a single
inverter circuit.
POWER DISSIPATION (CONT.)
 Solution:
 PD(avg) = VCC * [(ICCL + ICCH) / 2]
 = 5V * [(3mA + 1mA) / 2]
 = 10mW

 PD(gate) = PD(avg) / N
 = 10mW / 6
 = 1.67mW
PROPAGATION DELAY TIME
 Important characteristics of logic circuits because
it limits the switching speed (frequency)
 When signal passes (propagates) through a logic
circuit, it always experiences a time delay
 A change in the output level always occurs a
short time, called propagation delay time.
PROPAGATION DELAY TIME (CONT.)
 If shorter propagation delay, the speed of the
circuit become higher

Delay
t
SPEED POWER PRODUCT
 A measure of the performance of a logic circuit
 SPP = propagation delay time x power dissipation
 Unit = Joule
 The smaller of the speed power product, the
performance is more better.
FAN OUT
 There is a limit to the number of load gate inputs
that a given gate can drive. This limit is called the
fan-out of the gate.
 The number of gate that may be driven by single
gate output.
FAN OUT (CONT.)
 Fan out = driver gate current capacity = IOL(max)
 current drawn per gate IIL(max)
FAN OUT (CONT.)
 Example:
 Determine fan-out if a driver gate can sink a
maximum of 30mA and load gates provide a
maximum sink of current of 6mA/gate?
FAN OUT (CONT.)
 Solution:
 Fan-out = driver gate current capacity / current drawn
per gate
 = IOL(max) / IIL (max)
 = 30mA / 6mA
 =5
 Under these condition, 5 gates each provide 6mA,
can be connected to one output, which capacity is
30mA.