“I’ve failed over and over and over again in

my life and that is why I succeed.”

1
CHAPTER
….Michael Jordan

4 Logic Gate Families

Learning Objectives
After reading this chapter, you will know:
1. Digital IC Families (DTL, TTL, ECL, MOS, CMOS)

Introduction
Digital IC Gates are classified not only by their logic operation but also by the specific logic circuit
family to which they belong. Each logic family has its own basic electronic circuit upon which more
complex digital circuits and functions are developed.

Classification of Logic Families

The logic families are mainly classified in two categories
1. Bipolar Logic Families
2. Unipolar Logic Families

1. Bipolar Logic Families: The main elements of a bipolar IC’s are Diodes and Transistors. These
are further divided into two types, based on the BJT operating mode.
(a) Saturated Mode
(b) Non-Saturated Mode
(a) Saturated Mode
In saturated logic, the transistors are driven to saturation mode. The saturated bipolar
logic families are:
1. Resistor-Transistor Logic (RTL)
2. Diode Transistor Logic (DTL)
3. Direct Coupled Transistor Logic (DCTL)
4. High Threshold Logic (HTL)
5. Transistor Transistor Logic (TTL)
6. Integrated Injection Logic (I 2 L)
(b) The Non-Saturated Bipolar Logic Families are
1. Schottky TTL
2. Emitter Coupled Logic (ECL)

2. Unipolar Logic Families: MOS devices are unipolar devices and only MOSFETs are employed in
these MOS logic circuits. The MOS logic families are
1. PMOS
2. NMOS
3. CMOS

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 Logic Gate Families

Characteristics of Digital IC’s

The above classification of digital IC’s is based on the complexity of the circuit. Some of the
important characteristics or parameters are gives as follows
1. Speed of operation
2. Power dissipation
3. Figure of merit
4. Fan out
5. Fan in
6. Current and voltage parameter
7. Noise immunity
8. Operating temperature range

1. Speed of Operation: The speed of a digital circuit is expressed in terms of propagation delay

50%
t PLH

(a) Propogation delay (t PLH )

50%
t PHL

(b) Propogation delay (t PHL )

(a & b) Propogation Delay Times

The two propagation delay times are defined as follows

t PLH: It is the propagation delay time is going from logical LOW (0 state) to logical HIGH (1 state)
t PLH: It is the propagation delay time is going from logical HIGH (1 state) to logical LOW (0 state)

2. Power Dissipation: Any digital circuit requires some power for operation. This is the amount of
power dissipated in an IC. It is determined by the current an IC draws from the Vcc supply. It is
expressed by VCC × ICC . Specified in mW.

3. Figure of Merit: The figure of merit is defined as the product of speed and power. The speed of
logic circuit is specified terms of propagation delay, so the figure of merit is specified in mW.
Figure of Merit = Propagation Delay × Power

4. Fan Out: Fanout is the maximum number of similar logic Gates that a Gate can drive without
degrading voltage levels. High Fanout is advantageous because the need for additional drivers to
drive more Gates is less.

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 Logic Gate Families

5. Fan In: It is defined as the number of inputs that can be connected to a gate. For example 7400
represents two input NAND Gate, therefore fanin of 7400 is 2.

6. Current and Voltage Parameter: Current and Voltage parameters are very important in designing
a digital system. Figure show the current and voltage in the two logic states. VIH (min ) − High
level input voltage
IOH IIH
1
1 VOH VIH
HIGH

IOL IIL
0
0 VOL VIL
LOW

Current and Voltage in Two Logic States

 It is the minimum voltage level required for logic 1 as an input. Below the minimum level will
not be accepted as a HIGH by the logic circuit.
 VIL (max) − Low level input voltage
 It is the maximum voltage level required for logic 0 at an input. Any voltage above this level
will be considered as HIGH input.
 IOL (max) − Low level output Current
 It is the maximum current level at a logic circuit output in the logical 0 states under the
defined load condition.
 IIH (min) − High level input Current
 It is the minimum current that flows into an input when a specified high level voltage is
applied to that input.
 IIL (max) − Low level input current
 It is the maximum current that flows into an input when a specified low level voltage
is applied to that input.
 IOH − High level output current
 It is the minimum current that flows from an output in the logic 1 state under specified load
condition.
 IOL (max) − Low level output current
 It is the maximum current that flows from an output in the logic 0 state under specified load
condition.

7. Noise Immunity: The input and output levels of a digital circuit is specified by a voltage level
figure shows the input and output voltage levels. Some unwanted voltage might be induced due
to electric and magnetic fields, known as noise. It may cause the voltage at the input of a logic

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 Logic Gate Families

circuit to drop below VIH or above VIL and may produce undesired operation. Noise immunity is
maximum noise voltage that may appear at the input of a logic gate without changing the logical
state of its output.
State 1 noise margin (VNH ) = VOH − VIH
State 0 noise margin (VNL ) = VIL − VOL

Logic 1 VOH (min)

Logic 1
VNH

VlH (min)
voltage

VlL (max)
VNL
Logic 0
Logic 0 VOL (max)

Input Output Voltage Level for Noise Immunity

8. Operating Temperature: All IC Gates are semiconductor devices. They are temperature sensitive
by nature. The operating temperature ranges of an IC vary from 0°C to + 70°C for consumer and
industrial application, temperature ranges from −55°C to + 125°C for military applications.

Current Sourcing and Current Sinking Logic

Logic families can be categorized depending upon the flow of current from the output of one logic
circuit to the input of another circuit. Current sourcing and current sinking logic Gates are illustrated
in figure (a) and (b).
IOL IOL

1 1
IIL IIL
2 2
IIH IIH
3 3
IIH IIH

(a) To Other Current Sourcing (b) To Other Current Sinking

When a standard Gate output is high, the output current IOH from Gate 1, will drive the Gates 2 and
Gate 3, hence the Gate 1 acts as a current source. Here the input circuitry of Gate 2 is tied to Gate 1. In
other words, in the LOW state the circuit output that drives the input of Gate 2 must be able to sink a
current.

Resistor – Transistor Logic (RTL)

 Earliest logic family to be integrated
 Become absolute now because of its simplicity & for historical reasons.
 Basic RTL Gate is a NOR Gate.

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 Logic Gate Families

VCC
VCC
RC RC
output R B = 450 Ω
G1 VCC
R C = 640 Ω
V0 RB RC VCC = 3.6 V
V1 T1 V2 T2
RB RB G2
RB VCC

RC

Gn
Input Gates RB

Load Gates
If V1 &V2 both low If either of input is high (let T1 )
↓ ↓
T1 & T2 are cut-off Then T1 → saturation & T2 → cutoff
↓ ↓
Output is high All current passes through T1 & output is low i.e. , Vo → low

Loading Consideration
If all the inputs to the Gate are low, the output is high & if the Gate is not driving any other Gate, i.e.,
no load is connected, the output voltage will be slightly less than VCC (there is voltage drop across
the common collector resistor due to Ico of T1 &T2). When N similar Gates are being driven, as shown
above the load will be equivalent to a resistor of value 450/N in series with a voltage source of 0.8 V
(being the voltage b/w the Base & Emitter of a transistor in saturation).
3.6 V
640 V
Load

ICO ICO Vo
Load
450/NΩ
T1 T2

0.8 V

Base current for each load transistor

3.6 − 0.8 1 2.8
IB = [ 450] × =
640 + N 640 N + 450
N

Diode – Transistor Logic (DTL)

 More complex then RTL but because of its greater fan-out & improved noise margins has
replaced RTL.
 Main Disadvantage → Slower Speed → Because of this it was modified & emerged as TTL
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 Logic Gate Families

VCC
VCC
IL
R RC DA D1 D2
A P
DA D1 D2 VCC
B T D1 D2
DB P IL
RB P
C DA
DC
Load Gates

 DTL Gate is a NAND Gate If all input at high state

 If any input is in the low state (let DA ) DA , No diode conduct
conduct through resistor R. ↓
↓ No current flowing from VCC through R
∴ VP = VA + 0.7 should be sufficient to drive T in saturation.
Now if VP is such that it keep T in cutoff ∴ The output of T is VCE sat.
Then output of T is VCC ↓
For this VP should be For this VP should be
VP = 0.7 + 0.7 + 0.6 VP = VD1 + VD2 + VBE (sat)
= VD1 + VD2 + VBE (cutoff) = 0.7 + 0.7 + 0.8
= 2.0 V = 2.2 V

Direct-Coupled Transistor-Logic (DCTL)

VCC

Output
A B C

(Basic DCTL Circuit)

 More economically constructed.

 Input connections are made directly to the base, so it known as Direct-Coupled-Transistor-Logic
(DCTL) Gates.
 Above ckt is a NOR Gate or say DCTL NOR Gate.

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 Logic Gate Families

Vo
5V
VCC

Vi
0.1

0.6 0.8 Vi
Input-output characteristic of DCTL
(VTL) (at no load)
Noise Margin = NMH = VoH − VIH
= 5 − 0.8
= 4.2 V
NML = VIL − VoL
= 0.6 − 0.1
= 0.5

Emitter Coupled Logic (ECL) Circuits

An ECL OR/NOR Gate is shown in figure. The Emitter follower outputs provide the OR logic function
and its OR complement.
VCC = +5 V

R C1 R C2
T5
T4 (A+B)
OR Output
T1 T2 T3 VR
(A+B)′
NOR Output

Re R

−5.2 V
Two Input ECL OR-NOR Gate

Because of low output impedance of the Emitter follower and the high input impedance of the
differential amplifier input, high fan-out operation is possible. In this type of circuit, saturation is not
possible. The lack of saturation results in higher power consumption and limited voltage swing (less
than 1 V), but it permits high frequency switching.
The VCC pin is normally connected to ground and the VEE pin is connected to −5.2 V from the power
supply for best operation.
In the positive logic: 1 ⇒ High ⇒ −0.9 V
0 ⇒ Low ⇒ −1.7 V
In the negative logic: 1 ⇒ High ⇒ −1.7 V
0 ⇒ Low ⇒ − 0.9 V

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 Logic Gate Families

When both inputs are LOW (−1.7V for positive logic), T1 and T2 are at −1.7 V and base of T3 is at
−1.3 V. Therefore, T3 is more forward biased than T1 and T2 . Once T3 is ON, the Emitter voltage of T3
becomes −2.1V, making their base emitter junctions reverse biased. As a result T1 and T2 are OFF.
When T1 and T2 are OFF, the current flowing through R C1 is only the current through the base of T4 .
The value of R C1 is adjusted that the voltage across it is 0.1 V. This makes emitter of T4 as
(−0.1 V) + (−0.8 V) = − 0.9 V and we see that the NOR output is HIGH. On the other hand, as T3 is
ON, large current flows through R C2 . The value of R C2 is so adjusted such that when T3 is ON, the
voltage drop across R C2 is equal to 0.9 V. Therefore Emitter of T5 is (−0.9) + (−0.8) = −1.7 V, and
we see that OR output is LOW.
When input A is LOW and input B is HIGH (−0.9 V ), T2 is more forward biased than T3 and hence its
ON giving Emitter voltage −1.7 V (−0.9 − 0.8). This makes T1 and T3 OFF. Now the voltage drop
across R C1 and R C2 becomes 0.9 V and 0.1 V respectively. This given the NOR output LOW (−1.7 V)
and OR output is HIGH (−0.9 V). By similar analysis, we find that the NOR output is LOW and OR
output is HIGH whenever either or both input are HIGH.

Integrated Injection Logic (𝐈 𝟐 L)

This is another bipolar transistor based digital integrated circuit technology. It provides extremely
compact monolithic structure. No resistors are employed which occupy sufficient space on the chip
in case of other logic families. So very high densities of integration are possible, nearly ten times that
of the TTL. It consumes very low supply current and is characterized by lowest power-speed
product. But still it is usually not employed for producing wide range of functions in SSI or MSI
integrated circuits because it possesses extremely poor noise margin and voltage swing. So l2 L
technology has been employed only for producing complex LSI and VLSI functions like that of
microprocessors etc.
Figure shows l2 L NAND Gate. The NAND Gate is simply an inverter with inputs connected directly
together at the inverter input. When either or both inputs are LOW, input(s) sink current and Q 2 is
OFF. When both inputs are high, Q 2 is turned ON, making the output low.
VCC
+VCC

Q1
Output
A
Q2
B

𝐈 𝟐 𝐋 𝐍𝐀𝐍𝐃 𝐆𝐚𝐭𝐞

Truth Table for 𝐈 𝟐 𝐋 𝐍𝐀𝐍𝐃 𝐆𝐚𝐭𝐞

A B Q2 Output = AB
0 0 OFF 1
0 1 OFF 1
1 0 OFF 1
1 1 ON 0

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 Logic Gate Families

Metal – Oxide Semiconductor Field-Effect Transistors (MOSFET) Gates

MOS

Enhancement Type Depletion Type

NMOS PMOS CMOS NMOS PMOS CMOS

 MOSFET is a three-terminal device, with only one type of carrier involved in current conduction,
this it is a unipolar device.
 Current in a MOSFET depends on the control of the majority carriers, which are available in a
channel, by an applied electric field. So the device behaves as a voltage-controlled current source.

Advantage of MOSFET over BJT

 Small Size: MOSFET occupies typically less than one-third the area of a BJT.
 Require Fewer & less Complex step in the Fabrication: Due to this the ckt using MOSFETS are less
expensive to manufacture & have higher density per chip area.
 Low Power Requirement: MOSFET devices dissipate much less power during dynamic operation
& almost negligible amounts under static conditions.

Major Limitation of MOSFET

(a) Low current-driving capability results in relatively low speed of operation due to the large
lumped capacitance at the output node. High current loads cannot be driven without
degradation in performance. Special MOSFETs at slightly lower speeds are available for such
high-power loads.
(b) In a n-type MOS transistor the majority characters are electrons. A positive voltage applied on
the Gate with respect to the substrate enhances the number of electrons in the channel. (The
region immediately under the Gate) & hence increase the conductivity of the channel.
(c) For Gate voltages less than a threshold value denoted by Vt . The channel is cut-off, thus causing
a very low Drain-to source current.
(d) The operation of P-type transistor (i.e., PMOS) is analogous to the NMOS transistor, with the
exception that the majority carries are holes & the voltages are negative w.r.t the substrate.
(e) It is possible to make n-devices that conduct when the Gate voltage is equal to the source
voltage. Or requires a positive difference between Gate & source voltages to bring about
conduction (negative for P-devices)

Those devices that are normally cutoff (i.e., non-conducting) with zero Gate bias (Gate voltage-
Source voltage) known as enhancement mode devices, whereas those devices that conduct with
zero Gate bias are called depletion-mode devices.
The n-channel MOSFET & P-channel MOSFET are the duals of each other. That is the voltage
polarities required for correct operation are the opposite.
The most important parameter that characterizes the switching behaviour of an MOS device is the
threshold voltage Vt . This is the voltage at which an MOS device begins to conduct. (“turn-on”)
The threshold voltage VT depends on the doping concentration of the drain, the source, the substrate
& the capacitance between the Gate & the body.
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 Logic Gate Families

MOS Transistor
 MOS transistor is termed a majority - carriers devices in which the current, in a conducting
channel b/w source & drain, is modulated by a voltage applied to the Gate.
 In n type MOS i.e., NMOS majority electrons carriers → e−
PMOS→ Holes.
 In NMOS positive voltage applied on the Gate w.r.t the substrate enhances the no. of electrons in
the channel & hence increase the conductivity of the channel (in PMOS +ve voltage is applied
w.r.t substrate).
 For Gate voltages less than a threshold value (Vth ), the channels is cutoff, thus causing a very low
drain to source current.

Those device that are normally cutoff
(i.e., Non conducting) with zero gate
bias are called
Enhancement-Mode Devices
IDS
Those device that conduct with
zero Gate bias are called
Depletion-Mode Devices
Note: Gate bias(VGS )
↓
(Gate Voltage-Source Voltage)
IDS

VGS
0 +Vth Vgs
−Vth 0
(n-channel Enhancement)
(n-channel Depletion)

−Vtp Vtp
VGs VGs
0 0

Ids IDS

VDD VDD

D
D Vout G
G S
Vin Vout
S D
G
Vin
(Resistor Loaded NMOS Inverter) S
(Saturated Enhancement Loaded
NMOS Inverter) Saturated Enhancement
Loaded NMOS Inverter

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 Logic Gate Families

VGG VDD VDD

D G D
G S S
Vout Vout
D D
G G
Vin S Vin
S

(Linear Enhancement Loaded (Depletion NMOS Loaded

NMOS Inverter) NMOS Inverter)

VDD
Generic Pull-Up Device A
Load
F
B
VA D Vout
D VB
G S G Parallel NMOS Pull-Down
S

(2-input NMOS NOR Gate)

VDD VDD
D Generic Pull-Up
Device
S Load
Vout
A D D D Vout
B A
S S S
Series NMOS
D
B pull down
S
(Two-Input Depletion
Loaded NMOS NOR Gate)
(2 Input NMOS NAND Gate)

VDD
VDD

Load
Load
VR
VD VB Vt

VNOR
(NMOS OR/NOR Gate)

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 Logic Gate Families

VDD VDD

Load Load A
F = A+B
B
VA VAND F̅ = ̅̅̅̅̅̅̅
A+B
A
VB F = AB
B
̅̅̅̅
F̅ = AB
Vt
VNAND

VDD VDD

Load Load

Vout = ̅̅̅̅̅̅̅̅̅̅̅
AB + CD Vout = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(A + B)(C + D)
A C
A B
B D

C D
(Four Input NMOS AND- OR-NOR Gate)
(AOI)

(Four Input NMOS OR- AND-Inverter Gate)

(AOI)

NMOS Transmission gates (pass Gates)

VDD VDD

Load
Vout
VIn=VDD Active NMOS device
provide a highly
conductive path b/w
Vout & Ground
In Essence, the Active NMOS “Transfer”
the Ground Voltage to the Output.
Load
Vin=low
Vout
Cutoff NMOS device
separate o/p & ground
by an open Ckt
i.e., When Gate voltage is low. The
NMOS switch is off & an open ckt
exists between O/P & Ground.

VDD
VDD
NL
VEN −enable input
Vout NT VEN = high →then Vin ≈Vout
V′out
ND Vin VEN = low → Vin = Z
Vin
Z is floating & un driven
VEN
Transmission Gate NMOS Device

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 Logic Gate Families

IA NTA IMUX
VA VMUX
IB NTB
VB
IC NTC
VC
ID NTD
VD

VENA VENB VENC VEND

NMOS Transmission Gate used in a Multiplexer

Operating Regions of MOS Transistor

In MOS type Gates, we make use of two similar operating regions in the MOSFETs.
 The cutoff region is the same as that for a bipolar transistor: Under this condition, there is very
high impedance between the Drain and the Source terminals of the MOSFET.
 The ohmic region is analogous to the saturation region of a bipolar transistor: In this state, there is
a relatively low resistance between the MOSFETs Drain and Source.
Bias requirements for n and p channel enhancement mode MOSFETs
OFF ON
VDD VDD

D D

G G
n-Channel + +
VGS(th) = +1.5V VGS S VGS S
− −

VGS < VGS(th) VGS ≥ VGS(th)

VGS = 0 VGS = +2V(appr)

VDD VDD

D D

p-Channel G G
VGS(th) = −1.5V + +
VGS S VGS S
− −

VGS > VGS(th) VGS ≤ VGS(th)

VGS = 0 VGS = −2V(appr. )
Summarizes the bias requirement for n and p channel enhancement mode MOSFETs.

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 Logic Gate Families

CMOS Inverter
The operation of a CMOS inverter, or any other CMOS Gate, depends on arranging the bias
conditions of each complementary pair of transistors. These transistor are so arranged such that
they are always in opposite states. Whenever Q1 is ON, Q 2 is OFF and vice versa. Fig. shows a CMOS
inverter.
VSS

Q1
PMOS
Input
Output
A ̅
A
Q2
NMOS

CMOS inverter

When inputs is LOW, the Gate voltage of Q 2 is the same as its Q1 voltages: Vgs2 = 0. So Q 2 is OFF and
Q1 is ON. This condition connects the output to +VSS through the on resistance (small value), of Q1
the result is HIGH output.
When a HIGH is applied to the input, MOSFET Q1 is-OFF and the n channel MOSFET Q 2 , is ON. This
condition connects the output to ground through the ON resistance of Q 2 , resulting in a low voltage.
Table shows the summarized operation of CMOS inverter Gate.
Truth Table of CMOS Inverter Gate
Input MOSFET Output
P channel N channel
A Q1 Q2 ̅
A
L ON OFF H
H OFF ON L

CMOS NAND GATE

Figure shows a CMOS NAND Gate with two inputs along with the arrangement of the
complementary pairs (N channel and P channel MOSEFT). The operation of the CMOS NAND Gate is
as follows.
Case 1: When both inputs are LOW, Q1 and Q 2 are ON and Q 3 and Q 4 are OFF. The output is pulled
HIGH through on resistance of Q1 and Q 2 in parallel.

Case 2: When input A is LOW and input B is HIGH, Q1 and Q 4 are ON and Q 2 and Q 3 are OFF. The
output is pulled HIGH through the on resistance of Q1 .

Case 3: When input A is HIGH and input B is LOW, Q1 and Q 4 are OFF, and Q 2 and Q 3 are ON. The
output is pulled HIGH through the on resistance of Q 2 .

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 Logic Gate Families

Case 4: When both inputs are HIGH, Q1 and Q 2 OFF, and Q 3 and Q 4 are ON. In this case, the output
is pulled LOW through the on resistance of Q 3 and Q 4 in series to ground. The Table shows
the summarized operation of CMOS NAND Gate.
Vss

Q1 Q2
PMOS PMOS
y

A Q3
NMOS

B Q4
NMOS

CMOS NAND Gate

Truth Table of CMOS NAND Gate

MOSFETs
Input Output
P channel N channel
A B Q1 Q2 Q3 Q4 Y
L L ON ON OFF OFF 1
L H ON OFF OFF ON 1
H L OFF ON OFF ON 1
H H OFF OFF ON ON 0

CMOS NOR Gate

Figure shows a CMOS NOR Gate with two inputs. The operation of a CMOS NOR Gate as follows
Case 1: When both inputs are LOW, Q1 and Q 2 are ON and Q 3 and Q 4 are OFF. The output is pulled
HIGH through on resistance of Q1 and Q 2 in series.
Case 2: When input A is LOW and input B is HIGH, Q1 and Q 3 are ON and Q 2 & Q 4 are OFF. The
output is pulled LOW through on resistance of Q 4
VSS

A Q1
PMOS

B Q2
Y
Q3 Q4
NMOS NMOS

CMOS NOR Gate

Case 3: When input A is HIGH and input B is LOW, Q1 and Q 3 are OFF and Q 2 and Q 4 are ON. The
output is pulled LOW through on resistance of Q 3 .

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 Logic Gate Families

Case 4: When both inputs are HIGH, Q1 and Q 2 OFF and Q 3 and Q 4 are ON. In this case, the output
is pulled LOW through the on resistance of Q 3 and Q 4 in parallel to ground.

Table shows the summarized operation of CMOS NOR Gate.

Truth Table of CMOS NOR Gate
MOSFETs
Input Output
P channel N channel
A B Q1 Q2 Q3 Q4 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF ON OFF 0
1 0 OFF ON OFF ON 0
1 1 OFF OFF ON ON 0

Important Points:
 HTL is a modified form of DTL and IIL is a modified form of DCTL.
 Because of high package density MOS and I 2 L logic Gate families are used for Large Scale
Integration (LSI) functions.
 TTL, ECL and CMOS are used for Medium Scale Integration (MSI) or Small Scale Integration (SSI).
 Each logic Gate family is identified with a series number. For example TTL family available in
74/54 series. CMOS IC’s usually designated with 4000 series and ECL family with 10000 series.
 RTL, DTL, ECL and I 2 L Logic families uses bipolar transistors. Hence these families are called
“Bipolar logic Gate families”.
 MOS and CMOS families uses unipolar transistors called Metal- Oxide Semiconductor Field- Effect
Transistors (MOSFET). Hence, these families are called “Unipolar logic Gate families”.
 ECL has ultra-fast switching speed and low logic swing.
 The temperature range of 74-series of TTL logic Gate family is 0℃ to 80℃. This series of IC’s is
used for commercial applications.
 The temperature range of 54-series of TTL logic Gate family is −55℃ to 125℃. This series of IC’s
is used for “Military applications”.
 When the outputs of logic gates are connected together additional logic functions are performed.
This is known as “Wired logic”.
 When the outputs are available in complement as well as un-complement form it is referred to as
complementary outputs. This eliminates the need of using additional inverters.
 Passive Pull - Up: In a bipolar logic circuit, a resistance R c used in the collector circuit of the
output transistor is known as passive pull-up.
 Active Pull - Up: In a bipolar logic circuit a BJT and diode circuit used in the collector circuit of the
output transistor instead of R c is known as active pull-up. This is available in TTL family.
 The advantages of active pull- up over passive- pull up are increased speed of operation and
reduced power dissipation.
 Open Collector Output: In a bipolar logic circuit if nothing is connected at the collector of the
output transistor and this collector terminal is available as IC pin, it is known as open-collector
output.
 Tri - State Logic: In the tri - state logic, in addition to low impedance 0 and 1 there is a third state
known as the high-impedance state. When the Gate is disabled it is in the third state.

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 Logic Gate Families

 In TTL logic Gate family three different types of output configurations are available: They are
open collector output type, Totem-pole output type and Tri-state output type.
 The advantages of open-collector output are wired-logic can be performed and loads other than
the normal Gates can be used.
 The tri- state logic devices are used in bus oriented systems.
 If any input of TTL circuit is left floating, it will function as if it is connected to logic 1 level.
 The supply voltage range of 74-series is 5 ± 0.25 V and for 54-series is 5 ± 0.5 V.
 Negative supply is preferred in ECL family because, the effect of noise present in the supply line
is reduced considerably and any accidental short- circuiting of output to ground will not damage
the Gate.
 MOS logic is mainly used for LSI and VLSI applications because the silicon chip area required for
fabrication of a MOS device is very small.
 The fan-out of MOS logic Gates is very high because of their high input impedance.
 If any unused input terminal of a MOS gate is left unconnected, a large voltage may get induced at
the unconnected input which may damage the Gate.

Different Versions Available in TTL Logic Gate Family

1. 74/54 L : Low-power
2. 74/54 H : High-power/High-speed
3. 74/54 LS : Low-power schottky
4. 74/54 S : schottky
5. 74/54 LS : Low- Power schottky
6. 74/54 AS : Advanced schottky
7. 74/54 ALS : Advanced Low –Power schottky
The supply voltage required for ECL logic family is −5.2 V ± 10%

Comparison of Different Logic Gate Families

DTL TTL ECL CMOS PMOS

Fan-out 8 10 25 50 20
Propagation Delay 30 n sec 10 n sec 4 n sec 70 n sec 300 n sec
Power Dissipation 8-12 mW 12-22 mW 40 mW 0.01 mW 0.2-10 mW
Noise Margin(min.) 700 mV 400 mV 200 mV 300 mV 150 mV

 Fastest Logic Gate Family is ECL. It is also called Current Mode Logic.
 Slowest Logic Gate Family is CMOS.
 The Logic Gate Family, which consumes least power CMOS.
 The Logic Gate Family, which consumes maximum power ECL.
 The Logic gate Family, which is having highest fan out CMOS.
 In CMOS circuits NMOS transistor conducts if the Gate to source voltage is more positive where
as PMOS conducts if Gate to source voltage is more negative.
 NMOS is faster than PMOS.
 In tristate logic, in addition to two low impedance outputs 0 and 1, there is third state known as
“High Impedance State”.
 Standard 2 input TTL NAND Gate
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 Logic Gate Families

Vcc

4 kΩ 1.4 kΩ 4 kΩ

A
Q2
B Q1 y
Q3
1 kΩ

Y = ̅̅̅̅
AB

 2 – Input NAND gate Totem-pole out configuration

VCC

4 kΩ 1.6 kΩ 130 Ω

Q4
A D
Q2
B Q1

Q3
̅̅̅̅
y = AB
1k Ω

 The diode “D” is used to keep the transistor Q4 in OFF State when Q3 is ON State.
 2-Input NAND Gate with open collector output configuration.
VCC VCC

4 kΩ 1.6 kΩ RL

A ̅̅̅̅
y = AB
Q2
B Q1
Q3

1kΩ

 Gates with open collector output can be used for Wired − AND operation.

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 Logic Gate Families

Vss

A
OC y
B
Y = AB. CD = (AB + CD)
C
D OC

 Wired –AND operation is equivalent to AND – OR – INVERT

 Tristate output configuration –TTL circuit.
Control Unit A Y
0 X Z
1 0 1
1 1 0
Vcc

R R R

Q4
A Q5
Q2
B Q1 R
Q3 y=A ̅
Tristate invertor
R

R R

Q7
C Q6 Q8
R

 NMOS Gate Circuits

+VDD +VDD +VDD

N
N N
y y
y
A
A+B
Y = ̅̅̅̅̅̅̅

AB
Y = ̅̅̅̅

A B N
A N ̅
Y=A N N
B
N

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 Logic Gate Families

 CMOS Gate Circuits

+VDD +VDD +VDD

A P
P P
P
B P y
A y y
Y = ̅̅̅̅
AB
Y=A Y A N
B
N N N= A + B
B N
GND

 Similar to open collector output in TTL, open Emitter output are available in ECL. The output of
two or more ECL Gates can be connected to get additional logic without using additional
hardware. “Wired – OR” operation is possible with ECL circuits.
 “Wired –OR” operation is equivalent to “OR – AND-INVERT”.
 If any input of an ECL Gate is left unconnected, the corresponding E-B junction will not be
conducting .Hence it acts as if a logical 0 level voltage is applied to that input. i.e., in ECL IC’s all
unconnected/floating inputs are treated as logical Low.
A
(A + B + C + D)
B = ( A + B)(C + D)
y
C
D

Comparison of CMOS and TTL Families

Parameter CMOS TTL
Silicon Gate Metal Gate 74 74LS 74AS 74ALS
CMOS CMOS
VIH (min) 3.5 3.5 2.0 2.0 2.0 2.0
VIL (max) 1.0 1.5 0.8 0.8 0.8 0.8
VOH (min) 4.9 4.95 2.4 2.7 2.7 2.7
VNH 1.4 1.45 0.4 0.7 0.7 0.7
VNL 0.9 1.45 0.4 0.3 0.3 0.4
Propagation delay (ns) 8 105 10 10 1.5 4
Power per Gate 0.17 0.1 10 2 8.5 1
Speed power product or 1.4pJ 10.5pJ 100pJ 20pJ 12.8pJ 4 pJ
figure of merit
Input connection Input cannot be left open. It has to be Input can be left open. It is
connected to 0, or to VDD or to the treated as logic high input.
Another input

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 Logic Gate Families

Power connection Very less, but increases with increase More than CMOS. It is
in switching speed. constant, does not depend
on switching speed.
Fanout Fanout is more than TTL typically 50. Fanout for TTL is 10.
Noise More susceptible to noise. Less susceptible to noise.

Advantages and Disadvantages of Major Logic Families

TTL Gates
Advantages:
 It is the fastest saturating logic family. TTL Gates are available in the form of high speed, high
speed schottky, low power schottky and a variety of other types.
 It has good noise immunity. Typical noise-margin is about 0.4 V.
 Power dissipation is in the mega Watt range.
 Compatible with other logic families.
 Commercial and military versions of TTL Gates are available.
 More fan out; can drive upto 10 Gates.
 Low output impedance for higher/low states.

Disadvantages:
 Noise immunity is not very high so it cannot be used in areas where large noise voltages prevail.
 Because of isolation problems, VLSI circuits are not possible.
 Power dissipation is much higher than MOS Gates.
 Cost is higher than NMOS/CMOS, when MSI and LSI Gates are considered.
 It generates transient voltages at switching instants.
 Wired OR capability is not possible for the standard TTL.

ECL Gates
Advantages:
 Since transistors operate in the active region, highest speed among all logic families.
 Complementary outputs are available (OR-NOR).
 Outputs can be tied together to give the wired OR function.
 Parameters do not vary much with temperature.
 Typical supply voltage is −5.2 V.

Disadvantages:
 Very low noise margin.
 Highest power dissipation among all logic Gates.
 Capacitive loading limits fan out.
 Higher cost.
 VLSI design is difficult, as ECL Gates require resistors also to be fabricated.

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 Logic Gate Families

NMOS
Advantages:
 Less number of diffusions required. Hence cost per Gate is the lowest.
 Very low power dissipation (nW)
 Variability in power supply (from 5-15 V) possible.
 Large fan out capability (20 gates)
 Very high noise margin. Suitable for use in industrial atmosphere.
 MOS circuits are used as capacitors. They can also be used as resistors.

Disadvantages:
 MOS transistors are also capacitors. Hence speed of operation is lowest.
 Large propagation delay per Gate.
 Higher power dissipation than CMOS Gates.

𝐈 𝟐 L Gates
Advantages:
 Since l2 L Gates are made up of BJTs, they have high speed of operation.
 Very low power supply requirement.
 Low power dissipation.
 Process steps required are less. Hence cost per Gate is low.
 Several functions possible on the same chip

Disadvantages:
 Very low voltage swing, only from VBE (0.7 V)to VCE (0.2 V).
 Lower packing density than NMOS.
 Lower noise margin.
 External resistance required for proper functioning.
 l2 L technology, at present is inactive.

CMOS Gates
Advantages:
 Extremely large fan-out capability (>50).
 Lowest power dissipation of all gates (a few nano Watt).
 Very high noise immunity and noise margin.
 Lower propagation delay than NMOS.
 Large logic swing.
 Single power supply required.
 Temperature stability in excellent.

Disadvantages:
 Increased cost due to additional processing steps. But this is being rectified.
 Packing density less than NMOS.
 MOS chips must be protected from acquiring static changes by keeping the leads shorted.

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 Logic Gate Families

Comparison of Different Digital IC Families

Logic family

Parameter TTL
RTL DTL l2 L HTL ECL CMOS
Standard Schottky
Basic Gate NOR NAND NOR NAND NAND NAND OR-NOR NAND-NOR
Depends
Fan Out 5 8 on injector 10 10 10 25 50
current
Power
(6nW−70
dissipation 12 8-12 55 10 19 40-55 0.01
μW)
(in mW/gate)
Noise
Nominal Good Poor Excellent Very good Very good Poor Very good
Immunity
Propagation
12 30 25-250 90 10 3 2 70
Delay (in ns)
Speed-Power
Product (FOM) 144 300 <1 4950 100 57 100 0.7
(in pj)
CLK Rate(in
8 72 --- 4 35 125 >60 10
MHz)
Available
High Fairy High LSI only Nominal Very High Very High High High
Function

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