Operational Amplifiers and Its Applications: Learning Objectives

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6
CHAPTER
Operational Amplifiers and

Its Applications
Learning Objectives
After reading this chapter, you will know:
1. Differential Amplifiers
2. Analysis of Differential Amplifier
3. Common Mode Rejection Ratio (CMRR)
4. Operational Amplifier Circuits
5. Astable Multivibrator (Square Wave Generator)
6. Zero-Crossing Detector
7. The 555 Timer
Differential Amplifiers/ Instrumentation Amplifier

Differential Amplifier is the base building block of the Operational Amplifier called Op-Amp in short
form
VCC
R C1 R C2
I C1 I C2
V01 V02
I B1 I B2
Q1 Q2
VO Rs Rs
+ +
RE
V1 V2
− −
−VEE
There are two types of Input Signals to the DA

1. Differential Mode: Input signal is the difference between the input voltage V1 & V2
Vd = V2 − V1
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Operational Amplifiers and Its Applications
2. Common Mode: It is average of the two input voltages.

V1 + V2
Vc =
2
V2 and V1 can be expressed as a function of Vd and Vc
Vd = V2 − (2Vc − V2 )
Vd
V2 = Vc + … … … … … … (1)
2
Vd
V1 = Vc − … … … … … … (2)
2
If V1 = V2 , VD = 0, VC = V1 = V2
If V1 = −V2 , VD = 2V1 = −2V2 , VC = 0
Analysis of Differential Amplifier

Differential Mode: If the amplifier of the two transistor Q1 and Q 2 is A1 and A2
The output Vo = A1 V1 + A2 V2
Vd Vd
From equation 1 and 2 V1 = VC − & V2 = Vc +
2 2
Vd Vd
Vo = A1 (VC − ) + A2 (VC + )
2 2
Vd
Vo = VC (A1 + A2 ) + (A2 − A1 )
2
Vo = ACM Vc + ADM Vd………………(3)
Where ACM = A1 + A2 & → Common mode gain
A2 − A1
AM = → Differential mode gain
2
When V1 = −V2 , ± means two input voltage are antiphase
Vd = 2V2 = −2V1 and VC = 0 and we obtain the differential mode gain (VC = 0)ADM
When V1 = V2 that is in phase, Vd = 0, Vc = V1 = V2 and we obtain the common mode gain ACM
Small-signal Mode for Purely Differential Mode Input:

From equation (1) and (2)
V1 = Vd ⁄2 and V2 = −Vd ⁄2 because common mode voltage VC = 0
V01 V02
+ +
Vd rπ Vd
Vπ Rc Rc rπ Vπ −
2 g m Vπ 2
− g m Vπ −
i1 i2
Vx
RE
Vd −Vd
Here Vπ = Here Vπ =
2 2

Assume Yo > R e
By symmetry i1 = −i2 ; g m1 = g m2 = g m , rπ1 = rπ2 = rππ
For purely differential mode signal Vx = 0
Vd
V01 = −g m R c
2
Vd
V02 = g m R c
2
Vd Vd
V0 = V01 − V02 = −g m R c − g m R c = −g m R c Vd
2 2
Now ADM = Vo /Vd for purely differential mode input means VC = 0
So ADM = −g m R c
Small Signal Mode for Purely Common Mode Input

V1 = V2 = Vc , Vd = 0
V01 V02
+ +
VC VC
rп Rc Rc rπ
g m Vπ2
− g m Vπ −
i1 i2
Vx
RE
i2 = i2 → Vx = (i1 + i2 )R E = 2i2 R E = 2i1 R E

On solving the different circuit using KVL, we can get
Vo (V01 + V02 )/2 −g m R c
ACM = = =
Vc Vc 1 + 2g m R E
As the same signal V1 and V2 are applied to Q1 and Q 2 , V01 and V02 are 180° out of phase with ACM
−RL
for minimum A + ACM , R E is mode large then ACM ≈ 2RE
Common Mode Rejection Ratio (CMRR)

Our interest is the differential one & the common mode output zero. This is expressed as a ratio
called CMRR & defined as
ADM
CMRR =
ACM
CMRR should be high as possible and this can be when ACM is low and ADM is high
−g m R L
CMRR = = 2g m R E
−R L /2R E

Different Input, Output Combinations

1. Dual input, Dual (balanced)output
2. Dual input, Single ended (unbalanced) output
3. Single ended input, Dual (balanced) output
4. Single ended input, Single ended (unbalanced) output
Configuration Voltage Gain Input Resistance Output Resistance
R i1 = R i2
Rc
1. Dual input, Dual output AD = = 2βac re R 01 = R 02 = R c
re
= 2hie
RC R i1 = R i2
2. Dual input, Single output AD = Ro = Rc
2re = 2βac re
Rc
3. Single input, Dual output AD = R i = 2βac re R o1 = R o2 = R e
re
RC R o1 = R C
4. Single input, Single output AD = R i = 2βac re
2re
R o → Output resistance
R i → Input resistance
VT
re =
IEQ
Operational Amplifier
An operation amplifier is a very high gain amplifier having very high input impedance and low
output impedance. The basic circuit is made using a difference amplifier having two inputs
(Inverting and Non Inverting) and at least one output.
+VCC
Inverting input −
Op-Amp Output
Non inverting +
input −VCC
Basic OP-AMP
Ro
Vd Ri Ad Vd Vo Vd Ad Vd Vo
(a) (b)
AC Equivalent of Op-Amp Circuit: (a) Practical; (b) Ideal
A signal applied to non-inverting (+) input produces an output that is in phase with the signal
applied, while an input to the inverting input results in an opposite polarity output. The ac
equivalent circuit of the Op – Amp is shown in above figure. The signal applied between input

terminals sees an input impedance, Ri, that is typically very high. The output voltage is equal to
amplifier gain times the input signal taken through the output impedance, Ro, which is typically very
low.
The Ideal Op – Amp:

An ideal Op-Amp would exhibit the following electrical characteristics:
1. Infinite voltage gain A
2. Infinite input resistance R i so that almost any signal source can drive it and there is no loading
of the preceding stage.
3. Zero output resistance R o so that the output can drive an infinite number of other devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to ∞ Hz can be amplified without
attenuation.
6. Infinite common-mode rejection ratio so that the output common-mode noise voltage is zero.
7. Infinite slew rate so that output voltage changes occur simultaneously with input voltage
changes.
Rf
Vi −
R1 Op-Amp Vo
+
Basic Op-Amp Connection
Rf
R1 Ro
V1 + Vo
Vi Ri ~ AV Vi
−
(a)
Rf
R1 Ro = 0
Vi Vo
Vi Ri = ∞ ~ −AV Vi
(b)

R1 Rf
Vi ~ Vi ~ −AV Vi = Vo
(c)
Operation of Op-Amp Constant-Gain Multiplier: (a) Op-Amp AC Equivalent Circuit; (b) Ideal Op-Amp
Equivalent Circuit; (c) Redrawn Equivalent Circuit
The basic circuit connection using an Op-Amp is shown in figure a. The circuit shown provides
operation as a constant – gain multiplier. An input signal, Vi, is applied through resistor R1 to the
minus input. The output is then connected back to the same minus input through resistor R f. The
plus input is connected to ground. Since the signal Vi is essentially applied to the minus input, the
resulting output is opposite in phase to the input signal. Fig (a) shows the Op-Amp replaced by its ac
equivalent circuit. If we use the ideal Op-Amp equivalent circuit is shown in fig (b). The circuit is
then redrawn as shown in Fig (c), from which circuit analysis is carried out.
Using superposition, we can solve for the voltage Vi in terms of the components due to each of the
sources. For source Vi only (−AV Vi set to zero),
Rf
Vi1 = V
R1 + R f i
For source −AV Vi only (Vi set to zero),
R1
Vi2 = (−AV Vi )
R1 + R f
The total voltage Vi is then
Rf R1
Vi = Vi1 + Vi2 = Vi + (−AV Vi )
R1 + R f R1 + R f
which can be solved for Vi as
Rf
Vi = V
R f + (1 + AV )R1 i
If AV >> 1 and AV R1 >> R f , as is usually true, then
Rf
Vi = V
AV R1 i
Solving for Vo /Vi , we get
Vo −AV Vi −AV R f V1 R f V1
= = =−
Vi Vi Vi AV R1 R1 Vi
So that
Vo Rf
=−
V1 R1
The result shows that the ratio of overall output to input voltage is dependent only on the values of
resistors R1 and R f − provided that Av is very large.

V0
Unity Gain: If R f = R1, then voltage gain, = −1, so that the circuit provides the unity voltage with
Vi
180° phase inversion.
Constant Magnitude Gain: If R f is some multiple of R1, the overall amplifier gain is a constant. If we
select, precise resistor values for R f and R1 , we can obtain a wide range of gains, the gain being as
accurate as the resistors used and is only slightly affected by temperature and other circuit factors.
Virtual Ground: The fact that Vi ≈ 0 V leads to the concept that at the amplifier input there exists a
virtual short circuit or virtual ground. The concept of a virtual short implies that although the
voltage is nearly 0V, there is no current through that amplifier input to ground. Current only goes
through resistors R1 and R f
Differential and Common Mode Operation: One of the important features of a differential circuit
connection, as provided in an op-amp, is the circuit’s ability to greatly amplify signals that are
opposite at the two points, while only slightly amplifying signals that are common to both inputs.
Differential Inputs: when separate inputs are applied to the op-amp, the resulting difference signal is
the difference between the two points.
Vd = Vi1 − Vi2
Common Inputs: When both input signals are the same, a common signal element due to the two
inputs can be defined as the average of the sum of the two signals,
1
Vc = (Vi1 + Vi2 )
2
Output Voltage: Since any signals applied to an Op-Amp in general have both in-phase and out of
phase components, the resulting output can be expressed as
Vo = Ad Vd + Ac Vc
Where
Vd = Differential voltage
Vc = Common voltage
Ad = Differential gain of the amplifier
Ac = Common-mode gain of the amplifier
Opposite Polarity Inputs: If opposite polarity inputs applied to an Op-Amp are ideally opposite
signals, Vi1 = −Vi2 = Vs, the resulting difference voltage is,
Vd = Vi1 − Vi2 = Vs − (−Vs ) = 2 Vs
while the resulting common voltage is,
1 1
Vc = (Vi1 + Vi2 ) = [Vs + (−Vs )] = 0
2 2
So, The resulting output voltage is,
Vo = Ad Vd + Ac Vc = Ad (2Vs ) + 0 = 2 Ad Vs
This shows that when the inputs are ideal opposite signals (no common element), the output is the
differential gain times twice the input signal applied to one of the inputs.

Same Polarity Inputs: If the same polarity inputs are applied to an Op-Amp, Vi1 = Vi2 = Vs
The resulting difference voltage is,
Vd = Vi1 − Vi2 = Vs − Vs = 0
The resulting common voltage is,
1 1
Vc = (Vi1 + Vi2 ) = V
2 2(Vs + Vs ) s
So, the resulting output voltage is,
Vo = Ad Vd + Ac Vc = Ad (0) + Ac Vs
This shows that when the inputs are ideal in phase signals (no difference signal), the output is the
common-mode gain times the input signal Vs , which shows that only common-mode operation
occurs.
Common-Mode Rejection Ratio:

Ad Ad
CMRR = , CMRR(log) = 20 log10
Ac Ac
It should be clear that the desired operation will have Ad very large while Ac very small. That is, the
signal components of opposite polarity will appear greatly amplified at the output, whereas the
signal components that are in phase will mostly cancel out so that the common mode gain,Ac is very
small. Ideally, the value of the CMRR is infinite. Practically, the larger the value of CMRR, the better
the circuit operation.
Ac Vc
Vo = Ad Vd + Ac Vc = Ad Vd [1 + ]
Ad Vd
1 Vc
= Ad Vd (1 + )
CMRR Vd
Op-Amp Specifications
Input Offset Voltage: Input offset voltage is the voltage that must be applied between the two input
terminals of an Op-Amp to null the output. We denote input offset voltage by Vio . This voltage Vio
could be positive or negative.
Input Offset Current: The algebric difference between the currents into the inverting and
noninverting terminals is referred to as input offset current, Iio . In the form of an equation,
Iio = |IB1 − IB2 |
Where, IB1 is the current into the noninverting input and IB2 is the current into the inverting input.
As the matching between two input terminals is improved, the difference between IB1 and IB2
becomes smaller; that is, the Iio value decreases further.
Input Bias Current: Input bias current IB , is the average of the currents that flow into the inverting
and noninverting input terminals of the op-amp. In equation form,
IB1 +IB2
IB = 2
The two input currents IB1 and IB2 are actually the base currents of the first differential amplifier
stage.

Output Offset Voltages: While the Op-Amp output should be 0V when the input is 0 V, in actual
operation there is some offset voltage at the output. The output offset voltage is affected by two
separate circuit conditions.
These are
1. An input offset voltage, Vio and
2. An offset current due to the difference in currents resulting at the plus (+) and minus (−)
inputs.
Output offset voltage due to input offset voltage is,
R1 +Rf
Vo(offset) = Vio R1
Output offset voltage due to input offset current is,
Vo(offset) = Iio R f
Rf
Vi +
R1 +
Vi Op-Amp Vo
− Rf
− [= (1 + ) Vio ]
+ R1
Vio
−
RC
Operation Showing Effect of Input Offset Voltage 𝐕𝐢𝐨
Gain Bandwidth: Because of the compensation circuits included in an Op-Amp, the voltage gain
drops off as frequency increases. A frequency of interest is where the gain drops by 3dB, this being
the cutoff frequency of the Op-Amp, fc . The unity gain frequency f1 and cutoff frequency are related
by,
f1 = AVD fc = Gain × B.W. where AVD is differential voltage gain
AV
AVD
0.707AVD
1
0 f1 Frequency (log scale)
fC
B1
Gain Versus Frequency Plot
Slew Rate is maximum rate at which amplifier output can change in volts per µs.
∆Vo V
SR =
∆t μs
Maximum Signal Frequency: The maximum frequency that an Op-Amp may operate depends on both
the bandwidth and slew rate of the Op- Amp. For a sinusoidal signal of general form,
Vo = K sin2π ft
The maximum voltage rate of change can be shown to be, signal maximum rate of change = 2πfK V/s
To prevent distortion at the output, the rate of change must also be less than the slew rate, i.e,
2π fK ≤ SR
SR
ω≤ rad/sec
K
Example: Calculate the single-ended output voltage V01 for the circuit of below Fig. Also calculate
the common-mode gain of the circuit.
+9 V
47 kΩ RC 47 kΩ ri1 = ri2 = 20 kΩ
Vo β1 = β2 = 75
Q1 Q2
~
Vi1 = 2 mV
43 kΩ
−9 V
Solution: The dc bias calculations provide
VEE − 0.7 V 9 V − 0.7 V
IE = = = 193 μA
RE 43 kΩ
The collector dc current is then
IE
IC = = 96.5 μA
2
So that VC = VCC − IC R C = 9 V − (96.5 μA)(47 kΩ) = 4.5 V
The value of R E is
26
Re = ≅ 269 Ω
0.0965
The ac voltage gain magnitude can be calculated as,
RC (47 kΩ)
AV = = = 87.4
2R E 2(269 Ω)
Providing an output ac voltage of magnitude of
Vo = AV Vi = (87.4)(2 mV) = 174.8 mV = 0.175 V
Common-mode gain,
Vo βR C 75 (47 kΩ)
Ac = = = = 0.31
Vi ri + 2(β + 1)R E 20 kΩ + 2(76)(73 kΩ)

Example: Calculate the total offset voltage for the circuit of Figure for an Op-Amp with specified
values of input offset voltage VIo = 4 mV and input offset current IIo = 150 nA.
500 kΩ
5 kΩ
Vi −
Vo
+
5 kΩ
Solution: The offset due to VIo is

R1 + R f 5 kΩ + 500 kΩ
Vo (offset due to VIo ) = VIo = (4 mV) ( )
R1 5 kΩ
= 404 mV
Vo (offset due to IIo ) = IIo R f = (150 nA)(500 kΩ) = 75 mV
resulting in a total offset
Vo (total offset) = Vo (offset due to VIo ) + Vo (offset due to IIo )
= 404 mV + 75 mV = 479 mV
Example: Determine the output voltage of an Op-Amp for input voltages of Vi1 = 150 μVand
Vi2 = 140 μV. The amplifier has a differential gain of Ad = 4000 and the value of CMRR is:
a. 100
b. 105
Solution: Vd = Vi1 − Vi2 = (150 − 140)μV = 10 μV
1 150 μV + 140μV
Vc = (Vi1 + Vi2 ) = = 145 μV
2 2
1 V
a. Vo = Ad Vd (1 + CMRR V c )
d
1 145 μV
= (4000)(10 μV) (1 + )
100 10 μV
= 40 mV (1.145) = 45.8 mV
1 145 μV
b. Vo = (4000)(10 μV) (1 + 105 10 μV
) = 40 mV (1.000145) = 40.006 mV
Practical Op-Amp Circuits

Inverting Amplifier (Voltage-Shunt Feedback Amplifier)
Figure shows the inverting amplifier using an op-amp. The input voltage source drives the inverting
terminal via a series resistor R1 and the non-inverting terminal is grounded. The inverted output
signal is also applied to the inverting input via feed feedback resistor R F . This arrangement forms a
negative feedback because any increase in the output signal results in a feedback signal into the
inverting input, causing a decrease in the output signal.

+VCC
IB1
V1
+ R1 V2 RF
R1 IB
− iin iF
R in ≅ 0 Ω V2
iin + IB
−VEE +VCC
iF Vo R L
+ +
Vin ~ RF − ≡ ~ Vin −
− −
V1
iF
+ +
Vo R L
I B1 −VEE −
Feedback
Circuit
Inverting Amplifier (Voltage-Shunt Feedback Amplifier)
Closed-Loop Voltage Gain

The closed-loop voltage gain AF of the voltage-shunt feedback amplifier can be obtained by writing
Kirchoff’s current equation at the input node V2 (see Figure) as follows
Iin = IF + IB ……………….(1)
Since R i is very large, the input bias current IB is negligibly small. Therefore,
Iin ≅ IF
That is,
Vin − V2 V2 − Vo
= … … … … … … . (2)
R1 RF
However, output voltage, Vo = AVid = A(V1 − V2 ) So,
Vo
V1 − V2 =
A
Since V1 = 0 V,
Vo
V2 = −
A
Substituting this value of V2 in Equation (2) and rearranging, we get
Vin + Vo /A −(Vo /A) − Vo
=
R1 RF
Vo AR F
So closed loop voltage gain, AF = =− (exact) … … … … … … . (3)
Vin R1 + R F + AR1
The negative sign in Equation (3) indicates that the input and output signals are out of phase by
180° (or of opposite polarities). Because of this phase inversion, the configuration in Figure is
commonly called an inverting amplifier.
Since the internal gain A of the Op-Amp is very large (ideally infinity), AR1 ≫ R1 + R F . This means
that Equation (3) can be rewritten as
Vo RF
AF = = − (ideal) … … … … … … . (4)
Vin R1
This equation shows that the gain of the inverting amplifier is set by selecting a ratio of feedback
resistance R F to the input resistance R1 . In fact, the ratio R F /R1 can be set to any value whatever,
even to less than 1

Non Inverting Amplifier (Voltage -Series Feedback Amplifier)

The schematic diagram of the Non-Inverting amplifier is shown in below figure. The input voltage
source drives the non-inverting terminal and the inverting terminal is grounded via resistor R1. The
non-inverted output signal is also applied to the inverting input via feedback resistor R f
+VCC
R in ≅ 0Ω +
Vid
+
−
+
−VEE
Vin ~ RL
− Rf Vo
+
Vf R1
− −
Feedback
Circuit
Non Inverting Amplifier with Feedback (Voltage-Series Feedback Amplifier)
Closed-Loop Voltage Gain

The closed-loop voltage gain is,
Vo
AF =
Vin
However,
Vo = A (V1 − V2 )
Referring to Figure, we see that
V1 = Vin
R1 Vo
V2 = Vf = since R i >> R1
R1 + R f
R1 Vo
∴ Vo = A (Vin − )
R1 + R f
Rearranging, we get
A(R1 + R f )Vin
Vo =
R1 + R f + AR1
Thus
Vo A (R1 + R f )
AF = = (exact) … … … … … … . (5)
Vin R1 + R f + AR1
Generally, A is very large (typically 105 ). Therefore, AR1 ≫ (R1 + R f ) and (R1 + R f + AR1 ) ≅ AR1
Thus,
Vo Rf
AF = =1+ (ideal) … … … … … … . (6)
Vin R1
Equation (6) shows that the gain of the non-inverting amplifier is determined by the ratio of two
resistors, R1 and R f

Summary of Different Parameters for Non-Inverting and Inverting Amplifiers

Parameter Non-Inverting Amplifier Inverting Amplifier
A(R1 + R f ) −AR f
AF = (exact) AF = (exact)
R1 + R f + AR1 R1 + R f + AR1
A −A Rf
1. Voltage gain = = whereK =
1 + AB 1 + AB R1 + R f
Rf R
= 1 + R (ideal) =−
f
(ideal)
1
R1
2. Gain of the feedback circuit R1 R1
B= B=
R1 + R f R1 + R f
3. Input resistance R if = R i (1 + AB) Rf
R if = R1 + ( ||R )
1+A i
4. Output resistance Ro Ro
R of = R of =
1 + AB 1 + AB
5. Bandwidth fF = fo (1 + AB) fF = fo (1 + AB)
UGB (UGB)(K)
fF = fF =
AF AF
6. Total output offset voltage ±Vsat ±Vsat
VooT = VooT =
1 + AB 1 + AB
Unity Follower: (Voltage Follower) (Voltage Buffer)

Vs +
+
Vd Vo
− −
Unity Follower
The unity-follower circuit, provide a gain of unity (1) with no polarity or phase reversal, Vo = Vs
The output is of the same polarity and magnitude as the input.
A voltage buffer circuit provides a means of isolating an input signal from a load by using a stage
having unity voltage gain, with no phase or polarity inversion and acting as an ideal circuit with very
high input impedance and low output impedance.
Summing Amplifier:
Rf
R1
Vs1
R2
Vs2
−
Vs3 R3
Op-Amp Vo
+
Summing Amplifier

The circuit show a three-input summing amplifier, which provide a means of algebraically summing
(adding) three voltages, each multiplied by a constant-gain factor.
Rf Rf Rf
Vo = − [ Vs1 + Vs2 + V ]
R1 R2 R 3 s3
In other words, each input adds a voltage to the output multiplied by its separate constant-gain
multiplier.
Voltage Subtraction
Rf Rf
R1
− R2
−
+ + V01
Rf Rf Rf
~ V1
R3 + Vo = − [ V − V]
− R 3 2 R 2 R1 1
+
~ V2
−
Circuit for Subtracting Two Signals
Current-to-Voltage Converter
The ideal voltage-gain of the inverting amplifier is given by,
V2 RF
iin iin
IB 2 ≅ 0
+VCC
iin
+
Vo = −iin R F
−
V1
−VEE RL
IB 1 ≅ 0
Current-to-Voltage Converter
Vo = −iin R f
This means that if we replace the Vin and R1 combination by a current source iin as shown in above
figure, the output voltage Vo becomes proportional to the input current iin . In other words, the
circuit of above figure converts the input current into a proportional output voltage.
One of the most common uses of the current-to-voltage converter is in sensing current from
photodetectors and in digital-to-analog converter applications.

Example: Find an expression for the output Vo of the amplifier circuit of below Fig. Assume an ideal
op amp. What mathematical operation does the circuit perform?
R
Vs1
V2 +
R
Vs2 Vo
−
R2
R1
Solution: The principle of superposition is applicable to this linear circuit. With Vs2 = 0 (shorted),
the voltage appearing at the no inverting terminal is found by voltage division to be,
R Vs
V2 = Vs1 = 1
R+R 2
Let V01 be the value of Vo with Vs2 = 0. It is non-inverting amplifier, so,
R2 R 2 Vs
V01 = (1 + ) V2 = (1 + ) 1
R1 R1 2
Similarly, with Vs1 = 0,
R 2 Vs
V02 = (1 + ) 2
R1 2
By superposition, the total output is then
1 R2
Vo = V01 + V02 = (1 + ) (Vs1 + Vs2 )
2 R1
The circuit is a noninverting adder
Example: For the circuit of below Fig., derive the expression for IL and hence Vo .
R1
V1
−
Vs R1 A
Vo
+
R2
B
R2 RL iL
Solution: KCL at node A,

VS − V1 V1 − Vo
= or VS = 2V1 − Vo … … … … … … . (1)
R1 R1
KCL at node B (due to virtual ground voltage at node B is V1)
V1 V1 − Vo V1
+ + = 0
RL R2 R2
V1 − Vo V1
or IL + + = 0
R2 R2

2V1 − Vo
or IL + = 0
R2
VS
From Equation (1), IL + = 0
R2
VS
or IL = −
R2
From Equation (1),
Vo = 2V1 − VS = 2(R L IL ) − VS
VS RL
Vo = −2R L − VS = −VS [1 + 2 ]
R2 R2
Integrator
C if
is
R
−
Vs
Vo
+
Integrator
If the feedback component used is a capacitor, the resulting connection is called an integrator. The
capacitive impedance can be expressed as
1 1
Xc = =
jωC SC
Vo XC 1
= − =−
Vs R SCR
By taking inverse Laplace transform,
1
Vo (t) = − ∫ Vs (t)dt
RC
More than one input may be applied to an integrator with the resulting operation given by
1 1 1
Vo (t) = − [ ∫ V1 (t)dt + ∫ V2 (t)dt + ∫ V3 (t)dt]
R1 C R2C R3C
Differentiator
The circuit performs the mathematical operation of differentiation; that is, the output waveform is
the derivate of the input waveform.
dVs (t)
Vo (t) = −RC
dt

R
if
is C
−
Vs
Vo (t)
+
Differentiation Circuit
Active Filters
A filter circuit can be constructed using passive components: Resistors and capacitors. An active
filter additionally uses an amplifier to provide voltage amplification and signal isolation or buffering.
A filter that provides a constant output from dc upto a cutoff frequency fOH and then passes no
signal above that frequency is called an ideal “Low-Pass Filter”
A filter that provide or passes signals above a cut off frequency fOL is a “high pass filter”.
When the filter circuit passes signals that are above one ideal cut off frequency and below a second
cut off frequency, it is called a “Band Pass Filter”
Vo /Vi Vo /Vi
Low – Pass High – Pass

Filter Filter
f f
fOH fOL
(a) (b)
Vo /Vi
Band Pass
filter
f
fOL fOH
(c)
Ideal Filter Response: (a) Low – Pass (b) High – Pass, (c) Band Pass
Low – Pass Filter

A first – order, low – pass filter using a single resistor and capacitor as in below figure (a) has a
practical slope of – 20 dB per decade, as shown in below figure (b).The voltage gain below the cutoff
frequency is constant at
RF
AV = 1 +
RG
1
At the cutoff frequency of fOH =
2πR1 C1

RG V2 RF
V+
+
R1
− Output (Vo )
~ V1 C1 V−
(a)
Vo /V1
AV
0.707AV
f
fOH
(b)
First Order Low – Pass Active Filter
Connecting two sections of filter as in below figure results in a second – order low – pass filter
with cutoff at – 40 dB per decade. The circuit voltage gain and the cutoff frequency are the same
for the second – order circuit as for the first – order filter circuit, except that the filter response
drops at a faster rate for a second – order filter circuit.
RG RF
−
R1 R2 Op-Amp
Vi + Output (Vo )
C1 C2
(a)

Vo
Vi −40 dB⁄dec
AF
0.707AF
f
1 fH
fOH =
2п√R1 R 2 C1 C2
(b)
Second Order Low – Pass Active filter
High – Pass Active Filter

First and second order high – pass active filter can be built as shown in figure. The amplifier cutoff
frequency is
1
fOL =
2πR1 C1
with a second – order filter R1 = R 2 and C1 = C2 results in the same cutoff frequency as in below
Eq.1
1
fOL = … … … . . (1)
2π√R 2 R1 C1 C2
RG RF
− Vo
C1 Op-Amp
Vi
+
R1
(a)
RG RF
−
C1 C2 Op-Amp (Vo )
Vi +
R1 R2
(b)

RF
AV = 1 +
RG
Vo /Vi
AV
0.707 AV
−20 dB/decade
−40 dB/decade (Second Order)
f
fOL
High-Pass Filter: (a) First Order (b) Second Order (c) Response Plot
Band-Pass Filter
A band-pass filter can be formed by simply cascading high-pass and low-pass sections.
Below figure shows the ± 20dB/decade band-pass filter, which is composed of first-order high-pass
and first-order low-pass filters. To realize a band-pass response, however, fH must be larger than fL
First-Order First-Order
High-Pass low-Pass
Section R′1 Section R′
F
R1 RF
+VCC
+VCC
−
+ R ′ A2 Vo
C A1 +
− RL
+ ′ −VEE
C
~ Vin R −VEE
−
(a)
Vo
Gain, | |
Vin +20 dB/decade −20 dB/decade
AFT
0.707 AFT
Stop Stop
Pass Band
Band Band
fL fH Frequency
(b)
(a) ± 20 dB/Decade Band Bass Filter (b) Its Frequency Response
All-Pass Filter
An all-pass filter passes all frequency components of the input signal without attenuation, while
providing predictable phase shifts for different frequencies of the input signal. The all-pass filters
are also called delay equalizers or phase correctors.
Figure shows an all-pass filter where in R F = R1
The output voltage Vo of the filter can be obtained by using the superposition theorem:
−jXC
Vo = −Vin + V (2)
R − jX C in
But – j = 1/j and X C = 1/2πfC . Therefore, substituting for X C and simplifying, we get
2
Vo = Vin (−1 + )
j2πfRC + 1
R1 R F = R1
+VCC
−
R 1 − j2πfRC
+ + Vo = V
1 + j2πfRC in
~ Vin −VEE
− C RL
(a)
Voltage
Vin Vo
Vp
90° 180° 250° 360° 450° 540° Phase Angle (deg )

−Vp
ϕ = 90°
(b)
All-Pass Filter. (a) Circuit (b) Phase Shift Between Input and Output Voltages
Vo 1 − j2πfRC
or, = … … … … … . (7)
Vin 1 + j2πfRC
where f is the frequency of the input signal in Hertz.
Equation (7) indicates that the amplitude of Vo /Vin is unity; that is, |Vo | = |Vin | throughout the
useful frequency range and the phase shift between Vo and Vin is a function of input frequency f. The
phase angle ϕ is given by,
2πfRC
ϕ = −2tan−1 ( ) … … … … … … . (8)
1
Where ϕ is in degrees, f in Hertz, R in Ohms and C in Farads. Figure (b) shows a phase shift of 90°
between the input Vin and Output Vo . That is, Vo lags Vin by 90°. For fixed values of R and C, the
phase angle ∅ changes from 0 to -180° as the frequency f is varied from 0 to ∞
In figure (a), if the positions of R and C are interchanged, the phase shift between input and output
becomes positive. That is, output Vo leads Input Vin
Example: Find the relationship between Vo and Vin in the circuit of below Fig.
I2 C/2
R/2
Ii I1 I3
R R
−
+ C1 Op-Amp
+ +
Vi C
Vo
− −
(a)
Solution: Since the inverting terminal is a virtual ground, the Laplace-domain input current is given
by
Vi Vi (sRC + 1)
Ii = =
R + (R||1/sC) sR2 C + 2R
With zero current flowing into the op amp inverting terminal, current division yields
1/sC
I2 = I1 = I
R + 1/sC i
1 Vi (sRC + 1) Vi
= =
sRC + 1 R(sRC + 2) R(sRC + 2)
Again, because the inverting terminal is a virtual ground,
Vo sC(sRC + 4)
I3 = = V
1⁄ 1 R⁄ 4(sRC + 2) o
SC/2 + ( ⁄SC/2 ‖ 2)
and, by current division,
−R/2 −sRC sC(sRC + 4)
I2 = I3 = × V
2/sC + R/2 (sRC + 4 4 × (sRC + 2) o
−s 2 RC 2 Vo
=
4(sRC + 2)
Equating the two expressions for I2 yields a Laplace-domain expression relating Vo and Vi ;
4
Vo = − 2 2 2 Vi
s R C
Or, after inverse transformation,
4
Vo = − ∫ (∫ Vi dt) dt
(RC)2

Different Types of Operational Amplifiers and Converters

Circuit Gain or Input Resistance
Type of
Schematic Variable of or Input Current
Circuit
Interest or Voltage
R2
R1
Non Inverting Vo R2
− =1+ R in = ∞(idealy)
Amplifier ∞ + Vi R1
+ Vo
−+ −
Vi
− Vo
Buffer ∞ + =1 R in = ∞(idealy)
+ Vo Vi
−+ −
Vi
R2
Rb
(V1 − V2 )
Ra +Rb
i1 =
R1 R1
Difference −+ − R2 V2
V1 ∞ Vo = (V2 − V1 ) i2 = R a + R b
Amplifier + R1
+ Vo R1 R a
i2 𝐍𝐨𝐭𝐞: =
− R2 Rb
−+
Ra Rb (Requirements)
V2
Rf
R1 i1
V1
V1 i1 =
i2 Vo = R1
R2
V2 − V1 R f V2 R f V2
Adder Rn −[ + i2 =
∞ + R1 R2 R2
V3 + Vo Vn R f Vn
in
− + ⋯+ ] in =
Rn Rn
i R/K R
R/(K − 1) Vi KVi (1 − x)
Vo i= +
Variable Gain − = (2Kx − K) R3 R
Vi ∞ Vi Note: Potentiometer
Circuit ∓ +
+
Vo 0 ≤ x ≤ 1, K > 1 R 3 adjust
−
xR 3

R
i
Voltage to Vi Note : The current
− Vi
Current i= throughR L is
R1 ∞ + Ri
Convertor + independent of R L
Vo
−
R Vi RL
is = (1 − )
R R
Voltage to Note:
i
Current 2RL
− Vo = Vi ( ) The
Convertor RL R
Vi R
is ∞ + i= current ‘i’ is
with + Vo R
independent of R L
Grainded Vi ± −
R1 circuit has wide
Load R1 band-width for
RL ≪ R
R
ii
V = 0, Note: The
Current to −
+ voltage Vo is
Voltage Ri ∞ + Vo = −R i
ii V + Vo independent
Convertor − RL
Vi ± − of R L &R i
R2
R4
− R3
Current to ∞ −
+ R4
Voltage ∞ + Vo = −2iR1 V=0
R2 + Vo R3
Convertor −
+
i V
R1 R1 − R3 R4
−
+

R2
− + R1 +15 V
−
Inverting ∞
10 μF +15 V +
Amplifier Vi + Vo R2 Note : Requirement
− Vo = 7.5 − Vi
with Single R R1 R = 3.9 kΩ
Supply
0.1μF
R
R2
− + R1 +15
−
Non Inverting 10 μF ∞ +
Vi 10 μF + Vo Vo = 7.5
Amplifier − Note : Requirement
R2
with Single +Vi (1 + ) R = 3.9 kΩ
+15 V R1
Supply 100kΩ
R
Vi ±
1μF R
i RC Vi
R i=
Vo = −V(0) R
C t Note : Negative
± Vi
+ − 1 feedback is
V(o) − ∫ Vi (t)dt
RC required at DC.A
− + 0
Integrator ∞ large value of R c
Vo − Vo is the initial can be used or a
+
voltage across the feedback path can
capacitor R c is be established
very large through an
external circuit
R
V(o) Vi Vo
− i= −
R1
∞
Vo = 2 Vo R 2R
De Boo i + t Note :One end of
+ Vo
2
integrator R − + ∫ Vi (t)dt capacitor is
RC physically
± Vi 0
+ grounded
R
C V(o)
−
10 μF

R dVi
i=C
dt
i Note :
Differentiator are
− dVi
Differentiator ∞ Vo = −RC usually avoided in
C + dt
+ Vo the design of
Vi
− circuit the
accentuate noise
∞
+ −
Generalized
Impedance Z1 Z2 Z3 Z4 Z1 Z3 Z5
Zin =
Convertor Zin Z2 Z4
(GIC)
− +
∞ Z5
Astable Multivibrator (Square Wave Generator)

Square wave outputs are generated when the Op-Amp is forced to operate in the saturated region.
One such circuit is shown in below figure (a). This square wave generator is also called a free-
running or astable multivibrator. The output of the Op-Amp in this circuit will be in positive or
negative saturation, depending on whether the differential voltage Vid is negative or positive,
respectively.
Assume that the voltage across capacitor C is zero volts at the instant the dc supply voltages +VCC
and −VEE are applied. This means that the voltage at the inverting terminal is zero initially. At the
same instant, however, the voltage V1 at the noninverting terminal is a very small finite value that is
a function of the output offset voltage VoT and the values of resistors R1 and R 2 . Thus the differential
input voltage Vid is equal to the voltage V1 at the noninverting terminal. Although very small, voltage
V1 will start to drive the Op-Amp into saturation. For example, suppose that the output offset voltage
VooT is positive and that, therefore, voltage V1 is also positive. Since initially the capacitor C acts as a
short circuit, the gain of the Op-Amp is very large (A); hence V1 drives the output of the Op-Amp to
its positive saturation +Vsat . With the output voltage of the Op-Amp at +Vsat , the capacitor C starts
charging toward +Vsat through resistor R.

C Output Voltage
V2 RF
Vo V2
+Vsat ≈ VCC
+VCC
Vid V1
− Vo
R1 V1
+
0 t
−VEE
−V1
R2
−Vsat ≈ VEE
(a)
T
R1
|V1 | = |V |
R1 + R 2 sat
1 1
fo = = i If R 2 = 1.16 R1
T 2RC
(a) Square Wave Generator (b) Waveforms of Output Voltage 𝐕𝐨 and Capacitor Voltage 𝐕𝟐 of the
Square-Wave Generator
However, as soon as the voltage V2 across capacitor C is slightly more positive than V1 , the output of
the Op-Amp is forced to switch to a negative saturation, −Vsat . With the op-amp’s output voltage at
negative saturation, −Vsat , the voltage V1 across R1 is also negative, since
R1
V1 = (−Vsat )
R1 + R 2
Thus the net differential voltage Vid = V1 − V2 is negative, which holds the output of the Op-Amp in
negative saturation. The output remains in negative saturation until the capacitor C discharges and
then recharges to a negative voltage slightly higher than −V1. [See Figure (b)] Now, as soon as the
capacitor’s voltage V2 becomes more negative than −V1, the net differential voltage Vid becomes
positive and hence drives the output of the Op-Amp back to its positive saturation +Vsat . This
completes one cycle. With output at +Vsat , voltage V1 at the noninverting input is
R1
V1 = (+Vsat )
R1 + R 2
The time period T if the output waveform is given by
2R1 + R 2
T = 2RC ln ( )
R2
or
1
fo = 2R +R
… … … … … … . (9)
2RC ln ( R1 2 )
2
Equation (9) indicates that the frequency of the output fo is not only a function of the RC time
constant but also of the relationship between R1 and R 2
1
It R 2 = 1.16R1 , fo =
2пRC

Pulse Generator (Monostable Multivibrator)

A monostable multivibrator has one stable state and one quasistable state. The circuit remains in its
stable state until a triggering signal causes a transition to the quasistable state. Then, after a time T,
the circuit returns to its stable state. Hence a single pulse has been generated and the circuit is
referred to as a one-shot.
To see how the circuit operates, assume that it is in its stable state with the output at Vo = +Vz and
the capacitor clamped at
Vc = V1 ≈ 0.7 V
(The ON voltage of D1 with βVz > V1). If the trigger amplitude is greater than βVz − V1, then it will
cause the comparator to switch to an output Vo = −Vz. The capacitor will now charge through R′
toward −Vz because D1 becomes reverse biased. When Vc becomes more negative than −βVz, the
comparator output swings back to +Vz. The capacitor now starts charging toward +Vz through R′
until Vc reaches V1 and C becomes clamped again at Vc = V1. The pulse width T is given by,
1 + (V1 /Vz ) R3
T = R′ C ln [ ],β =
1−β R2 + R3
1
If Vz >> V1 and R 2 = R 3 , so that β = , then T = 0.69 R′ C
2
VC R′
Output Voltage
D1 C VC +Vz Vo
− R1 Vo
V1
+ 0 t
R2
D2 VZ VC
Trigger
−βVz
+
βVo R3 VZ
−Vz
− T
t p << T
(a) (b)
(a) Monostable Multivibrator (b) Output and Capacitor Voltage Waveforms
Comparator
Figure (a) shows an inverting comparator in which the reference voltage Vref is applied to the
(+) input and Vin is applied to the (−) input. In this circuit, Vref is obtained by using a 10kΩ
potentiometer that forms a voltage divider with the dc supply voltages + VCC and −VEE and the
wiper connected to the (+) input. As the wiper is moved toward −VEE, Vref becomes more negative,
while if it is moved toward +VCC , Vref becomes more positive. Thus a Vref of a desired amplitude
and polarity can be obtained by simply adjusting the 10kΩ potentiometer. With the sinusoidal input
waveform, the output Vo has the waveform shown in Figure (b) or (c), depending on whether Vref is
positive or negative, respectively.

+VCC
Protective
Diodes
+
RP D1 D2
Vref Vo
10 kΩ −
R
−VEE
R
+
~ Vin
−
(a)
Vin Vin
Vp
Vp
+Vref
0V t 0V t
−Vref
−Vp
−Vp
Vo Vin < Vref
+Vsat +Vsat
0V t 0V t
−Vsat −Vsat
Vin < Vref
Vin > −Vref
(b) (c)
(a) Inverting Comparator with Input and Output Waveforms (b) If 𝐕𝐫𝐞𝐟 is Positive
(c) If 𝐕𝐫𝐞𝐟 is Negative
Zero – Crossing Detector

An immediate application of the comparator is the zero – crossing detector or sine wave to square
wave converter. The basic comparator of Figure (a) can be used as the zero – crossing detector
provided that Vref is set to zero (Vref = 0 V). Figure (a) shows the inverting comparator used as a
zero – crossing detector. The output voltage Vo waveform in Figure (b) shows when and in what
direction an input signal Vin crosses zero volts. That is, the output Vo is driven into negative
saturation when the input signal Vin passes through zero in the positive direction. Conversely, when
Vin passes through zero in the negative direction, the output Vo switches and saturates positively.

Clamp
R Diodes +VCC
+
D1 D2
Vo
+ −
~ Vin −VEE RL
− R Vref = 0V
(a)
Vin
Vp
0V t
−Vp T
Vo
+Vsat
0V t
−Vsat
(b)
(a) Zero-Crossing Detector (b) Its Typical Input and Output Waveforms
Schmitt Trigger
Figure (a) shows an inverting comparator with positive feedback. This circuit converts an irregular-
shaped waveform to a square wave or pulse. The circuit is known as the Schmitt Trigger or squaring
circuit.
The input voltage Vin triggers (changes the state of ) the output Vo every time it exceeds certain
voltage levels called the upper threshold voltage Vut and lower threshold voltage Vlt , as shown in
figure (b)
In figure (a), these threshold voltages are obtained by using the voltage divider R1 − R 2 , where the
voltage across R1 is fed back to the (+) input. The voltage across R1 is a variable reference threshold
voltage that depends on the value of polarity of the output voltage Vo . When Vo = + Vsat , the voltage
across R1 is called the upper threshold voltage, Vut . The input voltage Vin must be slightly more
positive than Vut in order to cause the output Vo to switch from +Vsat to −Vsat . As long as Vin < Vut ,
Vo is at +Vsat . Using the voltage-divider rule
R1
Vut = (+Vsat )
R1 + R 2

+VCC
R OM ≈ R1 ||R 2 +15 V
−
+
Vin V~ + Vo
in
− −15 V RL
−VEE
R2
Vit R1
(a)
Vin
VP
Vut
0 t
Vit Vo
+Vsat
−VP
T
Vlt Vut
Hysteresis Vin
Vo
Voltage
(Vut − Vit )
+Vsat −Vsat
0 t
−Vsat
(b) (c)
(a) Inverting Comparator as Schmitt Trigger (b) Input and Output Waveforms of Schmitt Trigger
(c) 𝐕𝐨 Versus 𝐕𝐢𝐧 Plot of the Hysteresis Voltage
On the other hand, when Vo = −Vsat , the voltage across R1 is referred to as the lower threshold
voltage, Vit . Vin must be slightly more negative than Vit in order to cause Vo to switch from −Vsat to
+Vsat . In other words, for Vin values greater than Vit , Vo is at −Vsat
Vit is given by the following equation
R1
Vit = (−Vsat )
R1 + R 2
Thus, if the threshold voltages Vut and Vit are made larger than the input noise voltages, the positive
feedback will eliminate the false output transitions. Also, the positive feedback, because of its
regenerative action, will make Vo switch faster between +Vsat and−Vsat . In figure (a), resistance
R OM ≅ R1 ||R 2 is used to minimize the offset problems.
Figure (b) shows that the output of the Schmitt trigger is a square wave when the input is a sine
wave.

The comparator with positive feedback is said to exhibit hysteresis, a dead-band condition. That is,
when the input of the comparator exceeds Vut , its output switches from +Vsat to −Vsat and reverts
back to its original state, +Vsat , when the input goes below Vit [see figure (c)]. The hysteresis
voltage is, of course, equal to the difference between Vut and Vit . Therefore,
R1
Vhy = Vut − Vit = [+Vsat − (−Vsat )]
R1 + R 2
Voltage Limiters
In the circuit of figure (a), the Zener diodes D1 and D2 are connected in the feedback path; this
arrangement limits the positive and negative values of the output voltage Vo . When the input voltage
Vin crosses 0 V and increases in the positive direction, the output voltage Vo increases in the
negative direction until diode D1 is forward biased and D2 goes into avalanche conduction.
Therefore, the maximum negative value of Vo is equal to (VZ + VD1 ), where VZ is the zener voltage
and VD1 is the voltage drop across the forward-biased zener D1 (= 0.7 V typically). On the other
hand, when Vin crosses 0 V and starts increasing in the negative direction, Vo starts increasing
positively until diode D2 is forward biased and D1 goes into avalanche conduction. Thus the
maximum positive Vo is equal to (VZ + VD2 ), where VZ is the zener voltage and VD2 is the voltage
drop across the forward-biased zenerD2 (= 0.7 V typically). Thus the output voltage swing is limited
to +(VZ + 0.7) and – (VZ + 0.7) [see Figure (b)]
+ − + −
D1 D2
R +VCC
− Vo
V2
+ V1 + −
~ Vin
RL
− −VEE
R OM=R
+
(a)
Vin
Vp
0V t
−Vp
Vo
(VZ + VD2 )
0V t
−(VZ + VD1 )
(b)
(a) Basic Op-Amp Comparator with Positive and Negative Output Voltage Limiting
(b) Its Input and Output Waveforms

If there is a need to limit the swing of the output voltage Vo to a positive direction only, a
combination of zener and rectifier diodes is used as shown in the circuit of Figure (a). When the
input voltage Vin crosses 0 V and increases in the positive direction, the output voltage Vo is at −Vsat .
This happens because diode D2 is reverse biased, causing the Op-Amp to operate in the open-loop
configuration. However, when Vin crosses 0 V and starts increasing in the negative direction, Vo
starts increasing positively until D2 is forward biased and D1 goes into avalanche conduction.
Therefore, the maximum positive Vo = VZ + VD2 [see Figure (b)]
In the circuit of figure (a), if the position of D1 and D2 diodes in interchanged, the output voltage vo
will then be limited in a negative direction to −(VZ + VD2 ). However, the maximum positive
Vo = +Vsat
+ − + −
D1 D2
+VCC
R
− Vo
V2
+ V1 + −
~ Vin
RL
− −VEE (b)
R OM=R
+
(a)
Vin
Vp
0V t
−Vp
Vo
VZ + VD2
0V t
−Vsat
(b)
(a) Basic Op-Amp Comparator with Positive Output Voltage Limiting
(b) Its Input and Output waveforms
If only a single zener is used in the feedback path of an Op-Amp as shown in Figure (a), the output
voltage Vo is limited to +VZ and −VD, [see Figure (b)]. The exact opposite result can be obtained by
reversing the direction of the zener diode. That is, Vo will be limited to −VZ and +VD
R
+ −
D
+
~ Vin +VCC
− − Vo
+ −
−VEE RL
R OM=R (b)
+
(a)
Vin
Vp
Vo t
−Vp
Vo
VZ
t
−VD
(b)
(a) Basic Op-Amp Comparator with Positive and Negative Output Voltage Limiting (b) Its Input and
Output Waveforms
Example: Assuming ideal Zener diodes and op amp, find the relationship between Vo and VS for the
circuit given below. Sketch the results on a transfer characteristic.
Vz2 Vz1
− + + −
Z2 Z1
R2
R1
− Vo
Vs
+
Solution: Since the op amp is ideal, the inverting terminal is a virtual ground and Vo appears across
the parallel-connected feedback paths. There are two distinct possibilities:

Case I: If VS > 0, then Vo < 0, Z2 if forward-biased and Z1 reverse-biased. The Zener

feedback path is an open circuit until V0 at −VZ1 ; then Z1 will limit Vo at −VZ1 so that no
further negative excursion is possible.
Case II: If VS < 0, then Vo > 0, Z1 is forward-biased and Z2 reverse-biased. The Zener
feedback path acts as an open circuit until Vo reaches VZ2 , at which point Z2 limits Vo to
that value. In summary, for both cases
R1
VZ2 for VS < − VZ2
R2
R1 R1 R1
Vo = − VS for − VZ2 ≤ VS ≤ V
R2 R2 R 2 Z1
R1
−VZ1 for VS > V
{ R 2 Z1
The transfer characteristic is shown below:
Vo
Vz2
R1
V
R 2 Z1
VS
R1
− VZ2
R2
−VZ1
Positive and Negative Clippers

A positive clipper, a circuit that removes positive parts of the input signal, can be formed by using an
Op-Amp with a rectifier diode as shown in figure (a). In this circuit the Op-Amp is basically used as a
voltage follower with a diode in the feedback path. The clipping level is determined by the reference
voltage Vref , which should be less than the input voltage range of the op-amp. Additionally, Vref is
derived from the positive supply voltage (+VCC). As shown in Figure (b), the output voltage has
portions of the positive half-cycle above Vref clipped off.
The circuit works as follows: During the positive half-cycle of the input, the diode D1 conducts only
until Vin = Vref. This happens because, when Vin < Vref, the voltage (Vref ) at the (−) input is higher
than that at the (+) input; hence, the output voltage Vo′ of the Op-Amp becomes sufficiently negative
to drive D1 into conduction. When D1 conducts, it closes the feedback loop and the Op-Amp operates
as a voltage follower; that is, output Vo follows input Vin until Vin = Vref. However, when Vin is
slightly higher than Vref, the output Vo′ of the Op-Amp becomes sufficiently positive to drive D1 into
cutoff. This opens the feedback loop and the Op-Amp operates open-loop; therefore, it further drives
its output Vo′ toward positive saturation (≅ +VCC ). With D1 reverse biased, the output voltage
Vo = Vref. Thus, when Vin > Vref, Vo′ ≅ +VCC and Vo = Vref [see Figure (b)]
When Vin drops below Vref, the output of the Op-Amp Vo′ again becomes sufficiently negative to drive
D1 into conduction. This closes the feedback loop; hence the output follows the input. Thus diode D1
is on for Vin < Vref and off for Vin > Vref . The output follows the input only when the diode is on. The
Op-Amp alternates between open-loop and closed-loop operations as the diode D1 is turned off and
on, respectively.
−VEE
−15 V
− Vo′ D1 Vo
Vid
+
+ R = 10 kΩ
Vin ~ Rp
+15 V
−
+VCC 10 kΩ
Vref = 1 V
(a)
Vin Vin
+2V +2V
Vref = +1V Vref = +1V
0 t 0 t
−1V Vref = −1V
−2V −2V
Vo Vo
D1 off
2V 2V
Vref = +1V 1V
0 t t
−1V −Vref = −1V
−2V D1 on −2V
D1 off D1 on
(b) (c)
(a) Positive Clipper Circuit (b) Input and Output Waveforms with +𝐕𝐫𝐞𝐟 = 𝟏 𝐕 (c) Input and Output
Waveforms with −𝐕𝐫𝐞𝐟 = −𝟏 𝐕
In figure (a) If pot R p is connected to the negative supply −VEE instead of +VCC, the reference
voltage Vref will be negative. This will cause the entire output waveform above −Vref to be clipped
off, as shown in figure (c) The output follows the input only when Vin < −Vref
+VCC
+15 V
− D1
Vo′ Vo
Vid
+
+ R = 10 kΩ
Vin ~ Rp
−15V
−
−VEE 10 kΩ
Vref = 1V
(a)
Vin Vin
+2V +2V
+Vref = +1V
0 t 0 t
−Vref = −1V −2V
−2V
Vo D1 on Vo
+2V
+2V
+Vref = +1V
0 t 0 t
−Vref = −1V
D1 off
(b) (c)
(a) Negative Clipper Circuit (b) Input and Output Waveforms with −𝐕𝐫𝐞𝐟 = −𝟏 𝐕 (c) Input and Output
Waveforms with +𝐕𝐫𝐞𝐟 = +𝟏 𝐕
The positive clipper of figure (a) is converted into a negative clipper by simply reversing diode D1
and changing the polarity of reference voltage Vref. The resultant circuit is shown in figure (a). The
negative clipper clips off the negative parts of the input signal below the reference voltage [see
figure (b)]. Diode D1 conducts whenVin > −Vref and therefore during this period output Vo follows
the input Vin . However, the negative portion of the output voltage below −Vref is clipped off because
D1 if off for Vin < −Vref. In the circuit of figure (a), if −Vref is changed to +Vref by connecting the
potentiometer R p to the +VCC, the output voltage below +Vref will be clipped off, as shown in
figure (c). The diode D1 must be on for Vin > Vref and off for Vin < +Vref
Small-Signal Half-Wave Rectifiers

The circuit of figure (a) can be used as a positive small-signal half-wave rectifier provided that
−Vref = 0 V. Shown in figure (a), the resultant circuit can rectify signals with peak values down to a
few millivolts, unlike conventional diodes. This is possible because the high open-loop gain of the
Op-Amp automatically adjusts the voltage drive to the diode D1 so that the rectified output peak is
the same as the input [see figure (b)]. In fact, the diode acts as an ideal diode (switch), since the
voltage drop across the on diode is divided by the open-loop gain of the op-amp. As Vin starts
increasing in the positive direction, the Vo′ also starts increasing positively until diode D1 is forward
biased. When D1 is forward biased, it closes a feedback loop and the Op-Amp works as a voltage
follower. Therefore, the output voltage Vo follows the input voltage Vin during the positive half-cycle,
as shown in figure (b). However, when Vin starts increasing in the negative direction, Vo′ also
increases negatively until it is equal to the negative saturation voltage (≅ −VEE ). This reverse biases
diode D1 and opens the feedback loop. Therefore, during the negative half-cycle of the input signal,
Vo is 0 V

Vin
+100 mV
+VCC 0V t
+15V
−100 mV
− Vo′ D1 Vo
+ Vo
D1 on
+ −15V RL
+100 mV D1 off
~ Vin −VEE
−
0V t
(a) (b)
(a) Positive Small-Signal Half-Wave Rectifier Circuit (b) Its Input and Output Waveforms
Figure (a) shows a negative small-signal half-wave rectifier. This circuit, in fact, can be obtained
from the circuit of figure (a) by setting Vref = 0 V. During the positive alternation of Vin , D1 is reverse
biased; therefore, Vo = 0 V. On the other hand, during the negative alternation, D1 is forward biased;
hence Vo follows Vin .
Vin
+100 mV
+VCC 0V t
+15 V
−100 mV
− Vo′ D1 Vo
+ Vo
+ −15 V RL
D1 off
~ Vin −VEE D1 on
−
0V t
−100 mV
(a) (b)
(a) Negative Small-Signal Half-Wave Rectifier Circuit (b) Its Input and Output Waveforms
Yet another negative half-wave rectifier is shown in figure (a). In this circuit two diodes are used so
that the output Vo′ of the Op-Amp does not saturate. This minimizes the response time and increases
the operating frequency range of the op-amp. The output resistance is non-uniform since it depends
on the state of diode D1 . In other words, the output impedance is low when D1 is on and high (≅ R F)
when D1 is off. This problem, however, can be cured by connecting a voltage follower stage at the
output. During the positive half-cycle of Vin , output Vo′ is negative, which forward biases diode D1
and closes the feedback loop through R F . Since R1 = R F , Vo = Vin . However, on the negative
alternation of Vin , output Vo′ is positive; hence diode D2 is forward biased. In fact, it is this diode that

prevents the Op-Amp from going into positive saturation. Since diode D1 is off, output Vo = 0 V. To
obtain positive half-wave rectified outputs, diodes D1 and D2 must be reversed.
Vin
R1 R F = R1 Vo
Vp
_1
+ +VCC + 0 t
~ Vin
+15 V
D1
− − −Vp
−
+ Vo
−15 V +
R1
2
D2
R OM =
+VEE −
D1 on D2 on
0 t
−Vp
(a) (b)
(a) Negative Half-Wave Rectifier (b) Its Input and Output Waveforms
The 555 Timer

One of the most versatile linear integrated circuits is the 555 timer. A sample of its applications
includes monostable and astable multivibrators, DC-DC converters, digital logic probes, waveform
generators, analog frequency meters and tachometers, temperature measurement and control
devices, infrared transmitters, burglar and toxic gas alarms, voltage regulators, electric eyes and
many others. The 555 is a monolithic timing circuit that can produce accurate and highly stable time
delays or oscillation. The timer basically operates in one of two modes: either as a monostable (one
–shot) multivibrator or as an astable (free-running) multivibrator. The device is available as an
8-pin metal can, an 8-pin mini DIP or 14-pin DIP. Figure shows the connection diagram and the
block diagram of the SE/NE 555 timer. The SE5555 is designed for the operating temperature range
from –55° to + 125°C, while the NE555 operates over a temperature range of 0° to + 70°C. The
important features of the 555 timer are these: it operates on +5 to +18V supply voltage in both
free-running (astable) and one shot (monostable) modes; it has an adjustable duty cycle; timing is
from microseconds through hours; it has a high current output; it can source or sink 200 mA; the
output can drive TTL.
The Pin Description is Following

Pin 1 Ground: All voltages are measured with respect to this terminal.
Pin 2 Trigger: The output of the timer depends on the amplitude of the external trigger pulse applied
to this pin. The output is low if the voltage at this pin is greater than 2/3 VCC . However, when a
negative-going pulse of amplitude larger than 1/3 VCC is applied to this pin, the comparator 2 output
goes low, which in turn switches the output of the timer high [see figure (b)]. The output remains
high as long as the trigger terminal is held at a low voltage.

Pin 3 Output: There are two ways a load can be connected to the output terminal: either between pin
3 and ground (pin 1) or between pin 3 and supply voltage +VCC (pin 8) [see Figure (b)]. When the
output is low, the load current flows through the load connected between pin 3 and +VCC into the
output terminal and is called the sink current. However, the current through the grounded load is
zero when the output is low. For this reason, the load connected between pin 3 and +VCC is called
the normally on load’ and that connected between pin 3 and ground is called the normally off load.
On the other hand, when the output is high, the current through the load connected between pin 3
and +VCC (normally on load) is zero. However, the output terminal supplies current to the normally
off load. This current is called the source current.
Pin 4 Reset: The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When the
reset function is not in use, the reset terminal should be connected to +VCC to avoid any possibility
of false triggering.
Pin 5 Control Voltage: An external voltage applied to this terminal changes the threshold as well as
the trigger voltage. In other words, by imposing a voltage on this pin or by connecting a pot between
this pin and ground, the pulse width of the output waveform can be varied. When not used, the
control pin should be bypassed to ground with a 0.01µF capacitor to prevent any noise problems.
Pin 6 Threshold Voltage: This is the non-inverting input terminal of comparator 1, which monitors
the voltage across the external capacitor. When the voltage at this pin is ≥ threshold voltage 2/3VCC ,
the output of comparator 1 goes high, which in turn switches the output of the timer low.
Pin 7 Discharge: This pin is connected internally to the collector of transistor Q1 .When the output is
high Q1 is off and acts as an open circuit to the external capacitor C connected across it. On the other
hand, when the output is low, Q1 , is saturated and acts as a short circuit, shorting out the external
capacitor C to ground.
Pin 8 +𝐕𝐂𝐂 : The supply voltage of +5V to +18V is applied to this pin with respect to ground (pin 1).
Ground 1 8 +VCC
Trigger 2 7
555 Discharge
Output 3 6 Threshold Voltage
Reset 4 Control Voltage

5
(a)

+VCC
8 5 Control Voltage
Vref
R 4
6 Q2 Reset
Comparator
Threshold 1 2
V
3 CC
R 1
V
3 CC Comparator 2
Trigger
2
R
7
Discharge
Q1 Flip - Flop
Output stage
3
Output Ground
(b)
(a) 555 Timer Connection Diagram, (b) Block Diagram
The 555 as a Monostable Multivibrator

A monostable multivibrator, often called a one-shot multivibrator, is a pulse-generating circuit in
which the duration of the pulse is determined by the RC network connected externally to the 555
timer. In a stable or standby state the output of the circuit is approximately zero or at logic-low
level. When an external trigger pulse is applied, the output is forced to go high (≅VCC ). The time the
output remains high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logic-low stable state. The output
stays low until the trigger pulse is again applied. Then the cycle repeats. The monostable circuit has
only one stable state (output low), hence the name monostable. Normally, the output of the
monostable multivibrator is low.
+VCC
RA
+ 8 4 Reset
Trigger 7
0 Input 2 6
555 C
Output 3 1
5
C1
(a) 0.01μF

+VCC
+
Decoupling C1
RA −
Capacitor
R 5 kΩ Vref
6 Comparator 1
2 + 4
VCC Q2
Threshold 5 3 − Reset
Control Voltage
R 5 kΩ
"on" load
Normally
Comparator 2 Flip - Flop
+ RL
1
+ V
2 3 CC
−
0 Trigger
7
Input
Discharge
Output 3
R 5 kΩ Stage
Q1
Output NOrmally
C
"off" load
RL
1 Ground
(b)
Figure (a) Shows the 555 Configured for Monostable Operation. To better Explain the Circuit’s
Operation, the Internal Block Diagram is Included in Figure (b)
+VCC
Trigger Input
0V
T
≅ VCC
0V
Output Waveform
tP
2
V
3 CC
0V
Capacitor Voltage (c)
Figure (a) and (b) 555 Connected as a Monostable Multivibrator (c) Input and Output Waveforms
Monostable Operation
According to figure (b), initially when the output is low, that is, the circuit is in a stable state,
transistor Q1 is on and capacitor C is shorted out to ground. However, upon application of a negative
trigger pulse to pin 2, transistor Q1 is turned off, which releases the short circuit across the external
capacitor C and drives the output high. The capacitor C now starts charging up toward VCC through
R A . However, when the voltage across the capacitor equals 2/3 VCC , comparator 1’s output switches
from low to high, which in turn drives the output to its low state via the output of the flip-flop. At the
same time, the output of the flip-flop turns transistor Q1 on, and hence capacitor C rapidly
discharges through the transistor. The output of the monostable remains low until a trigger pulse is
again applied. Then the cycle repeats. Figure (c) shows the trigger input, output voltage and
capacitor voltage waveforms. As shown here, the pulse width of the trigger input must be smaller
than the expected pulse width of the output waveform. Also, the trigger pulse must be a negative-
going input signal with an amplitude larger than 1/3 VCC
The time during which the output remains high is given by,
t P = 1.1R A C seconds
Where R A is in Ohms and C is in Farads
The 555 as an Astable Multivibrator

An astablemultivibrator, often called a free-running multivibrator, is a rectangular-wave-generating
circuit. Unlike the monostable multivibrator, this circuit does not require an external trigger to
change the state of the output, hence the name free-running. However, the time during which the
output is either high or low is determined by two resistors and a capacitor, which are externally connected to
the 555 timer.
Astable Operation: Figure (a) shows the 555 timer connected as an astable multivibrator. Initially,
when the output is high, capacitor C starts charging toward VCC through R A and R B . However, as
soon as voltage across the capacitor equals 2/3 VCC , comparator 1 triggers the flip-flop, and the
output switches low [see figure (b)]. Now capacitor C starts discharging through R B and transistor
Q1 . When the voltage across C equals 1/3 VCC , comparator 2’s output triggers the flip-flop, and the
output goes high. Then the cycle repeats. The output voltage and capacitor voltage waveforms are
shown in figure (b)
+VCC = +5 V
RA 4
7
3
555
6 Output
RB
2 1 5
C1
C
0.01 μF
(a)
Output Voltage
T
≅ VCC
0V
t
Capacitor Voltage
2 tc td
V
3 CC
1
V
3 CC
t
Charging Discharging
(b)
The 555 as an Astable Multivibrator (a) Circuit (b) Capacitor and Output Voltage Waveforms

As shows in this figure, the capacitor is periodically charged and discharged between 2/3 VCC and
1/3 VCC , respectively. The time during which the capacitor charges from 1/3 VCC to 2/3 VCC is equal
to the time the output is high and is given by
t c = 0.69(R A + R B )C
Where R A and R B are in Ohms and C is in Farads. Similarly, the time during which the capacitor
discharges from 2/3 VCC to 1/3 VCC is equal to the time the output is low and is given by
t d = 0.69(R B )C
Where R B is in Ohms and C is Farads. Thus the total period of the output waveform is
T = t c + t d = 0.69(R A + 2R B )C
This, in turn, gives the frequency of oscillation as
1 1.45
fo = =
T (R A + 2R B )C
The above equation indicates that the frequency fo is independent of the supply voltage VCC .
Often the term duty cycle is used in conjunction with the astable multivibrator. The duty cycle is the
ratio of the time t c during which the output is high to the total time period T. It is generally
expressed as a percentage. In equation form,
tc
% Duty cycle = × 100
T
RA + RB
= (100)
R A + 2R B
The duty cycle of the square wave is 50%. This means that, according to above Equation, the astable
multivibrator shown in Figure (a) will not produce square-wave output unless the resistance
R A = 0 Ω. However, there is a danger in shorting resistance R A to zero. WithR A = 0 Ω, terminal 7 is
connected directly to +VCC . When the capacitor discharges through R B and Q1 (pin 7), an extra
current is supplied to Q1 by VCC through a short between terminal 7 and +VCC, which may damage
Q1 and hence the timer.
Solved Examples
Example 1
In the figure shown, assume that the zener diode and operational amplifier to be ideal
(A) Draw the equivalent circuit and evaluate the gain ( Vo vs Vi ) of the circuit for
1 kΩ
Vz = 5 V
1 kΩ
Vi
+ Vo
1 kΩ −
i. Vi ≤ 0
ii. 0 < Vi < 5V
iii. Vi > 5V
(B) Sketch the gain (Vo vs Vi ) characteristics of the above circuit and label the salient
features.

Solution:
(A) i When Vi ≤ 0, zener diode is forward baised and is replaced by S.C. then the
equivalent circuit
1 kΩ
1 kΩ I Ideal zener
Vi I2 + Vo Vz = 5 V
a
1 kΩ −
I1 b
Vb − Va ≈ 0, Vb = Va = 0
Apply KCL at ′a′ I = I1 + I2
Vb = Va = 0
Vo −Vi −Vi
= +
103 103 103
Vo = −2Vi
Vo
= −2
Vi
ii. When 0 < Vi < 5 V
Then zener reverse biased and the current through it is (Since it is given that
ideal) Then the equivalent circuits
1 kΩ
Vi 1 kΩ
− Vo
Vo
∴ = −1
Vi
iii. When Vi > 5V zener operation in breakdown region and is replaced by the zener
voltage
1 kΩ
5V
1 kΩ If
Vi I2 _ Vo
a
1 kΩ +
I1
Apply KCL at ‘a’

I1 + I2 = If
Vi Vi − 5 −Vo
+ ( ) =
103 103 103
2Vi − 5 = −Vo , Vo = 5 − 2Vi
(B) The gain (or) transfer characteristics curve of the above circuit is
5
4 Vo
(i) 3
Vo
2
1
−5−4 −3−2−1
−1 12 3 4 5 6 7
−2
(ii)
−3
−4
−5
−6
−7 (iii)
−8
−9
Example 2
(A) For the circuit shown in figure
R1
R1
Vi − Vo
+
C R
V
(i) Calculate the transfer function Vo
i
(ii) Plot the amplitude and phase response as a function for R=R1
Solution:
(i) The given circuit is
Apply KCL at ‘b’
Vi − Vb Vb
( )=
1/SC R
(Vi − Vb )SCR = Vb
1 + SCR SCR
Vi = Vb ( ) , Vb = Vi ( )
SCR 1 + SCR
R1
R1
Vi a −
Vo
b
+
C R
Apply KCL at ′a′

Vi − Va Va − V0
( )=( ) ⇒ Vo = 2Va − Vi
R1 R1
Va = Vb
SCR
= 2Vi ( ) − Vi
1 + SCR
SCR − 1 Vo SCR − 1
= Vi [ ]⇒ =( )
1 + SCR Vi SCR + 1
(ii) The magnitude of transfer function is
Vo √(ωCR)2 + 1
| |= =1
Vi √(ωCR)2 + 1
The phase plot is
∠θ = π − 2 tan−1 (ωCR)
Vo
| |=1⇒
Vi
θ
Vo
| |=1 π
Vi
π/2
ω
f ω = 1/RC
Example 3
Figure below shows an Op-Amp amplifier. Find the output voltage in steady state
condition where (i) Switch is open (ii) S is closed
0.1 μF
S1
1 kΩ 1 kΩ 1 kΩ
If
− Vo
a
Vi = 1 V +
Solution:
(i) Vd ≈ 0 ⇒ Va ≈ 0 (when switch is open)
Apply KCL at ′a′
Vi − Va Va − Vo
= ⇒ −Vo = 2V1
103 2 × 103
⇒ Vo = −2 Volts
(ii) When ‘S’ is closed. The capacitor changes to the peak value. In steady state “C” acts as
O.C. Then again Vo = −2 Volts

Example 4
In the circuit of figure R s =2 kΩ, R L = 5 kΩ for the op – amp A = 105 , R i =100 kΩ, R o = 50
Vo
kΩ, for Vo = 10V. Calculate Vs and and estimate the input resistance of the circuit
Vs
+ Vo
Vs −
RL
Solution:
(i) Given Op-Amp circuit can be redrawn as
a − V
Rs
+
b R
~ Vs
The current entering into the Op-Amp terminal is zero

∴ Vo = Vs = Va = Vo′
Vo
Vo = Vs ⇒ =1
V1
When Vo = 10 V, Vs = 10 V
(ii) The input resistance of the circuit is
− V
R
+
Ri R
Vs
Vo = Vs and IS = 0
Vs
⇒ Zin = = R i = 100 kΩ
Is

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“Change will not come if we wait for some other

person or some other time. We are the ones we've

Operational Amplifiers and

Differential Amplifiers/ Instrumentation Amplifier

There are two types of Input Signals to the DA

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2. Common Mode: It is average of the two input voltages.

Analysis of Differential Amplifier

Small-signal Mode for Purely Differential Mode Input:

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Small Signal Mode for Purely Common Mode Input

i2 = i2 → Vx = (i1 + i2 )R E = 2i2 R E = 2i1 R E

Common Mode Rejection Ratio (CMRR)

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Different Input, Output Combinations

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The Ideal Op – Amp:

Basic Op-Amp Connection

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Common-Mode Rejection Ratio:

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Operation Showing Effect of Input Offset Voltage 𝐕𝐢𝐨

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Solution: The offset due to VIo is

Practical Op-Amp Circuits

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Closed-Loop Voltage Gain

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Non Inverting Amplifier (Voltage -Series Feedback Amplifier)

Non Inverting Amplifier with Feedback (Voltage-Series Feedback Amplifier)

Closed-Loop Voltage Gain

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Summary of Different Parameters for Non-Inverting and Inverting Amplifiers

Unity Follower: (Voltage Follower) (Voltage Buffer)

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Circuit for Subtracting Two Signals

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Solution: KCL at node A,

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Low – Pass High – Pass

Low – Pass Filter

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High – Pass Active Filter

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90° 180° 250° 360° 450° 540° Phase Angle (deg )

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Different Types of Operational Amplifiers and Converters

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Astable Multivibrator (Square Wave Generator)

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Pulse Generator (Monostable Multivibrator)

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Vo Vin < Vref

Zero – Crossing Detector

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