“I have not failed.

I’ve just found

10.000 ways that won’t work”.
…. Thomas A. Edison.

5
CHAPTER

Combinational and
Sequential Digital Circuits

Learning Objectives
After reading this chapter, you will know:
1. Arithmetic Circuits
2. Multiplexers
3. Decoders
4. Encoder
5. Demux
6. Code Converters
7. PROM’s and PLA’s
8. Latches and Flip-Flops
9. F/F Conversion
10. Counters and Shift Registers

Introduction
Digital circuits can be classified into two types
 Combinational Digital Circuits
 Sequential Digital Circuits

Combinational Digital Circuits

In these circuits “The outputs at any instant of time depends on the inputs present at that instant
only.”
 For the design of Combinational Digital Circuits Basic Gates (AND, OR, NOT) or Universal
gates (NAND, NOR) are used.
Examples for Combinational Digital Circuits are Half Adder, Full Adder, Half Subtractor, Full
Subtractor, Code Converter, Decoder, Multiplexer, Demultiplexer, Encoder, ROM, etc.

Combinational
I/P’s Digital CKT O/P’s

Combinational Digital Circuit

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 Combinational and Sequential Digital Circuits

I/P’s O/P’s
C. D. CKT

F/F
F/F

Sequential Digital Circuit

Sequential Digital Circuits

 The output at any instant of time not only depends on the present inputs but also on the
previous inputs or outputs. For the design of these circuits in addition to gates we need
memory elements flip-flop.
 Examples for sequential digital circuits are Registers, Shift register, Counters etc.

Combinational Digital Circuits

 Half Adder: A combinational circuit that performs the addition of two bits is called a “half-
adder”. It consists of two inputs and two outputs.
X Y Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Sum = X ⊕ Y = XY′ + X′ Y
Carry = XY
X Sum = X ⊕ Y
Y X Sum
H. A.
Y Carry
Carry =X Y

 Half Subtractor: It is a Combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if ‘1’ has been borrowed.
X Y Borrow Diff
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Diff. = X ⊕ Y = XY′ + X′Y X Diff. = X ⊕ Y

Borrow = X′ Y Y

X D Borrow =x’ y
H.S.
y B

Y Y
Y Y
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 Combinational and Sequential Digital Circuits

 Half adder can be converted into half Subtractor with an additional inverter.
 Full Adder: It performs the addition of three bits (Two Significant bits and a Pervious Carry)
and generates sum and carry.
X Y Z Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

X Sum
Y F. A
Z Carry

Sum = X  Y  Z
Carry = XY + YZ + ZX
= XY + Z(X  y)
X Y Z

Sum

Carry

Full Adder can be implemented by using two half adders and an OR Gate.
X Sum
H. A. H. A.
Y

Z Carry

Sum
=XYZ

Carry
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+ YZ
+ ZX
 Combinational and Sequential Digital Circuits

X
Y
Sum
Z

Carry

 Full Subtractor: It subtracts one bit from the other by taking pervious borrow into account
and generates difference and borrow.
Truth Table of Full Subtractor
X Y Z Borrow Difference
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

X Difference
Y F. S.
Z Borrow
Diff. = X  Y  Z
Borrow = X′Y + YZ + X′Z
X Y Z

Difference

Borrow

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 Combinational and Sequential Digital Circuits

 Full Subtractor can be implemented by using two Half-Subtractor and an OR Gate.

X Difference
H. S. H. S.
Y

Z Borrow

X
Y
Difference
Z

Borrow

 Full adder can be converted into Full Subtractor with an additional inverter.
 Four bit Binary parallel adder can be constructed by using three Full Adders and one half
Adder or by using four Full Adders with input carry for least significant bit Full Adder is zero.
 Four bit Binary parallel adder shown in figure is also called as Ripple Carry Adder.
B3 A3 B2 A2 B1 A1 B0 A0

FA3 FA2 FA1 FA0 Cin = 0

Cout S3 S2 S1 S0
B3 A3 B2 A2 B1 A1 B0 A0

FA3 FA2 FA1 HA0

Cout S3 S2 S1 S0

 Carry Look- Ahead Adder is faster than Ripple Carry Adder.

 Full Adder is an example for 1-bit adder.

Example: Implement Boolean function F = ABC′ + A′ C + B′C using half adder.

Solution: F = ABC + C(A + B)
= ABC + C(AB)
= (AB) ⊕C
A S
A H.A.
S
B HA C S F= (AB) ⊕C
B C H.A. S
HA C
C

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 Combinational and Sequential Digital Circuits

Decoder
A Decoder is a logic circuit that converts an n bit binary input code into M (=2n ) output lines
such that each output line will be activated for only one of the possible combinations of inputs.
(or)
A Decoder is a combinational circuit that converts binary information from ‘n’ input lines to a
maximum of 2n unique output lines.
E.g. 2 × 4 line Decoder (It is also called one four line decoder)

 Decoders are available in two different types of output forms

(1) Active high output type Decoders
(2) Active low output type of Decoders
 Active high output type of Decoders are constructed with AND Gates and active low output
type of Decoders are constructed with NAND Gates.

Truth Table of active high output type of Decoder

X Y 𝐃𝟎 𝐃𝟏 𝐃𝟐 𝐃𝟑
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

X Y

D0
X D0 = X′Y′
D1
2×4 D1 = X′Y
Y D2
D3 D2 = XY′

D3 = XY

 Active low output types of decoders will give the output low for given input combination and
all other outputs are high.

Truth Table of active low output type of Decoder

X Y D0 D1 D2 D3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

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 Combinational and Sequential Digital Circuits

X Y

X D0
D0 = X′Y′
D1
2×4 D1 = X′Y
Y D2
D3 D2 = XY′

D3 = XY

 3 to 8 line decoder is also called “Binary-to-Octal decoder” or “Converter”. It is also called 1 of

8 decoder, because only one of the 8 outputs is active at a time.
 Decoders are widely used in the memory system of computer, where they respond to the
address code input from the CPU to activate the memory storage location specified by the
address code.
 Decoders are also used to convert Binary data to a form suitable for displaying on Decimal
read outs.
 Decoders can be used to implement combinational circuits, Boolean functions etc.

Example: Implement Full –Adder with a Decoder

Solution: S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
D0
D1
D2
S
A2 D3
3×8
D4
A1
Decoder

A0

D5
D6 C
D7

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 Combinational and Sequential Digital Circuits

Example: Implement 3× 8 decoder using 2 × 4 decoder

Solution:
D0 D0
B A1 D1 D1
C A0 D2 D2
EN D3 D3

D0 D4
B A1 D1 D5
C A0 D 2 D6
EN D 3 D7

Demultiplexer
A Decoder with enable input, acts as “Demultiplexer.” A Demultiplexer is a circuit that receives
information on a single line and transmits that information on one of 2n possible output lines.
The selection of specific output line is controlled by the bit values of ‘n’ selection lines.
E A B 𝐃𝟎 𝐃𝟏 𝐃𝟐 𝐃𝟑
1 X X 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1

D0
D1
E 1×4
D2
D3

A B

Multiplexer
Multiplexing means transmitting a large number of information units over a smaller number of
channel lines. “A Digital multiplexer is a combinational circuit that selects Binary information
from one of many inputs lines and direct it a to single output line. The selection of a particular
lines is controlled by a set of selection lines. Normally, there are 2n input lines and ‘n’ selection
lines whose bit combinations determine which input is selected.”

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 Combinational and Sequential Digital Circuits

I0
I1
4×1 Y
I2 MUX
I3

S1 S0

𝐒𝟏 𝐒𝟎 𝐘
0 0 I0
0 1 I1
1 0 I2
1 1 I3

 Multiplexers can be used for the Implementation of Boolean Functions, Combinational

Circuits. They can also be used for “Parallel to Serial Conversion”.
 Multiplexer is also called “Data Selector or Universal Circuit”.
 All three Variable Boolean Equations can be Implemented by using 8 × 1 multiplexer without
using any additional Gates. Some but not all three Variable Boolean equations can also be
implemented with 4×1 mux without using any additional Gates.

Example: Implement Boolean Function F(A, B, C) = ∑(1, 3, 5, 6) with 4 × 1 mux

Solution: Truth Table

A B C F
0 0 0 0
0 0 1 1 C I0
C I1
0 1 0 0 Y
0 1 1 1 C I2
C I3
1 0 0 0 S1 S0
1 0 1 1
1 1 0 1 A B
1 1 1 0 A

F = ∑(1, 3, 5, 6)
When AB = 00, F is equal to C, similarly for all other combinations of AB, input to mux
is defined in terms of C.

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 Combinational and Sequential Digital Circuits

 Implementation of Higher Order MUX Using Lower Order MUX:

⇒ 4: 1MUX by 2: 1MUX
I0
2.1
I1
S0 2.1 Y
I2
2.1 S1
I3
S0
Total number of 2: 1 MUX = 3
 To implement 2n : 1 MUX by using 2 : 1 MUX, the total number or 2 : 1 MUX required is
(2n − 1)
Given MUX To be Implemented Required
MUX No of MUX
4:1 16 : 1 4+1=5
4:1 64 : 1 16 + 4 + 1 = 21
8:1 64 : 1 8+1=9
8:1 256 : 1 32 + 4 + 1 = 37

 MUX circuit or IC’s may have an enable input to control operation of the unit. When it is input
is in a given Binary state the output is disabled and when in the other state the circuit
functions as a normal Multiplexer.
 The MUX is a very useful MSI function and has a multitude of applications
 It is used for connecting two or more sources to a single destination among computer units
and it is useful for constructing a common bus system.

MUX as an Universal Logic Gate

1. Buffer : Y = Output = A

I0 2 : 1
0
MUX Y
1 I1 S

2. NOT-Gate/Inverter : Y = A
I0
1 2:1
MUX Y
0 I1 S

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 Combinational and Sequential Digital Circuits

3. AND-Gate : Y = AB

0 I0
2:1
MUX Y
B I1 S

4. OR-Gate : Y = A + B

B I0 2 : 1
MUX Y
1 I1 S

5. NOR-Gate : Y = A + B

̅
B I0 2 : 1
MUX Y
0 I1 S

6. NAND-Gate : Y = AB

1 I0 2 : 1
MUX Y
̅
B I1 S

7. EX-OR-Gate : Y = A ⊕ B = AB + AB

B I0 2 : 1
MUX Y
̅
B I1 S

8. EX-NOR Gate : Y = A ⊙ B = AB + A B

̅
B I0
2:1
MUX Y
B I1 S

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 Combinational and Sequential Digital Circuits

Example: The Boolean function implemented in the figure using two input multiplexers is
C 0
0 0
f
̅
C A
1 1

B E
̅C + ABC̅
(A) AB (C) ̅ BC + A
A ̅B̅C̅
(B) ABC + AB ̅C̅ (D) ̅̅̅̅
ABC + A̅ BC̅
Solution: From the figure we have
E = output of 1st MUX
=B⨁C=B ̅C + BC̅
And f=̅ E 0 + E A = EA
f = AB̅C + ABC̅

Example: How many minimum number of 2 : 1 MUX required for implement the Half Adder
(H.A)
(A) 2 (C) 4
(B) 3 (D) None of these
Solution: We know, H.A a SUM = A ⊕ B and a carry A and B are the two input variable i.e.,
A Sum= A⨁B
H.A
B Carry = AB
⇒ For carry we required an AND-Gate as
0 I0 2 : 1
MUX Carry=AB
B I1 S

A
⇒ For SUM we required an EX-OR Gate as
B I0 2 : 1
MUX Sum = A⨁B
̅
B I1 S

A
B as input is not available, so we require an inverter circuit also as
1 I0 2 : 1
MUX B
0 I1 S

B
Finally, to implement a H.A. we required 3, 2 : 1MUX
[For SUM ⇒ 2 and Carry ⇒ ×1]

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 Combinational and Sequential Digital Circuits

Example: What are the minimum number of 2 to 1 multiplexers required to generate a 2-input
AND Gate and a 2-input Ex-OR Gate?
(A) 1 and 2 (C) 1 and 1
(B) 1 and 3 (D) 2 and 2
Solution: [Ans. A]
For AND Gate ⇒ 2:1 MUX required = 1 and for EX-OR Gate ⇒ 2 : 1 MUX required = 2.

Example: Implementation of given function using 8 to 1 multiplexer F(A, B, C, D)

= Σ (1, 3, 11, 12, 13, 14, 15)
Solution: Total number of variable (n) = 4(A, B, C, D)
Number of select lines (n − 1) = 3(B, C, D)
The given function has 4 variable, so the 16 possible minterms (0 – 15) are entered in
the implementation table, the first of minterms (0 – 7) are entered in the first row
because these minterms are complement minterms (variable A is complemented) and
the second group (8 – 15) minterms are entered in the second row.

Implementation Table
I0 I1 I2 I3 I4 I5 I6 I7
̅ 0 0 ① 2 ③ ④ 5 6 7
A
A 1 8 9 10 ⑪ ⑫ ⑬ ⑭ ⑮
0 ̅ 0 1 1 A A A
A
Given multiplexer is 8:1
Number of input lines 8(I0 , I1 , I2 , I3 , I4 , I5 , I6 , I7 )

Logic Diagram:
0
B C D

I0
̅
A I1
I2
1 I3 8:1 y
I4 MUX
I5 MUX
A I6 MUX
I7

Example: Implement the following Boolean function using

8 : 1 MUX F(A, B, C, D) = Σ m(0, 1, 2, 4, 6, 9, 12, 14)
Solution: Select lines are B, C and D
I0 I1 I2 I3 I4 I5 I6 I7
A̅ ⓪ ① 2 3 ④ 5 ⑥ 7
A 8 ⑨ 10 11 ⑫ 13 ⑭ 15
̅ 1 A
A ̅ 0 1 0 1 0

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 Logic Diagram:
B C D

A I0
I1
I2
I3 8:1
F
1 I4 MUX
I5
I6
0 I7

Example: Implement the following Boolean function with 8 : 1

F(A, B, C, D) = ΠM(0, 3, 5, 6, 8, 9, 10, 12, 14)
Solution: The given maxterms are inverted to obtain minterms. From the minterms we can
implement the above Boolean function by using 8 : 1 multiplexer. Select lines are B, C
and D, the input variable is A.
F(A, B, C, D) = Σm(1, 2, 4, 7, 11, 13, 15)
I0 I1 I2 I3 I4 I5 I6 I7
̅
A 0 ① ② 3 ④ 5 6 ⑦
A 8 9 10 ⑪ 12 ⑬ 14 ⑮
0 A ̅ A ̅ A A ̅ A 0 1

Logic Diagram:
0 B C D

I0
A′ I1
I2
I3 8:1 F
I4 MUX
A I5
I6
1 I7

Example: Implement the following Boolean function with 8 : 1 multiplexer

F(A, B, C, D) = Σm(0,2,6,10,11,12,13) + Σd(3, 8, 14)
Solution: The Boolean function has three don’t care conditions which can be treated as either
0’s or 1’s. In this example don’t care condition is consider as 1.
I0 I1 I2 I3 I4 I5 I6 I7
̅
A ⓪ 1 ② ③ 4 5 ⑥ 7
A ⑧ 9 ⑩ ⑪ ⑫ ⑬ ⑭ 15
1 0 1 1 A A 1 0

Logic Diagram:

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 B C D
1

I0
I1
I2
I3 8:1
F
MUX
I4
A
I5
I6
I7
0

 Encoder: A decoder identifies a particular code present at the input terminals of the circuit.
The inverse process is called “Encoding.”An Encoder has number of inputs (2n ), one and only
one of which is in the high state or active and an n-bit code is generated upon which of the
inputs is excited.

ROM (Read Only Memory)

ROM is nothing but the combination of “Decoder and Encoder”. It is a semiconductor memory,
and which is permanent memory ROM can also be defined as a “Simple Code Conversion unit”.
2N × M M outputs
N inputs

 ROM = Fixed AND, Programmable OR

 PAL = Programmable AND, Fixed OR
 PLA = Programmable AND, Programmable OR

Sequential Circuits
 Two cross coupled inverters will form a basic latch which can store one bit of information.
 Flip-Flops: Flip-Flop is also called “Bistable Multivibrator”. It can store one bit of information.
 In a Flip-Flop one output is always complement of the other output.
 Flip-Flop has two stable states.

Flip Flops
Clocked S-R Flip-Flop: It is called set reset Flip-Flop.
𝐒𝐧 𝐑𝐧 𝐐𝐧+𝟏
0 0 Qn
0 1 0
1 0 1
1 1 ∗

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 Set S Pr
Q
Clock CLK
Q
Reset R Cr

Q n+1 = SQn + RQ n

PRESET

Set N3
N1 Q

CLK

Reset N2 N4 Q′

CLEAR

 N1 And N2 Form a basic latch, N3 and N4 are called Steering Gates or Control Gates, because
they are used to control the output.
 S and R inputs are called “synchronous inputs”. Preset (Pr) and Clear (Cr) inputs are called
“Direct inputs or asynchronous inputs”.
 The output of the Flip-Flop changes only during the clock pulse. In a Clock duration the
output of the Flip-Flop does not change.
 During normal operation of the Flip-Flop, preset and clear inputs must be always high.
 The disadvantage of S-R Flip-Flop is for S=1, R=1 output cannot be determined. This is
eliminated in J-K Flip-Flop.
 S-R Flip Flop can be converted to J-K Flip-Flop by using the two equation S=JQ′ and R= KQ.
Truth Table
Jn Kn Q n+1
0 0 Qn
0 1 0
1 0 1
1 1 Q′n

Q n+1 = JQ′n + K ′ Q n

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 J
S Pr Q
J Q
Q′
CLK
CLK

R Q′
Q Cr K Q′
K

 Race Around Condition is present in the J-K Flip Flop, when both J=K=1.
 Toggling the output more than one during the clock pulse is called “Race Around Problem”.
 The race around problem in J-K Flip-Flop can be eliminated by using edge triggered Flip-Flop
or master slave J-K Flip Flop or by the clock signal whose pulse width is less than or equal to
the propagation delay of Flip-Flop.
 Master-slave flip-flop is a cascading of two J-K Flip-Flops. Positive or direct clock pulses are
applied to master and inverted clock pulses are applied to the slave flip-flop.

D-Flip-Flop: It is also called a “Delay Flip-Flop”. By connecting an inverter in between J and K

input terminals, D Flip-Flop is obtained. K always receives the compliment of J.
Truth Table
D Q′n +1
0 0 Q n +1 = D
1 1

D
J D
Q Q
CLK CLK
K Q′ Q′

 D Flip-Flop is used to provide delay. The bit on the input D line is transferred to the output in
the next clock pulse.

T Flip-Flop: J−K Flip-Flop can be converted into T- Flip-Flop by connecting J and K input
terminals to a common point. If T=1, then Q n+1 = ̅̅̅̅
Q n . This unit changes state of the output with
each clock pulse and hence it acts as a toggle switch.
Truth Table
T Q n +1
0 Qn
1 Qn
Q n +1 = TQ′n + T ′ Q n = T Q n

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 T
J T
Q Q
CLK CLK
K Q′ Q′

 If X kHz clock signal is applied to a T Flip-Flop when T=1, then the output (Q) signal
frequency is given by X/2kHz. Thus it acts as a frequency divider.

Excitation Table:
Qn Qn + 1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

Qn Qn + 1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

Qn Qn + 1 D
0 0 0
0 1 1
1 0 0
1 1 1

Qn Qn + 1 T
0 0 0
0 1 1
1 0 1
1 1 0

Setup Time (𝐭 𝐬 ): Time interval immediately preceding the active transition of clock signal during
which the control input must be maintained at the proper level.
Hold Time (𝐭 𝐇): The time interval immediately following the active transition of the clock signal
during which the synchronous control input must be maintained at the proper level.

D D D Q D Q
C C CLK ̅ ̅
CLK Q
Q
(Positive Edge) (Negative Edge) (+Ve Level) (−Ve Level)

Characteristic Tables Characteristic Excitation Tables

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 Equations
JK Flip-Flop Q(t) Q(t+1) J K
J K Q(t+1) 0 0 0 ×
0 0 Q(t) No Change Q(t + 1) = JQ′ + K′Q 0 1 1 ×
1 0 1 Set 1 0 × 1
0 1 0 Reset 1 1 × 0
1 1 Q(t) Complement
D Flip-Flop Q(t + 1) = D Q(t) Q(t+1) D
T Q(t+1) 0 0 0
0 0 Reset 0 1 1
1 1 Set 1 0 0
1 1 1
T Flip-Flop Q(t + 1) = T ⊕ Q Q(t) Q(t+1) T
T Q(t+1) = TQ′ + T′Q 0 0 0
0 Q(t) No Change 0 1 1
1 Q(t) Complement 1 0 1
1 1 0
SR Flip-Flop
S R Q(t+1) Q(t) Q(t+1) S R
0 0 Q(t) No Change 0 0 0 ×
0 1 0 Reset 0 1 1 0
1 0 1 Set 1 0 0 1
1 1 ? Unpredictable 1 1 × 0

Conversion Equations:

JK → T JK → T JK → D D → JK D→T D → SR

J=T ⊗ J=D D = JQ′ + K′Q D = T ⨁ Qn ⨂

K=T T → SR K=D ̅ SR → JK SR → D SR → T
T → JK × T→D ̅n
S = JQ S=D ̅n
S = TQ
̅ n + JK + KQ n
T =JQ T = D⨁Q n R = K Qn R=D ̅ R = Qn

Truth Table of JK Flip-Flop Excitation Table of T Flip-Flop

J K Q n Q n+1 Q n Q n+1 T
0 0 0 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 1 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Conversion Table:
J K Q n Q n+1 T
0 0 0 0 0
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0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1

KQ n
T 00 01 11 10
J 0
0 0 1 0

1 1 0 1 1

̅ nJ
T = KQ n + JK + Q

T→D
D Q n Q n+1
0 0 0
0 1 0
1 0 1
1 1 1

Qn Q n+1 T
0 0 0
0 1 1
1 0 1
1 1 0

D T Q

̅
Q

Check
D=0 T = Q n Q n+1 = 0
D=1 T=Q ̅ n Q n+1 = 1

K
T Q

̅
Q
J

Check
J=K=0 →T=0 → Q n+1 = Q n
J = 1, K = 0 →T=Q ̅n Q n+1 = 1
J = 0, K = 1 → T = Qn Q n+1 = 0

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 J=K=1 →T=1 Q n+1 = ̅̅̅̅
̅n
Q

Required
D Qn Q n+1 T
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

Qn
D 0 1
0 0 1
1 1 0
̅ n = D ⊕ Qn
̅ + DQ
T = Qn D

Registers and Shifts Registers

 A register is a group of Flip-Flops used to store binary information. An n-bit register can store
n-bit information.
 A register which is able to shift the information either from left to right or from right to left is
called a “shift register”.
I. Shift Register Can Perform Four Different Operations:
1. Serial Input Serial Output
2. Serial Input Parallel Output
3. Parallel Input Parallel Output
4. Parallel Input Serial Output
II. Universal Shift Register: A register which is able to shift the information from left to right
or from right to left and which can perform all four operations is called Universal Shift
Register.
III. Applications of Shift Registers:
1. Serial to Parallel Conversion (It is also called Spatial to Temporal Code Conversion).
2. Parallel to Serial Conversion (It is also called Temporal to Spatial Code Conversion).
3. Sequence Generator.
4. Multiplication and Division.
5. Ring Counter and Twisted Ring Counter.
6. Digital Delay Line (Serial Input and Serial Output Operations).

Left shift operation is nothing but multiplied by 2.

E.g.: Q 3 Q 2 Q1 Q 0

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 0 1 0 1 =5

1 0 1 0 = 10
Shift left by n – positions is equivalent to multiplication by 2n .
 If least significant bit = 0, then Right Shift operation by one position is same as Division by 2.
E.g.: Q 3 Q 2 Q1 Q 0
1 0 1 0 =1
0

0 1 0 1 =5
 If L.S.B = 1, then Right Shift operation gives integer division by 2.
E.g.: Q 3 Q 2 Q1 Q 0
0 1 0 1 =5
0

0 1 0 =2 (Instead of 2.5)
 Ring Counter: Shift register can be used as ring counter when Q0 output terminal is connected
to serial input terminal.
 An n-bit ring counter can have “n” different output states. It can count n-clock pulses.
 Ring Counter

Q2 Q1
D Q D Q D Q
D D Q0

D
CLK
001 100 010

Mod – 3, Divide by 3 Counter, N: 1 counter

 Twisted Ring Counter: It is also called “Johnson’s Ring Counter”. It is formed when ̅̅̅̅
Q 0 output
terminal is connected to the serial input terminal of the shift register.
 An n-bit twisted ring counter can have maximum of 2n different output states.

Q2 Q1 Q0
D Q D Q D Q
D D D

CLK

000 100 110 111

001 011

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 Mod – 6, Divide by 6, 2N: 1 Counter

Counters
 The Counter is driven by a clock signal and can be used to count the number of clock cycles.
Counter is nothing but a frequency divider circuit.
 Two types of counters are available:
1. Synchronous 2. Asynchronous
 Synchronous counters are also called “Parallel Counters”. In this type clock pulses are applied
simultaneously to all the Flip-Flops.
 Asynchronous counters are also called “Ripple or Serial Counters”. In this type of counters the
output of one Flip-Flop is connected to the clock input of next Flip-Flop and so on.
 Ripple Counter (Asynchronous):
Q0 Q1 Q2

1 D 1 D 1 D
J Q J Q J Q

CLK CLK CLK CLK

1 K 1 K 1 K

Combinational Circuit Which Decides Whether up Counter or Down Counter.

CLK
X
̅
Q

For Up – Counter, X = 1 So, CLK = Q

For Down – Counter, X = 0 So, CLK = Q
 A counter having n-Flip-Flops can have 2n output states i.e., it can count 2n clock pulses
(0 to 2n − 1).
 The largest Binary number that can be represented by an n-bit counter has a Decimal
equivalent of (2n − 1).
E.g.: n = 3, then 2n − 1 = 23 − 1 = 7.
 A counter can be made to count either in the ‘up mode’ or in the ‘down mode’.
 Synchronous Counters are faster than asynchronous Counters.
 The modulus of a counter is the total number of states through which the Counter can
progress. For example mod-8 Counter is having 8 different states (000 to 111).
 The output signal frequency of Mod-n Counter is 1/n th of the input clock frequency.
Hence that Counter is also called Divide by n Counter.
 The number of Flip-Flops (n) required to Construct Mod N Counter can be obtained from the
following formula
2n−1 < N ≤ 2n .
 A decade counter is also called Mod- 10 or Divide by 10 Counter. It requires 4 Flip-Flops.

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 Any Binary Counter can be a modulus Counter where as the modulus Counter need not be a
Binary Counter.
 Six Flip-Flops are required to construct mod-60 Counter.
 Two types of synchronous Counters are available.
1. Series Carry
2. Parallel Carry

Finite State Machines

Introduction to FSM: Any digital system will have some control part, why digital system, every
system will have two parts hard and soft like hardware and software. Similarly, any system, any
digital system will have two paths one is known as data path and second is known as control
path.
Finite State Machine (FSMs) is commonly used to realize the control part. An FSM can be
diagrammatically represented by a state-transition diagram in which labelled nodes represent
states and labelled directed edges represent transition among the states. State transition is
generally indicated with i/o where ‘i’ indicates input and ‘o’ indicates output. Also, sometimes
state transition is represented only with input.
The behaviour of state machines can be observed in many devices in modern society performing
a predetermined sequence of actions depending on a sequence of events with which they are
presented. Simple examples are vending machines which dispense products when the proper
combination of coins are deposited, elevators which drop riders off at upper floors before going
down, traffic lights which change sequence when cars are waiting and combination locks which
require the input of combination numbers in the proper order.

Design of FSM
Here is an example of a designing a finite state machine, worked out from start to finish.
Step 1: Describe the machine in words.
In this example, we’ll be designing a controller for an elevator. The elevator can be at one of two
floors: Ground or First. There is one button that controls the elevator, and it has two values. Up
or Down. Also, there are two lights in the elevator that indicate the current floor. Red for Ground,
and Green for First. At each time step, the controller checks the current floor and current input,
changes floors and lights in the obvious way.

Step 2: Draw the FSM diagram

In this diagram, the bubbles represent the states, and the arrows represent state transitions.
The arrow labels indicate the input value corresponding to the transition. For instance, when

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the elevator is in the Ground state, and the input is Up, the next state is First. The information in
the brackets indicates the output values for the lights in each state.

Step 3: Select numbers to represent states and values. Before converting the above FSM diagram
to a circuit, we need to represent every value in our example as a binary number. Here is some
convenient numbers to use.
Ground = 0 Down = 0 Off = 0
First = 1 Up = 1 On = 1

Step 4: Write the truth table

From the FSM diagram, its easy to read off the correct truth table.
Current State Input Next State Red Green
0 0 0 1 0
0 1 1 1 0
1 0 0 0 1
1 1 1 0 1

Step 5: Draw a “big picture” view of the circuit

Here is the finite-state machine circuit, with many details missing. The variable names have been
abbreviated. The dashed boxes indicate the parts (let’s call them “sub circuits”) that we still need
to design.

E.g.: Design a sequence detector that produces ‘1’ when three ones appear sequentially at the
input.
1/0 1/0
0/0
S1 S2 S3
0/0

0/0

1/1

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The state transition diagram shown in the figure above produces ‘1’ when five ones appear
sequentially at the input can be represented with the help of three states S1, S2, S3. Let us
consider S1 as initial state.
Step 1: Present State S1, Next State S2
(a) If input is 1, we move from S1 to S2 with state transition represented by 1/0 as input is 1
and output is zero.
(b) If Input is 0, we move from S2 to S1 inorder to restart the count of three consecutive ones. It
is represented by 0/0 where both input and output are zeros.
Step 2: Present State S2, Next State S3, Previous State S1
(a) f input is 1, we move from S2 to S3 with state transition represented by 1/0 as input is 1 and
output is zero.
(b) If Input is 0, we move from S2 to S1 inorder to restart the count of three consecutive ones. It
is represented by 0/0 where both input and output are zeros.
Step 3: Present State S2, Next State S3, Previous State S1
(a) If input is 1, we move from S3 to S1 with output becoming 1 as three consecutive ones have
been successfully been detected now moving back to initial state inorder to restart the
process. State transition represented by 1/1 as input is 1 and output is 1.
(b) If Input is 0, we move from S3 to S1 inorder to restart the count of three consecutive ones. It
is represented by 0/0 where both input and output are zeros.

The state machines are modelled using two basic types of sequential networks - Mealy and
Moore. In a Mealy machine, the output depends on both the present (current) state and the
present (current) inputs. In Moore machine, the output depends only on the present state.

Mealy FSM
A general model of a Mealy sequential machine consists of a combinatorial network, which
generates the outputs and the next state, and a state register which holds the present state as
shown below. The state register is normally modelled as D flip-flops. The state register must be
sensitive to a clock edge. The other block(s) can be modelled either using the always procedural
block or a mixture of the always procedural block and dataflow modelling statements; the
always procedural block will have to be sensitive to all inputs being read into the block and must
have all output defined for every branch in order to model it as a combinatorial block. The two
blocks Mealy machine can be viewed as

Input Next State Current

and Output State
logic Register
Clock
Outputs

Moore FSM
A general model of a Moore sequential machine is shown below. Its output is generated from the
state register block. The next state is determined using the present (current) input and the
present (current) state. Here the state register is also modelled using D flip-flops. Normally
Moore machines are described using three blocks, one of which must be a sequential and the

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other two can be modelled using always blocks or a combination of always and dataflow
modelling constructs.

Input Current Outputs

Next State Output
State
logic logic
Register
Clock

Example: The state transition diagram for the logic circuit shown is

2-1 MUX
D Q X1
Y
CLK Q X0
Select

A
A=1 A=0 A=0 A=0
A=1 A=1
(A) (B)
Q=0 A=0 Q=1 Q=0 A=1 Q=1

A=0 A=1 A=1 A=1

A=0 A=0
(C) (D)
Q=0 A=1 Q=1 Q=0 A=0 Q=1

In this example, we have a D-Flip-flop with output Q and a 2×1 multiplexer with
selection line A. Now, if A=0, then Y=X0 and for A=1 then Y=X1 is selected.
From the options, Q has two values 0 and 1 respectively.
For Q=1, then Q̅ = 0.
If A = 0 then Y = X0 = Q ̅ = 0, Now next state is Q = 0
If A = 1 then Y = X1 = Q = 1, Now next state is Q = 1 which means same state
For Q = 0, then Q̅=1
If A = 0 then Y = X0 = Q ̅ = 1, Now next state is Q = 1
If A = 1 then Y = X1 = Q = 1, Now next state is Q = 0 which means same state
So, the Answer is Option D

Example: The digital logic shown in the figure satisfies the given state diagram when Q1 is
connected to input A of the XOR gate. Suppose the XOR gate is replaced by the XNOR
gate. Which one of the following options preserves the state diagram? Suppose the
XOR gate is replaced by an XNOR gate. Which one of the following options preserves
the state diagram?
(A) Input A is connected to Q2
(B) Input A is connected to Q2
(C) Input A is connected to Q1 and S is complemented
(D) Input A is connected to Q1

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 S=0

S=1
A 00 01
D1 Q1 D1 Q1
S=0
S=1 S=1
S S=0
Q1 Q2
CLK
10 11
S=1

S=0
Solution: [Ans. D]
The input of D2 flip-flop is
D2 = Qi s + Q i s(∵ A = Q i )
The alternate expression for EX-NOR gate is =A ⊕ B = A ⊕ B = A ⊕ B
So, if the Ex-OR gate is substituted by Ex-NOR gate input A should be connected to Qi
D2 = Qi S + Q i s = Qi S + Qi S (∵ A = Qi )
= Q i S + Qi S

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