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LOGIC FAMILIES
Transistor as a switch
Typical npn Transistor Parameters
INPUT OUTPUT
X Y Z
H H L
H L L
L H L
L L H
Digital IC specifications (or)
characteristics of digital logic
families
• The most useful specifications or feature to be concerned of IC logic
families:
– Threshold voltage
– Propagation delay
– Power dissipation
– Fan-in
– Fan-out
– Voltage and current requirement
– Noise Margin
– Operating temperature
– Speed power product
Digital IC Specifications
– Threshold voltage: The voltage at the input of a gate which causes a change
in the state of the output from one logic level to the other.
– Propagation delay: Time interval b/w the application of an i/p pulse &
occurrence of resulting o/p pulse.
• The average transition-delay time for the signal to propagate from
input to output when the binary signal changes in value.
• A pulse through a gate takes a certain amount of time to propagate
from input to output. This interval of time is known as the propagation
delay of the gate.
• Average transition delay time tpd = (tPLH + tPHL) /2
Logic families: propagation delay
• High state fan-out : the fan-out of the gate when its output is logic
1-driving gate sources current
• Low state fan-out : the fan-out of the gate when its output is logic
0- driving gate sinks current
• Actual fan out is smaller of these two numbers.
Logic families: Voltage levels
VOH(min) – The minimum voltage level at an output in the logical “1”
state under defined load conditions
VOL(max) – The maximum voltage level at an output in the logical
“0” state under defined load conditions
VIH(min) – The minimum voltage required at an input to be
recognized as “1” logical state
VIL(max) – The maximum voltage required at an input that still will
be recognized as “0” logical state
Logic families: current requirements
IOH – Current flowing into an output in the logical “1” state under
specified load conditions
IOL – Current flowing into an output in the logical “0” state under
specified load conditions
IIH – Current flowing into an input when a specified HI level is
applied to that input
IIL – Current flowing into an input when a specified LO level is
applied to that input
Noise margin
• The unwanted signals are referred to as noise
• Noise margin is the maximum noise added to an input signal of a
digital circuit that does not cause an undesirable change in the
circuit output .
• High state noise margin is the difference between the lowest
possible high output and the minimum input voltage required for a
HIGH.
• Low state noise margin is the difference between the largest
possible low output and the maximum input voltage required for a
LOW.
- operating temperature
• The IC gates and other circuits are temperature sensitive.
• They are designed to operate satisfactorily over a specified range of
temperature.
• Range for commercial application is 0 ֯to70 ֯C, industrial 0 ֯to85 ֯C and
for military applications -55 ֯to 125 ֯C.
– Speed power product
• Multiply the gate propagation delay by the gate power dissipation
• Smaller value is desirable. The smaller value gives better overall
performance.
• It has the units of energy and expressed in picco-joules
• The IC has an average propagation delay of 10ns and an average power
dissipation of 5mw, the speed power product is
10 ns*5mw=5*10^-12 watts-seconds= 5 picco-joules
COMPARISON OF LOGIC FAMILIES
UNIT-II
LOGIC FAMILIES
IC digital logic families
– RTL(Resistor-transistor logic)
– DTL(Diode-transistor logic)
– ECL(Emitter-coupled logic)
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Diode Logic (DL)
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Resistor-Transistor Logic (RTL)
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RTL--NOR
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Diode-Transistor Logic (DTL)
A B NAND o/p
0 0 1
0 1 1
1 0 1
1 1 0
DL AND gate inverter
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DTL-NAND
• Input Diodes Da,Db,Dc conduct through resistor R, if the corresponding input
is in the LOW state, while the corresponding to HIGH state the is non
conducting.
• If at least one of the input is LOW, the diode connected to their input conducts
and the voltage at the output is one diode drop above the low level voltage at
the input. this voltage keep the transistor in cut-off. The output of transistor is
Vcc.
• If all the three i/ps are in High state ,the i/p diodes are cut-off and current
flowing from Vcc through R should be sufficient to drive transistor in
saturation. Therefore the o/p of transistor is Vce(sat).
• Voltage corresponds to logic 1 and logic 0 as Vcc and Vce(sat).
• Delays are associated with the turning on and off of the output transistor.
• While turning on, any capacitance shunting the output of the gate discharges
rapidly through the low impedance of the o/p transistor in saturation
• At turn off, the shunt capacitor must charge through the pull-up resistor Rc in
addition to the storage time delay. Turn off delay is larger than turn on delay by
a factor of 2 or 3.
• Propagation delay of DTL gates are 30 to 80ns.
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TTL (Transistor-Transistor Logic)
Disadvantages of RTL & DTL
RTL :
DTL :
1. Slow Speed
2. Improved noise margin & Fan out
TTL (Transistor-Transistor Logic)
• The original basic TTL gate was a slight improvement over the DTL gate.
• Introduced several TTL subfamilies or series
• First introduced by in 1964 (Texas Instruments)
• TTL has shaped digital technology in many ways
• Transistor alone performs the logical operation & Logic gate operations
• Transistors operated in saturated mode and cut off mode.
• Fastest of the saturated logic families
• Good speed
• Low manufacturing cost
• Wide range of circuits & applications
• Availability in SSI & MSI
• Relatively high power consumption
TTL (Transistor-Transistor Logic)
TTL subfamilies
• Standard TTL
• High speed TTL
• Low power TTL
• Schottky TTL
• Low power Schottky TTL
• Fast TTL
Three different types of output configurations
1. Open-collector output
2. Totem-pole output
3. Three-state (or tristate) output
Transistor Operation
Ic = β*Ib
NAND Gate
Open-collector TTL – NAND Gate
• Multiple emitter of Q1 connected to i/ps. Compare to DTL ,i/p diodes--
Q1, D1--B-C jn, D2—Q2.
• o/p is taken from open collector of Q3.
• Pull up resistor connected to Vcc, to pull up the o/p to high level when Q3
is off. Otherwise the o/p acts as an open circuit.
• 0.2v for low level,2.4 to 5v for high level.
• If any i/p is low , corresponding B-E jn of Q1 is F.B. the voltage at base of
Q1 is 0.9v(i/p 0.2+Vbe drop 0.7).
• In order for Q3 to start conducting the path from Q1-Q3 must overcome
the potential 1.8v (Diode drop in B-C jn drop+ two Vbe drop of Q2,Q3).
But at Q1 is 0.9v so Q3 is cut-off , o/p is high.
• If all i/ps are high Q2, Q3 conduct and saturate. B-E jns of Q1 are all R.B.
when Q3 saturates o/p goes low to 0.2v.
• Applications are driving a lamp or relay, performing wired logic and
construction of common bus system
Three-state TTL with Inverter operation
TTL family Evolution
LOGIC FAMILIES
Emitter-Coupled Logic (ECL)
• Non saturated digital logic family & Used in high speed circuits
• Including
– Emitter-follower outputs
ECL NOR / OR
2
Circuit Symbol MOSFET – N Channel
D
ID= IS
IS G-Gate
D-Drain
S S-Source
B-Substrate or Body
Configuration - CS
Common source: This MOSFET configuration is probably the most widely used. The
common source circuit provides a medium input and output impedance levels. Both
current and voltage gain can be described as medium, but the output is the inverse of the
input, i.e. 180° phase change. This provides a good overall performance and as such it is
often thought of as the most widely used configuration.
Configuration - CD
Common source: This MOSFET configuration is also known as the source follower.
The reason for this is that the source voltage follows that of the gate. Offering a high
input impedance and a low output impedance it is widely used as a buffer. The voltage
gain is unity, although current gain is high. The input and output signals are in phase.
Configuration - CG
Common source: This transistor configuration provides a low input impedance while
offering a high output impedance. Although the voltage is high, the current gain is low
and the overall power gain is also low when compared to the other MOSFET circuit
configurations available. The other salient feature of this configuration is that the input
and output are in phase.
MOSFET (Types)
• Four types:
– n-channel enhancement mode
– Most common since it is cheapest to manufacture
– p-channel enhancement mode
– n-channel depletion mode
– p-channel depletion mode
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
MOSFET - Uses
•Most important device in digital design
•Simple manufacturing
0
n+ n+
S D
p bulk Si
nMOS Operation Cont.
When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2
1
n+ n+
S D
p bulk Si
pMOS Transistor
Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2
p+ p+
n bulk Si
Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge, no
dc current exists.
Static States of the CMOS Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge,
no dc current exists.
Static Characteristics of the CMOS
Inverter
v 2.5 VTN ( 0.6) for NMOS
vI 2.5V (1 state) GS
vGS 0 VTP ( 0.6) for PMOS
M is "On"
N vO 0 VL (0state)
P
M is "Off"
• The capacitor discharges through RonN ,
current exists only during discharge,
no dc current exists.
A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF
A Y
GND
CMOS Logic Design
• The design of logic gates for CMOC inverter is different from the similar logic
design for NMOS inverters that we considered earlier.
• For NMOS gates, the logic involved only the switching transistor.
• For CMOS, both transistors are involved, since the input affects both in
symmetrical way.
• Thus, for each logic input variable in CMOS gate there is one transistor in NMOS
network and one transistor in PMOS network.
Load
transistor
Y
A
Reference Inverter
CMOS NAND gate
CMOS NAND Gates
Y
A
A=0 Y=1
Reference Inverter A=0 Y=1 B=0 Y=1
CMOS NAND gate
CMOS NAND Gates
Y
A
Reference Inverter
A=1 Y=0 A=1 & B=1 Y=0
CMOS NAND gate
CMOS NAND Gates
Y
A
A=0 Y=1
Reference Inverter A=0 Y=1 B=0 Y=1
A=1 Y=0 A=1 & B=1 Y=0
CMOS NAND gate
CMOS NAND Gates
Y
A
Reference Inverter
CMOS NAND gate
• The same rules apply for sizing the NAND gate devices as for the NOR gate,
except now the NMOS transistors are in series
• (W/L)P will be the same size of that of the reference inverter
CMOS NAND Gates
Y
A
Reference Inverter
CMOS NAND gate
• The same rules apply for sizing the NAND gate devices as for the NOR gate,
except now the NMOS transistors are in series
• (W/L)P will be the same size of that of the reference inverter
• (W/L)N will be twice the size of that of the reference inverter
Multi-Input CMOS NAND Gates
CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
1 0 1 0 ON
A OFF
1 1 0 0
1
1
0 OFF
ON
B ON
OFF
PROPAGATION DELAY, TRISTATE LOGIC
& IT’S APPLICATIONS
PROPAGATION DELAY
• Every logic gate experiences some delay (though very small) in
propagating signals forward, This delay is called Gate
(Propagation) Delay(tPD).
• Formally, it is the average transition time taken for the output
signal of the gate to change in response to changes in the input
signals.
• Three different propagation delay times associated with a logic
gate:
• tPHL: output changing from the High level to Low level
• tPLH: output changing from the Low level to High level
• tPD=(tPLH + tPHL)/2 (average propagation delay)
PROPAGATION DELAY
PROPAGATION DELAY
• Variations:
Data input, IN, can be inverted
EN is to make output Hi-Z or Control input, EN, can
be inverted by addition of "bubbles" to signals
Tristate (Three-State) Logic
Hi-Impedance Outputs
• Tristate gate utilize the high-speed operation
of the totem-pole arrangement when input
enabled
• Permit outputs to be connected together High Z-Output
• What is a Hi-Z value?
Both transistor are turned off in the totem- pole
arrangement
An equivalent circuit
This means that, looking back into the circuit, the (open circuit) for the
output appears to be disconnected tristate output in the
high-Z state
Tristate (Three-State) Logic
Applications:
* 1
FPGA structure
Simplified CLB Structure
HDL user defined primitives
HDL user defined primitives
HDL user defined primitives
HDL user defined primitives
HDL user defined primitives
Sequential Level Sensitive UDP’s
example
Stimulus to the design
VERIFYING OUTPUT