Syllabus: DIC

OVERVIEW OF HIGH-SPEED LOGIC FAMILIES(08 Hours)

BJT Inverter, DC Switching Characteristic, Introduction to TTL, Schottky TTL, and
ECL Logic Family, Concept of Noise margin, Fan Out and Propagation Delay,
NMOS, PMOS, CMOS, Bi- CMOS Circuits
MOSTRANSISTORS(08 Hours)
Fundamental of MOSFET operation and MOSFET capacitances, MOSFET I-V
Characteristics, MOSFET Model, Modeling of MOS Transistor using Spice, Scaling
and Small Geometry Effects, Fabrication Process Flow, CMOS N-Well Process and
Twin Tub Process
NMOS AND CMOS LOGIC DESIGN (12 Hours)
Various NMOS Inverters, Determination of VTC, Calculation of VTC Critical
Points, CMOS Inverter Technology, VTC, Static Characteristics, Dynamic Behavior,
Static and Dynamic Power Dissipation, Power-Delay Product, TTL-CMOS
Interfacing.

15-01-2024 DOECE, SVNIT 1

Syllabus: DIC
CMOS COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS
MOS Logic Circuits, Complex Logic Circuits, Pass transistor and Transmission gate,
Behavior of MOS Logic Elements. The Bistability Principle, SR Latch Circuit, Clocked
Latch and Flip-Flop Circuits, CMOS DLatch and Edge-Triggered Flip-Flop. Layout
Design Rules, Full-Custom Mask Layout Design and Stick Diagrams Antenna effect

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 Chapter 1

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Transistor (BJT) as a switch

• A circuit that can turn on/off current in

electrical circuit is referred to a switching
circuit and transistor can be employed as
an electronic switch.

• Cut off region - OFF State

Both junctions are reverse biased,
Ic = 0 and V(BE) < 0.7 V

• Saturation region - ON State

Ic = maximum and V(BE)>0.7 v

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MOSFET as Switch
Cut off (Switch OFF)
• The input and Gate are grounded ( 0V )
• Gate-source voltage less than threshold voltage
VGS < VTH
• MOSFET is “OFF” ( Cut-off region )
• No Drain current flows ( ID = 0 Amps )
• VOUT = VDS = VDD = “1”
• MOSFET operates as an “open switch”
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Saturation (Switch ON)
• The input and Gate are connected to VDD
• Gate-source voltage is much greater than
threshold voltage VGS > VTH
• MOSFET is “ON” ( saturation region )
• Max Drain current flows ( ID = VDD / RL )
• VDS = 0V (ideal saturation)
• Min channel resistance RDS(on) < 0.1Ω
• VOUT = VDS ≅ 0.2V due to RDS(on)
• MOSFET operates as a low resistance
“closed switch”
DOECE, SVNIT 5
Logic Families
Classification:

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Various parameters of ICs

Fan In: Fan in or gate is the number of inputs that can practically be supported
without degrading practically input voltage level.

Fan Out:
• The maximum number of digital inputs of the next stage that the output of a single
logic gate can feed and the gate must be the same logic family.
• In the given Fanout = 4
• Fan Out is calculated from the amount of current available in the output of
a gate and the amount of current needed in each input of the connecting
gate.
• It is specified by manufacturer and is provided in the data sheet.
• Exceeding the specified maximum load may cause a malfunction
• Because the circuit will not be able supply the demanded power.

15-01-2024 DOECE, SVNIT 7

Noise margin
• Noise margin is closely related to the DC voltage characteristics [Wakerly00].
• This parameter allows you to determine the allowable noise voltage on the input
of a gate so that the output will not be corrupted.
• The specification most commonly used to describe noise margin (or noise
immunity).
• NM have two parameters: the LOW noise margin, (NML) and the HIGH noise
margin (NMH ) NML is defined as the difference in maximum LOW input voltage
recognized by the receiving gate and the maximum LOW output voltage produced
by the driving gate.

NML = VIL - VOL

• The value of NMH is the difference between the minimum HIGH output voltage
of
the driving gate and the minimum HIGH input voltage recognized by the receiving
gate

NMH = VOH - VIH

15-01-2024 DOECE, SVNIT 8

VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
VOH= minimum HIGH output voltage
VOL = maximum LOW output voltage
NML = VIL – VOL

NMH = VOH - VIH

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Propagation Delay

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Digital circuits are often modelled as first-order RC networks of the type shown in
Figure

Propagation delay τ = RC
V= final voltage
Vin = initial voltage across the capacitor is assumed to be zero.

15-01-2024 DOECE, SVNIT 11

Power dissipation
• The power consumption of a design determines how much energy is consumed
per operation, and how much heat is dissipated by the circuit.
• These factors influence critically to design decisions, such as the
• Power-supply capacity,
• Battery lifetime,
• Supply-line
• Sizing, packaging and cooling requirements.

• Energy and power are closely related but are not the same physical quantity.
Energy is the ability to cause change; power is the rate energy is moved, or used.

• Power is defines as how fast energy is used or transmitted - power is the amount
of energy divided by the time it took to use the energy

15-01-2024 DOECE, SVNIT 12

 Power = Potential Energy (E)/ Time(t)
in electrical domain PE = qV
P = qV/t , q is charge, V is potential difference
P = VI : I is current

• Lifting a box requires a specific amount of energy, no matter how quickly the box
is picked up. Lifting faster will change the amount of power but not the amount
of energy.
• So in a electrical circuit we can have two types of power
• Power consumption (VI) : Charging/Discharging of capacitor
: Storage (Battery charging/Discharging)
• Power dissipation : Resistive losses (I2R)
: Static power dissipation
: Dynamic power dissipation

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Depending upon the design problem at hand, different dissipation measures have to
be considered. For instance, the peak power Ppeak is important when studying supply-line
sizing.

When addressing cooling or battery requirements, one is predominantly interested

in the average power dissipation Pav.

• p(t) is the instantaneous power

• isupply is the current being drawn from the supply voltage (Vsupply) over the interval t =
[0,T]
• ipeak is the maximum value of isupply over that interval.

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The dissipation can further be decomposed into:

1. Static: The static component is present even when no switching occurs and is caused
by static conductive paths between the supply rails and ground or by leakage
currents of the devices.
• It is always present, even when the circuit is in stand-by. Minimization of this
consumption source is a worthwhile goal.

2. Dynamic: It is attributed to the charging of capacitors and temporary current paths

between the supply rails and ground.
• Therefore, it is proportional to the switching frequency: the higher the
number of switching events, the higher the dynamic power consumption.
• The dynamic power consumption originates from the activity of logic gates
inside a CPU.
2
• 𝑷 𝒅𝒚𝒏 = 𝑪 ⋅ 𝑓. 𝑽

• The total power dissipation has not the only component where electrical energy has
been converted into thermal energy but the energy which goes into ground while
operation is the major one.
•

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Resistor Transistor Logic(RTL)
• The basic RTL device is a NOR gate.

• The inputs represent either logic level HIGH (1) or LOW (0).

• The logic level LOW is the voltage that drives corresponding transistor in cut-off
region, while logic level HIGH drives it into saturation region.

• If both the inputs are LOW, then both the transistors are in cut-off i.e. they are
turned-off. Thus, voltage Vcc appears at output I.e. HIGH.

• If either transistor or both of them are applied HIGH input, the voltage Vcc drops
across Rc and output is LOW.

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RTL Basic gate
Working or Logic Operation:

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Advantages of RTL Logic circuit:
it involved a minimum number of transistors, which was an important consideration
before integrated circuit technology, as transistors were the most expensive
component to produce.
•
Limitations:
• The obvious disadvantage of RTL is its high current dissipation when the
transistor conducts to overdrive the output biasing resistor.

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DCTL
• Direct-coupled transistor logic (DCTL) is similar to resistor–transistor logic (RTL)
but the input transistor bases are connected directly to the collector outputs
without any base resistors.
• Basic gate is NOR
• Logic 1 = 0.8V and Logic 0 = 0.2V (Vce sat)

Drawback:
• Logic swing is very small
• It never become popular because of Current hogging
• Therefore, the noise margin of this circuit is very poor.
• Current hogging: Current hogging is slang for a circuit with parallel branch
elements does not have the same current in each branch

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Current hogging
• This does not pose any problem if all the transistors have same input
characteristics but, unfortunately, the input characteristics differ due to the
manufacturing tolerances of different IC packages operating at different
temperatures.
• Owing to these differences, the saturation voltages of the load transistors may be
different.
• Let the base-emitter voltages of the transistors corresponding to saturation be
0.78, 0.79, and 0.80 V.
• The transistor with the base-emitter voltage of 0.78 V, when it enters saturation,
will not allow other transistors to enter into saturation and will take the whole of
the current supplied from the driver gate. This is known as current hogging.

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Diode Transistor Logic

• The diode-transistor logic, also termed as DTL, replaced RTL family because of
greater fan-out capability and more noise margin.
• DTL circuits mainly consists of diodes and transistors that comprises DTL devices.
• The basic DTL device is a NAND gate.
Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will
conduct only when corresponding input is LOW.
• If any of the diode is conducting i.e. when at least one input is LOW, the voltage
at output keeps transistor T in cut-off and subsequently, output of transistor is
HIGH.
•

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DIODE-TRANSISTOR LOGIC (DTL)
• If all inputs are HIGH, all diodes are non-conducting, transistor T is in saturation,
and its output is LOW.
• The diode-transistor logic is somewhat more complex than RTL but because of its
greater fan-out and improved noise margins it has replaced RTL.

• Its main disadvantage is slower speed and because of this it was modified and
emerged as transistor-transistor logic (TTL) which is the most popular logic family,
as far as small- and medium-scale ICs are concerned

• Although TTL has completely replaced DTL, for historical reasons as well as for
better appreciation of TTL circuit, it is worthwhile discussing the details of DTL.

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• If any of input is low then transistor should be in cut-off then V0 = logic1
• In this situation Vp will be at 0.7 V and therefore D4 and D5 is connected between
point p and transistor , otherwise T will turn ON at the same time practically.
• If all the input are high, all diodes will be OFF, then T will be in saturation and V=
Vce sat.

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Propagation Delays: The turn-off delay is considerably larger than the turn-on delay,
often by a factor of 2 or 3. The propagation delay time of commercially available DTL
gates are of the order of 30 to 80 ns.

Reason: delays are associated with the turning-on (turn-on delay) and the turning-off
(turn-off delay) of the output transistor. While turning on, any capacitance shunting
the output of the gate discharges rapidly through the low impedance of the output
transistor in saturation. On the other hand, at turn-off the shunt capacitor must
charge through the pull-up resistor R in addition to the storage time delay.

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Current sink and sourcing

Source current is the ability of the digital output/input port to supply current

Sink current is the ability of the port to receive current.

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Wired AND logic
If the outputs of gates are connected together as shown in Figure, additional logic is
performed without additional hardware. This type of connection is referred to as
wired-logic, wired- AND, or implied-AND.

Wired AND connection of DTL gate

If Y1 and Y2 =1 then Y=1, otherwise Y =0 for any combination

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Effect of wired AND over power dissipation, speed
and fanout
• Power dissipation :The power dissipation in LOW output state P(0) increases
because of reduction in effective collector resistor (Rc || Rc = Rc/2).

• Speed: Consequently, the speed of operation increases due to reduction in

charging resistor (Rc/2).

• Fanout: There is an effective reduction in the fan-out of the gate in the wired-
AND connection.
• If only one output transistor (say T') is conducting, then this transistor is not only
sinking the current coming from the load gates and its own pull-up resistor but
also sinking the current in the pull-up resistor of the other output transistor T".
• This situation makes it necessary to reduce the allowable fan-out of each gate in
the wired-AND connection.

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Modified Integrated DTL NAND Gate
The fan-out of DTL may be increased by increasing the base current of the output
transistor. This can be done by replacing D4, by a transistor T1

15-01-2024 DOECE, SVNIT 28

HIGH-THRESHOLD LOGIC (HTL)
• Due to the presence of electric motors, on-off control circuits, high voltage
switches, etc. in an industrial environment, the noise level is quite high and the
logic families discussed so far do not perform the intended functions.

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HIGH-THRESHOLD LOGIC (HTL)
• For this purpose, the DTL gate of Figure has been redesigned with a higher supply
voltage (15 V instead of 5 V).
• The diode D, has been replaced by a Zener diode with a Zener breakdown voltage
of 6.9 V
• And the resistances have been modified so that approximately the same currents
are obtained as in DTL.
• The circuit can be analysed to determine the noise-margins, fan-out and power
dissipation
• The propagation delay time is adversely affected due to large resistance values. It
is as high as hundreds of nano-seconds.
• The temperature sensitivity of the HTL gate is considerably less than that of DTL

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TRANSISTOR-TRANSISTOR LOGIC (TTL)
• The transistor-transistor logic (TTL) is the most successful bipolar logic which was
evolved in the 1960s and has survived for more than four decades.
• TTL families use transistors, both to perform logic functions and to provide high
output drive capability
• The NAND gate is the basic TTL logic circuit.
• Standard TTL circuits operate with a 5-volt power supply. A TTL input signal is
defined as "low" when between 0 V and 0.8 V with respect to the ground terminal,
and "high" when between 2 V and VCC (5 V)
• TTL outputs are typically restricted to narrower limits of between 0.0 V and 0.4 V
for a "low" and between 2.4 V and VCC for a "high", providing at least 0.4 V of noise
immunity.

A simple TTL logic gate

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TTL
It uses a multiple-emitter transistor T1. The number of inputs (fan-in) to the gate is
same as the number of emitters fabricated during its manufacturing.
Operation of TTL NAND GATE
The following voltages are assumed for p-n junction (diode operation) and transistors.
p-n junction:
Voltage across a conducting diode = 0.7 V
Cut-in voltage V = 0.6 V
Transistor:
Cut-in voltage Vbi = 0.5 V
VBE sat = 0.8 V
VCE,sat = 0.2 V
Condition I: At least one input is LOW,
Any of pn junction will be ON,
Voltage at B1 will be 0.2+0.7=0.9V
For base-collector junction of T1 to be forward-biased, and for T2, and T3, to be
conducting, voltage is required to be at least 0.6+0.5 +0.5= 1.6 V. Hence, T2, and T3,
are OFF.

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TTL
Since T, is OFF, therefore Y = V (1) = Vcc
Condition II: All inputs are HIGH.
• The emitter-base junctions of T1, are reverse-biased and T1 is in Reverse active
mode. If we assume that T2, and T3, are ON, then
• VB2 = VC1 =0.8+0.8 = 1.6 V. Since B1, is connected to Vcc (5V) through R1, the
collector-base junction of T1, is forward-biased.
• The transistor T 1 is operating in the active inverse mode, making IC1 flow in the
reverse direction.
• This current flows into the base of T2 driving T2 and T3, into saturation. Therefore,
Y= V(0) ≈ 0.2 V.

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TTL
• Condition III: Let the circuit be operating under condition II when one of the
inputs suddenly goes to V(0).
• The corresponding emitter-base junction of T1, starts conducting and VB1 drops
to 0.9 V.
• Therefore, T2, and T3, will be turned off when the stored base charge is removed.
• Since previously VC1= VB2 = 1.6 V, therefore the collector-base junction of T1 is
back-biased, making T1, operate in the normal active region.
• This large collector current of T1 is in a direction which helps in the removal of
stored base charge from T2, and T3, and improves the speed of circuit.
• The direction of the collector current is same as the current IC1,

• Propagation Delay: The speed of the circuit can be improved by decreasing

• RC3 which decreases the time constant (RC3 - C0) with which the output
capacitance charges from 0 to 1 logic level.
• This reduction in time constant, however, would increase dissipation
across the load capacitor and would make it more difficult for T3 to enter
into saturation.

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Power dissipation:
• The currents drawn from the VCC supply will be different for the two conditions,
i.e., when the output is in the LOW state and when the output is in the HIGH
state.
• The power consumption in the LOW output state P(0) will be due to IB1
• Whereas the power consumption when the output is in the HIGH state P(1) will
be due to the currents flowing through RC2, RC3, and the leakage currents of
load devices
• Average power consumption is {P(0) + P(1)} /2
• TTL Fanout :
• When outpot is low: The fan-out(N) of a gate depends upon the maximum
collector current rating of the transistor T3. The total collector current is
IC3(sat) + N*IL
• When outpot is High: It will depend on the power supply and the
resistance RC3.

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Open Collector output:
• This can be one of the ways to take the output from TTL where RC3 is missing and
the collector terminal is floating. In this configuration, the RC3 can be connected
from outside.
• This allows the designer to fabricate wired logic by connecting the open-collector
outputs of several logic gates together and providing a single external pull-up
resistor.
• If any of the logic gates becomes logic low (transistor conducting), the combined
output will be low.
• 7401 and 7403 series are the example of this type of gates.
• Open-collector outputs of some gates have a higher maximum voltage, such as 15
V for the 7426, useful when driving non-TTL loads.

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Active Pull-up
• In the previous circuit of TTL we have seen that load capacitor is charging with
very high RC3 and if the RC3 is high then it will take longer time to charge or
switch the logic fro 0 to 1.
• This is called passive pullup.
• In the passive pullup the charging and discharging time may vary wastely because
of discharging occurs through transistor T3 and charging occurs through
resistance .
• But in the active pullup TTL, the resistance RC3 will be replaced by another
transistor and separated by one diode as shown in the figure. Thus is called an
active pull-up or totem-pole output.

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The operation of the circuit can qualitatively be described as:
1. For output Y to be in 0, transistor T4 and diode D are cut-off.
2. When the output makes a transition from LOW to HIGH corresponding to any
input going to LOW, transistor T4 enters saturation and supplies current for the
charging of the output capacitor with a small time constant.

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• This current decreases and eventually becomes zero under steady-state
condition when Y = V(1).
• Transistor T3 and T4 should be in the combination of ON and OFF, both should
not be in the same state at an instant of time.
• That’s why diode is used in between T3 and T4
• Diode D is used in the circuit to keep T4 in cut-off when the output is at logic 0.
Corresponding to this, T2 and T3 are in saturation.

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Open Collector output
• This can be one of the way taking the output from TTL where RC3 is missing and
collector terminal is floating. In this configuration the RC3 can be connected from
out side.
• This allows the designer to fabricate wired logic by connecting the open-collector
outputs of several logic gates together and providing a single external pull-up
resistor.
• If any of the logic gates becomes logic low (transistor conducting), the combined
output will be low.
• 7401 and 7403 series are the example of this type of gates.
• Open-collector outputs of some gates have a higher maximum voltage, such as 15
V for the 7426, useful when driving non-TTL loads.

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Unconnected Inputs and Clamping Diodes :
Unconnected Inputs : This discussion is at the input section means at T1.
• If any input of a TTL gate is left disconnected (open or T1 floating) the
corresponding E-B junction of T 1 will not be forward-biased.
• Hence, it acts exactly in the same way as if a logic 1 is applied to that input.

Clamping Diodes: TTL Gate showing the Clamping diodes are commonly used in all
TTL gates to suppress the ringing caused from the fast voltage transitions found in
TTL. These diodes shown in Figure clamp the negative undershoot at approximately
-0.7V.

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Comparison with other logic families
• TTL is less sensitive to damage from electrostatic discharge than early CMOS
devices.
• TTL has more power dissipation than equivalent CMOS devices at rest, but power
consumption does not increase with clock speed as rapidly as for CMOS devices.
• Due to the output structure of TTL devices, the output impedance is asymmetrical
between the high and low state, making them unsuitable for driving transmission
lines.
• ECL, by virtue of its symmetric low-impedance output structure, does not have this
drawback.
• The TTL "totem-pole" output structure often has a momentary (short) overlap
when both the upper and lower transistors are conducting. Which results a
substantial pulse of current drawn from the power supply.

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Various type of TTL logic families
• Successive generations of technology produced compatible parts with improved
power consumption or switching speed, or both.

• Standard TTL: Already studied

• Low Power TTL: Low-power TTL (L), which traded switching speed (33ns) for a
reduction in power consumption (1 mW) (now essentially replaced by CMOS logic)

• High Power TTL: with faster switching than standard TTL (6ns) but significantly
higher power dissipation (22 mW)

• Schottky TTL: introduced in 1969, which used Schottky diode clamps at gate inputs
to prevent charge storage and improve switching time. These gates operated more
quickly (3ns) but had higher power dissipation (19 mW)

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SCHOTTKY TTL
• Schottky Transistor: A Schottky transistor is a combination of a transistor and
a Schottky diode that prevents the transistor from saturating by diverting the
excessive input current.
• Standard transistor-transistor logic (TTL) uses transistors as saturated switches.
• A saturated transistor is turned on hard, which means it has a lot more base drive
than it needs for the collector current it is drawing.
• The extra base drive creates a stored charge in the base of the transistor. The
stored charge causes problems when the transistor needs to be switched from on
to off: while the charge is present, the transistor is on; all the charge must be
removed before the transistor will turn off. Removing the charge takes time
(called Reverse recovery time).
• So the result of saturation is a delay between the applied turn-off input at the
base and the voltage swing at the collector. Storage time accounts for a significant
portion of the propagation delay in the original TTL logic family.
• With this, the transistors are prevented from entering saturation and hence,
there is saving in turn-off time.

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Schottky transistor
• A Schottky transistor places a Schottky diode between the base and collector of
the transistor. As the transistor comes close to saturating, the Schottky diode
conducts and shunts any excess base drive to the collector.
• The resulting transistors, which do not saturate, are Schottky transistors. The
Schottky TTL logic families (such as S and LS) use Schottky transistors in critical
places.

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• The speed limitation of TTL is mainly due to the tum-off time from saturation to
cut-off of the trannsistor T1 or input transistor. It means making the transistor
OFF is a critical factor for time delay.
• This will involve the storage time and reverse recovery concept of the junction.
• This can be eliminated by replacing the transistors of TTL gate by Schottky
transistors.

• Schottky TTL gates have propagation delay time of the order of 2 ns which is very
small in comparison with
• The propagation delay time of standard TTL which is of the order of 10 ns. It is a
nonsaturating bipolar logic.

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EMITTER-COUPLED LOGIC (ECL)
• Emitter-coupled logic (ECL) is the fastest of all logic families and therefore is used
in applications where very high speed is essential.
• High speeds have become possible in ECL because the transistors are used
in difference amplifier configuration, in which they are never driven into
saturation and thereby the storage time is eliminated.
• Here, rather than switching the transistors from ON to OFF and vice-versa, they
are switched between cut-off and active regions. Propagation delays of less than
1ns per gate have become possible in ECL.
• Basically, ECL is realised using difference amplifier in which the emitters of the
two transistors are connected and hence it is referred to as emitter-coupled logic.

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• A 3-input ECL gate is shown in Figure: which has three parts:
• The middle part is the difference amplifier which performs the logic operation.
• Emitter followers are used for d.c. level shifting of the outputs, so that V(0) and
V(1) are same for the inputs and the outputs.

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• Note that two output Y1 and Y2, are available in this circuit which are
complementary. Y1 corresponds to OR logic and Y2 to NOR logic and hence it is
named as an OR / NOR gate
• Additional transistors are used in parallel to T1 to get the required fan-in.
• In ECL, the positive end of the supply is connected to ground in contrast to other
logic families in which negative end of the supply is grounded.
• This is done to minimise the effect of noise induced in the power supply and
protection of the gate from an accidental short circuit developing between the
output of a gate and ground.
• The V0 and VI both are negative as positive terminal of the battery is connected
to the ground.

Symbol ECL

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 Chapter 2

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MOSFET Structure 3D and 2D
• metal-oxide-semiconductor FET is derived from its physical structure.
• But most modern MOSFETs are fabricated using a process known as silicon-gate
technology.
• Another name for the MOSFET is the insulated-gate FET or IGFET.
• MOSFET is a three-terminal device, with the terminals being the gate (G), the
source (S), and the drain (D) when the substrate is grounded and have no effect
on MOSFET operation.

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• A thin layer of silicon dioxide (SiO2) of thickness tox
(typically 1 nm to 10 nm)
• SiO2 is an excellent electrical insulator, is grown on the surface of the substrate,
covering the area between the source and drain regions.
• Metal (Al) or poly silicon materials are used to form contacts such as gate, drain
source and body.
• Typically L = 0.03 μm to 1 μm, W = 0.05 μm to 100 μm, and the thickness of the
oxide layer (tox) is in the range of 1 to 10 nm.

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Symbol
sa

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Type of MOSFETs

Type Channel Substra Channel

te formation

N P Induction • Most widely used

• overdrive voltage is key voltage
• Down scaling is quite easy
P N
Enhancement

N P Implanted • It is a special type of device.

• When Vgs <0 operated in
depletion mode.
• When Vgs >0 operated in
P N enhancement mode.
Depletion • It is characterized by the same
equations

15-01-2024 DOECE, SVNIT 54

Operation of N channel MOSFET
Operation with Zero Gate Voltage
• With zero voltage applied to the gate, two back-to-back diodes exist in series
between drain and source.
• These back-to-back diodes prevent current conduction from drain to source when a
voltage vDS is applied. In fact, the path between drain and source has a very
high resistance (of the order of 1012 Ω)

15-01-2024 DOECE, SVNIT 55

Creating a Channel for Current Flow

Consider next the situation when source and the drain are grounded and applied a positive
voltage to the gate.
As we increase applied gate voltage, depletion takes place (holes are pushed downward
into the substrate, leaving behind a carrier-depletion region)
Inversion: positive gate voltage attracts electrons from the n+ source and drain regins
(where they are in abundance) into the channel region.
When a sufficient number of electrons
accumulate near the surface of the substrate under the gate, an n region is in effect created
connecting the source and drain regions, as indicated in the figure.

15-01-2024 DOECE, SVNIT 56

• The channel is created by inverting the substrate surface from p
type to n type. Hence the induced channel is also called an inversion layer.
• The value of vGS at which a sufficient number of mobile electrons accumulate in
the channel region to form a conducting channel is called the threshold voltage.
• The gate and the channel region of the MOSFET form a parallel-plate capacitor,
with the oxide layer acting as the capacitor dielectric
• Detailed physics is already discussed in previous subject.
• he excess of vGS over Vt is termed the effective voltage or the overdrive voltage
and is the quantity that determines the charge in the channel.
• VGS -Vt ≡ VOV

15-01-2024 DOECE, SVNIT 57

Apply small VDS with Gate voltage
Having induced a channel, we now apply a positive voltage vDS between
drain and source.
We first consider the case where vDS is small (i.e., 50 mV or so). The voltage vDS
causes a current iD to flow through the induced n channel. Current is carried by free
electrons traveling from source to drain.

Thus, for small vDS, the channel behaves as a linear resistance whose value is
controlled by the overdrive voltage vOV, which in turn is determined by vGS.

15-01-2024 DOECE, SVNIT 58

three factors: (μnCox), (W/L), and VOV (or equivalently, vGS - Vt).
The first factor, (μnCox), is determined by the process technology used to fabricate the
MOSFET.
The dimension of Kn’ is A/V2

The second factor in the expression for the conductance gDS. is the transistor aspect
ratio (W/L).
That the channel conductance is proportional to the channel width W and inversely
proportional to the channel length L should make perfect physical sense.
The (W/L) ratio is obviously a dimensionless quantity that is determined by the device
designer.

15-01-2024 DOECE, SVNIT 59

The operation of the MOSFET as a voltage-controlled resistance
Observe that the resistance is infinite for VGS ≤ Vt and decreases as VGS is increased
above Vt

The ID–vDS characteristics of the MOSFET in Fig. 5.3 when the voltage applied between
drain and source, vDS, is kept small. The device operates as a linear resistance whose
value is controlled by vGS.

15-01-2024 DOECE, SVNIT 60

Operation as VDS Is Increased
• For this purpose, let VGS be held constant at a value greater than Vt;
• that is, let the MOSFET be operated at a constant overdrive voltage VOV .
• VDS appears as a voltage drop across the length of the channel.
That is, as we travel along the channel from source to drain, the voltage (measured
relative to the source) increases from zero to VDS
• Thus the voltage between the gate and points along the channel decreases from
source to drain.
• Therefore, channel is no longer of uniform depth; rather, the channel will take the
tapered shape

Since the gate voltage is fixed at some value higher than Vth So Vgd (the voltage at
the drain end) decreases and when Vg =Vd then Vgd = 0.
Which means there will no longer be a channel exist.

15-01-2024 DOECE, SVNIT 61

Operation as VDS Is Increased
As VDS is increased, the channel becomes more tapered and its resistance
Increases correspondingly. Thus, the iD-vDS curve does not continue as a straight line
but bends as shown in the figure.
By putting the values of different voltages in the previous equation of Ids we will have
new equation of ID.

This relationship describes the semi parabolic portion of the iD-vDS curve

15-01-2024 DOECE, SVNIT 62

Operation for VDS ≥ VOV: Channel Pinch-Off and Current Saturation

In the previous case we have assumed that channel became tapered, and it still had a
finite (nonzero) depth at the drain end.
If further Vds increases to Vov then Vgd = Vth and channel will be pinched off at the
drain side.

15-01-2024 DOECE, SVNIT 63

Increasing VDS beyond this value (i.e., VDS >VOV) has no effect on the channel shape and
charge, and the current through the channel remains constant at the value reached for
VDS =VOV.
The drain current thus saturates at the value found by substituting VDS =VOV

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ID -VG and ID -VD Characteristic of NMOSFET

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Depletion type MOSFET characteristics
Symbols

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Depletion type N channel MOSFET

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Depletion type P channel MOSFET Characteristics

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 Short channel effects:
DIBL
❑ DIBL: In case of short channel
devices source and drain fields
penetrate deeply into the middle of
the channel, which lowers the
potential barrier between the source
and drain. Therefore at high drain
voltage a very high drain current
flows without counting the gate
voltage.

❑ Thus, gate loses the control over the

channel and drain voltage finds the
Curve A is for long channel MOSFET, curve B is for short control over the drain current.
channel MOSFET at lower drain biasing and curve C is for
short channel MOSFET at higher drain biasing .
❑ Causes variation in threshold voltage.

1/15/2024 69
 Contd Hot carrier effect

Hot carrier effect damaging gate oxide

❑ Constant voltage scaling produces higher vertical and horizontal field with in
device and electrons get larger kinetic energy in the channel.
❑ These hot carriers cross the potential barrier of surface and surmounted into
oxide near drain junction.
❑ These hot electrons produce additional charges to the interface traps.

1/15/2024 70
 Contd.. Channel length modulation
❑ Variation in depletion width (ΔL) is the difference in
channel length when
𝑉𝐷𝑆 = 𝑉𝐷𝑆 𝑠𝑎𝑡 𝑎𝑛𝑑 𝑉𝐷𝑆 > 𝑉𝐷𝑆 (𝑠𝑎𝑡)
2𝜀𝑠
∆𝐿 = Φ𝑓 + 𝑉𝐷𝑆 (𝑠𝑎𝑡) + ∆𝑉𝐷𝑆 − Φ𝑓 + 𝑉𝐷𝑆 (𝑠𝑎𝑡)
𝑞𝑁𝑎

❑ We know that IDS is inversely proportional to channel

length so we can approximate:
L 1
IDS IDS IDS IDS ΔL
= L−ΔL = 1−
𝐿
Cross sectional view of N-
MOSFET depicting channel length
modulation.
∆𝐿 ≈ 𝑉𝐷𝑆 − 𝑉𝐷𝑆 (𝑠𝑎𝑡)
λ is an empirical model parameter, and is called the
channel length modulation coefficient. Assuming that λ VDS
❑ The depletion width can be
<< 1, and we can write IDS
approximated in reverse K n W
bias condition at drain IDS = [(VGS - Vth)2(1+λVDS)]
2 L
substrate junction by the
equation: ❑ So, the output resistance is no more infinite, drain current
is affected by channel length modulation parameter (λ) as
2𝑠𝑖 (ɸfp + VDS) shown in the above equation.
𝑥 =
1/15/2024 𝑞𝑁𝑎 71
 Contd. Threshold roll-off
❑ Variation in the depletion region charge density at surface inversion in the
trapezoidal channel causes variation in the threshold voltage depicted by the
equation:
∆𝐿𝑆 + ∆𝐿𝐷
❑ 𝑄𝐵𝑜 = − 1 − 2 𝑞 𝜀𝑠𝑖 𝑁𝑎 2Φ𝑓
2𝐿

1 𝑋𝑗 2𝑋𝑑𝑆 2𝑋𝑑𝐷
❑ ∆𝑉𝑡ℎ = 2 𝑞 𝜀𝑠𝑖 𝑁𝑒𝑞 2Φ𝑓 1+ −1 + 1+ −1
𝐶𝑜𝑥 2𝐿 𝑋𝑗 𝑋𝑗

Cross sectional view of N-MOSFET

𝑋
❑ According to the equation, ΔVth depends over 𝐿𝑗 .
❑ In long channel devices Xj <<< L.
❑ In short channel devices Xj and L are comparable.
1/15/2024 72
MOSFET Capacitances
• In order to examine the transient (AC) response of MOSFETs and digital circuits
consisting of MOSFETs, on the other hand, we have to determine the nature and
the amount of parasitic capacitances associated with the MOS transistor
• The on-chip capacitances found in MOS circuits are in general complicated
functions of the layout geometries and the manufacturing processes. Most of
these capacitances are not lumped, but distributed, and their exact calculations
would usually require complex, three-dimensional nonlinear charge-voltage
models.
• But, we will develop simple approximations for the on-chip MOSFET capacitances
that can be used in most hand calculations. These capacitance models are
sufficiently accurate to represent the crucial characteristics of MOSFET.
• Classification of MOSFET capacitances:
• Oxide related capacitances:
• Junction Capacitances

1/15/2024 73
 OXIDE CAPACITANCE: Figure shows the cross-sectional view and the top view
(mask view) of a typical n-channel MOSFET. In this figure, the mask length
(drawn length) of the gate is indicated by LM, and the actual channel length is
indicated by L. The extent of both the gate-source and the gate-drain overlap are LD;
thus, the channel length is given by
L=LM -2 LD

1/15/2024 74
 Schematic representation of MOSFET oxide capacitances during (a) cut-off, (b)
linear, and (c)saturation modes.

1/15/2024 75
 Approximate oxide capacitance values for three operating modes of the MOS Transistor:

Variation of the distributed (gate-to-channel) oxide capacitances as functions of

gate-to-source voltage VGS
1/15/2024 76
Junction Capacitance

1/15/2024 77
 Derivation:

1/15/2024 78
1/15/2024 79
 Lumped representation of capacitances

1/15/2024 80
CMOS N well Process Flow
CMOS N Well Processes Flow:
1.

2. Oxidation
Grow SiO2 on top of Si wafer
• 900℃ - 1200℃ with H2O or O2 in an oxidation furnace

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3. Photoresist
Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

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4. Lithography
Expose photoresist through n-well mask Strip off exposed photoresist

5. Etch
Etch oxide with hydrofluoric acid (HF)
Only attacks oxide where resist has been exposed

15-01-2024 DOECE, SVNIT 83

6. Strip Photoresist Strip off remaining photoresist
– Old days we used a mixture of nitric and sulphuric acids called piranha etch
– Now we use a plasma etch which is much safer (and greener).
Necessary so resist doesn’t melt in the next step

7. n-Well
• n-Well formed with diffusion or ion implant Diffusion
• Place wafer in furnace with Arsine (AsH3) gas
• Heat until As atoms diffuse into exposed Si

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8. Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter to exposed Si

9. Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent
steps involve similar series of steps

15-01-2024 DOECE, SVNIT 85

10. Polysilicon
-Grow/deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of Si layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

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11. Polysilicon Cont…
Patterning
Use same lithography process to pattern polysilicon

15-01-2024 DOECE, SVNIT 87

12. Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be
diffused or implanted
N-diffusion forms NMOS source, drain, and n-well contact

15-01-2024 DOECE, SVNIT 88

13. N-diffusion
Pattern oxide and form n+ regions
Self-aligned process - gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it doesn’t melt during
later processing

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14. Etch off oxide to complete patterning step

15. P-Diffusion
- Similar set of steps form p+ diffusion regions for PMOS source and drain and
substrate contact

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Contacts….
- Now we need to wire together the devices Cover chip with thick field oxide
- Etch oxide where contact cuts are needed

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16. Metallization
Sputter on Aluminium over whole wafer
Pattern to remove excess metal, leaving wires

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Two layout views of CMOS

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Layout design Rule:
Motivation:
In VLSI design, as processes become more and more complex, need for the designer
to understand the intricacies of the fabrication process and interpret the relations
between the different photo masks. Therefore, a set of layout rules, also called
design rules, has been defined. They act as an interface or communication link
between the circuit designer and the process engineer during the manufacturing
phase

Objective:
The objective associated with layout rules is to obtain a circuit with optimum yield
(functional circuits versus non-functional circuits) in as small as area possible
without compromising reliability of the circuit. Generally, they are a compromise
between yield and performance without compromising reliability of the circuit.
So the need of design rules arises due to manufacturing problems like
• Photo resist shrinkage, tearing.
• Variations in material deposition, temperature and oxide thickness.
• Impurities.
• Variations across a wafer.

15-01-2024 DOECE, SVNIT 94

Layout design rules describe how small features can be engraved and how closely
they can be put together without sacrificing reliably in a particular manufacturing
process,

The design rules primary address two issues:

1. The geometrical reproduction of features that can be reproduced by the mask
making and lithographical process, and
2. The interaction between different layers.

15-01-2024 DOECE, SVNIT 95

Types of Design Rules
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules)

2. Absolute Design Rules (e.g. μ-based design rules ) : Micron rules, in which the
layout constraints such as minimum feature sizes and
minimum allowable feature separations are stated in terms of absolute
dimensions in micrometers,

1. Scalable Design Rules (e.g. SCMOS, λ-based design rules)

Mead and Conway [Mead80] popularized scalable design rules based on a single
parameter, λ that characterizes the resolution of the process.
λ is generally half of the minimum drawn transistor channel length (feature size).
This length (feature size) is the distance between the source and drain of a transistor
and is set by the minimum width of a polysilicon wire.

15-01-2024 DOECE, SVNIT 96

Drawback:
• Lambda-based rules are necessarily conservative because they round up
dimensions to an integer multiple of λ
• Most of the submicron CMOS process design rules do not lend themselves to
straightforward linear scaling. The use of λ-based design rules must therefore be
handled with caution in sub-micron geometries
Advantage:
• However, they make scaling layout trivial
• The same layout can be moved to a new process simply by specifying a new value
of λ

The MOSIS (MOS Implementation System) service is a low-cost prototyping service

has developed a set of scalable lambda-based design rules that covers a wide range
of manufacturing processes. The rules describe the minimum width to avoid breaks
in a line, minimum spacing to avoid shorts between lines, and minimum overlap to
ensure that two layers completely overlap.

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 Chapter 4

15-01-2024 DOECE, SVNIT 98

Sequential Circuits
• sequential circuit consisting of a combinational circuit and a memory block in the
feedback loop. In most cases, the regenerative behavior of sequential circuits is
due to either a direct or indirect feedback connection between the output and the
input.
• Regenerative operation can, under certain conditions, also be interpreted as a
simple memory function. The critical components of sequential systems are the
basic regenerative circuits, which can be classified into three main groups: bistable
circuits, monostable circuits, and astable circuits.

15-01-2024 DOECE, SVNIT 99

• Bistable circuits have, as their name implies, two stable states or operation modes,
each of which can be attained under certain input and output conditions.
• Monostable circuits, on the other hand, have only one stable operating point
(state). Even if the circuit experiences an external perturbation, the output
eventually returns to the single stable state after a certain time period.
• Astable circuits, there is no stable operating point or state which the circuit can
preserve for a certain time period. Consequently, the output of an astable circuit
must oscillate without settling into a stable operating mode.

• Example: The ring oscillator circuit is a typical example of an Astable regenerative

circuit.
• Example: The bistable circuits are most widely used and the most important class.
All basic latch and flip-flop circuits, registers, and memory elements used in digital
systems fall into this category.

15-01-2024 DOECE, SVNIT 100

Behaviour of the Bistable Circuit

• The basic bistable element examined here is consists of two identical cross coupled
inverter circuits, as shown in Figure below:
•

• Here, the output voltage of inverter [1] is equal

to the input voltage of inverter [2], i.e., Vo1 = Vi2,
and the output voltage of inverter [2]is equal to
the input voltage of inverter [1], i.e., V02 = Vi1.
• In order to investigate the static input-output
behavior of both inverters, we start by plotting the
voltage transfer characteristic of inverters.

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• We know that out put of one inverter is treated input for the second inverter
Therefore we can also plot the voltage transfer characteristic of both inverters
using the same axis pair.
• It can be seen in the previous figure that the two voltage transfer characteristics
intersect at three points and two of these operating points are stable, as indicated
in the same Figure.
• If the circuit is initially operating at one of these two stable points, it will preserve
this state unless it is forced externally to change its operating point .
• Note that the gain of each inverter circuit, i.e., the slope of the respective voltage
transfer curves, is smaller than unity at the two stable operating points.
• Thus, in order to change the state by moving the operating point from one stable
point to the other, a sufficiently large external voltage perturbation must be
applied so that the voltage gain of the inverter loop becomes larger than unity.

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• On the other hand, the voltage gains of both inverters are larger than unity at the third
operating point. Therefore, even if the circuit is biased at this point initially, a small
voltage perturbation at the input of any of the inverters will be amplified, causing the
operating point to move to one of the stable operating points.
• This leads to the conclusion that the third operating point is unstable. The circuit has
two stable operating points, hence, it is called bistable.

• Circuit diagram of a CMOS bistable element.

• Second diagram shows the possibility for the expected time-domain behavior of the
output voltages, if the circuit is initially set at its unstable operating point.

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 Flip Flop
flip-flop is an edge-triggered type of
memory circuit
A flip-flop state repeatedly changes at an
active state of the clock pulses. They
remain unaffected even when the clock
pulse does not stay active. The clocked
flip-flops particularly act as the memory
elements of the synchronous sequential
circuit- while the un-clocked ones
(latches) function as the memory
elements of asynchronous sequential
circuits.
JK Flip-Flop
SR (Set-Reset) Flip-Flop
Data or Delay (D) Flip-Flop
Toggle (T) Flip-Flop
The clock
15-01-2024 signal is present.
DOECE,
Latch
latch is a level-triggered type.
A latch is an electronic device that
changes its output immediately on the
basis of the applied input. One can use it
to store either 0 or 1 at a specified time. A
latch contains two inputs- SET and RESET,
and it also has two outputs. They
complement each other. One can use a
latch for storing one bit of data. It is a
memory device- just like the flip-flop. But
it is not synchronous, and it does not
work on the edges of the clock like the
flip-flop.
The
clock
SVNIT signal is absent. 104
 Flip Flop Latch
You can design it using Latches along with a You can design it using Logic gates.
clock.
Flip-flop is sensitive to the applied input and Latches are sensitive to the applied input
the clock signal. signal- only when enabled.

It has a slow operating speed. It has comparatively fast operating speed.

You can classify a flip-flop into a
synchronous or asynchronous flip-flop.
Flip-Flops work using the binary input and
the clock signal.
Flip-flop performs Synchronous operations.
Flip-flops are comparatively more robust.
They constitute the building blocks of many
sequential circuits such as counters.
15-01-2024 DOECE, SVNIT
A user cannot classify the Latch this way.
Latches operate only using binary inputs.
Latch performs Asynchronous operations.
Latches are comparatively less robust.
Users can utilize these for designing
sequential circuits. But they are still not
generally preferred.
105
SR Latch
SR NOR Latch and truth table

SR Latch Based on two input

NOR gate implemented using
CMOS Logic

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SR Latch design by NAND2 gate

SR latch design using NANA gate

and Truth Table

SR Latch Based on two input

NAND gate implemented using
CMOS Logic

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Clocked Latch and Flip-Flop Circuits
• All of the SR latch circuits examined in the previous section are essentially
asynchronous sequential circuits, in which the output will respond to the
corresponding change in the input including the delays (via feed back path and
signal delay).
• To facilitate synchronous operation, the circuit response can be controlled simply
by adding a gating clock signal to the circuit, so that the outputs will respond to the
input levels only during the active period of a clock pulse.

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 Sample input and output waveforms illustrating the
operation of the clocked NOR based SR latch circuit.

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