CHAPTER TWO: Logic Gates

implementation using Resistors,

Diodes, and Transistors

Nana Diawuo
Objectives
Look at the implementation of the logic gates and devices using;
• Diode
• Diode Resistor logic [DRL]
• Transistor as an invertor
• Bipolar Transistor Logic [BTL]
• Resistor Transistor logic [RTL]
• Diode Transistor Logic [DTL]
• Transistor Transistor Logic [TTL]
• nMOS Implementation
• CMOS Implementation
Diode
A diode can be modelled as

Reverse bias Forward bias

 Diode (2)
•It is an open circuit when it is reverse biased (we
ignore its leakage current)

•It acts like a small resistance, Rf, in series with Vd, a

small voltage source.

•Rf is the forward resistance of the diode

•Vd is called diode drop, and is about 0.7 V

Diode Logic
•We can construct simple gates with nothing more
than two or more diodes and a resistor. See Figure
below
Simple gates from diodes and resistors
•The left of the figure above is a diode AND gate, and at the
right a diode OR gate.

•Let's examine the AND gate first.

 AND gate Implementation
• If one of the inputs A or B is grounded, current flows through the diode
and the output node X is at a low voltage. The only way to get a high
output is by having both inputs high. This is clearly a logical AND
function.

• To realize the basic idea, the diodes are reverse connected and forward
biased by an additional voltage source +V (a power supply) through the
pull-up resistor R1.
• The input voltage sources are connected in opposite direction to the
supplying voltage source (traveling along the loop +V - R1 - D - Vin). To
invert the output voltage and to get a grounded output, the
complementary voltage drop (+V - VR1) between the output and ground
is taken as an output instead the floating voltage drop VR1 across the
resistor.
Input logic ‘1’
• When all the input voltages are high, they "neutralize" the biasing
supply voltage +V. The voltage drops across the diodes are zero and
these diode switches are open.
• The output voltage is high (output logical 1) since no current flows
through the resistor and there is no voltage drop across it. The output
resistance is R1. Hence, the behavior of the diode switches is
reversed - whereas in diode OR logic gates diodes act as normally
open switches, in diode AND logic gates diodes act as normally closed
switches.
Input logic ‘0’
• If the voltage of some input voltage source is low, the power supply
passes current through the resistor, diode and the input source. The
diode is forward biased (the diode switch is closed) and the output
voltage drop across the diode is low.
• The output resistance is low and is determined by the input source.
The rest of diodes connected to high input voltages (input logical 1s)
are backward biased and their input sources are disconnected from
the output Node 1.
• A diode AND gate uses its own power supply to drive the load
through the pull-up resistor.
Diodes can perform digital logic functions: AND, and OR.

Diode AND gate

OR logic
•gates are implemented by parallel connected normally
open switches. So, in diode OR logic gates, the input
voltage sources are connected to diode anodes. Diode
cathodes are joined to the output which is connected
through the pull-down resistor R1 to ground.
•Whenever one or the other of the inputs A and B are high,
current flows through the associated diode.
OR logic
Input logic ‘1’;
• If the voltage of a particular input voltage source is high, the
according diode is forward biased and this diode switch is closed.
• The input source passes current through the diode and creates high
voltage drop across the resistor R1 (output logical 1). The rest of
diodes connected to low input voltage are backward biased and their
input sources (grounds) are disconnected from the output.
 OR logic
Input logic ‘0’.
• If all the input voltages are low, the voltage drops across the diodes are
zero. These diode switches are open and the input sources (grounds)
are disconnected from the output. No current flows through the
resistor. The output voltage is low (output logical 0) and the output
resistance is R1.
• A diode OR gate does not use its own power supply. The input sources
with high voltage (logical 1) supply the load through the forward-biased
diodes.
OR gate
 Setback Of Diode As A Logic Gate
•Unfortunately, it is difficult to cascade circuits of this kind into
multiple levels of logic gates. The voltage drops across the diodes
add up as they are cascaded in series, leading to significantly
degraded voltage levels.

•For example, suppose we wire up five diode-resistor AND gates in

series. If a string of inputs are logic 0 and the series diodes are
conducting, then the output from the final stage should be
recognized as a logic 0 as well. But because each diode adds a 0.7-V
drop, the measured output would actually be at 3.5 V. This is pretty
far from any voltage that would be recognized as logic 0.
Setback Of Diode As A Logic Gate
•Also note that it is not possible to construct an inverter with
only diodes and resistors.
•AND and OR functions by themselves are not a complete
logic without NOT.
•Thus, there are some logic functions that cannot be
implemented in diode-resistor logic.
•Fortunately, transistors solve all of these problems.
Solution to Using the Diode as Gate
• One solution is to increase the power supply voltage, redefining the
range that is recognized as a logic 0 and logic 1.

• Of course, the higher the voltage, the higher the power consumed
and the more heat the circuit generates.

• And no matter what you set the power supply to, there is still a limit
to the number of logic levels that can be cascaded. This is hardly an
adequate solution.
Bipolar Transistor Logic (Resistor–transistor logic
(RTL) )
•Next, we examine how to build logic gates
from bipolar transistors, the dominant
technology of the 1970s and early 1980s.

•Resistor–transistor logic (RTL) is a class of

digital circuits built using resistors as the
input network and bipolar junction
transistors (BJTs) as switching devices.
•A high voltage at the base turns on the transistor. The
output F is discharged to ground, getting close to 0 V
but never quite reaching it (it reaches a voltage drop
away from 0 V).

•When a low voltage is placed on the base, the transistor

is turned off. The output node F is charged up toward
the power supply voltage through the pull-up/load
resistor R1.
 RTL inverter
• A bipolar transistor switch is the simplest RTL gate (inverter or NOT
gate) implementing logical negation. It consists of a common-emitter
stage with a base resistor connected between the base and the input
voltage source. The role of the base resistor is to expand the
negligible transistor input voltage range (about 0.7 V) to the logical
"1" level (about 3.5 V) by converting the input voltage into current

• The role of the collector resistor is to convert the collector current

into voltage; its resistance is chosen high enough to saturate the
transistor and low enough to obtain low output resistance
One-transistor RTL NOR gate
• By connecting additional base resistors (R3 and
R4) to the inverter it is expanded to the
simplest RTL NOR gate.

• OR is performed by applying consecutively the

two arithmetic operations addition and
comparison (the input resistor network acts as
a parallel voltage summer with equally
weighted inputs and the next
common-emitter transistor stage - as a
voltage comparator with a threshold about 0.7
V).
Advantages

•The primary advantage of RTL technology was that it involved a

minimum number of transistors, which was an important
consideration before integrated circuit technology

•Early IC logic production used the same approach briefly, but

quickly transitioned to higher-performance circuits such as
diode–transistor logic and then transistor–transistor logic, since
diodes and transistors were no more expensive than resistors in
the IC.
Limitations
•The obvious disadvantage of RTL is its high power dissipation
when the transistor is switched on (the power is dissipated mainly
by the base resistors connected to logical "1" and by the collector
resistor). This requires that more current be supplied to and heat
be removed from RTL circuits.

•In contrast, TTL circuits with Push–pull output stage minimize

both of these requirements. (usually realized as a complementary
pair of transistors, one dissipating or sinking current from the load
to ground or a negative power supply, and the other supplying or
sourcing current to the load from a positive power supply).

•Another limitation of RTL was its limited fan-in.

Diode-Transistor Logic

Diode-transistor (DTL) NAND gate

 Diode-Transistor Logic
• Diodes, transistors, and resistors can be used to implemented a
wide variety of gates.
• Basically, we combine the diode logic of Figure above with the
transistor inverter to form NAND (not AND) and NOR (not OR )
functions.

• The diodes marked D1 and D2, together with resistor R1, form a
two-input AND function.
• At the input to D3, a logic 0 is represented by approximately 0.7 V,
while a logic 1 is in the range 4 to 5 V.
• D3 increases the voltage required to turn on the transistor. This
gives a better separation between the voltage levels recognized as
a logic 0 and logic 1.
•For the transistor to conduct, D3 must be turned on. This
happens when the anode voltage reaches 1.4 V.
•If the voltage at the anode is much higher than this, the
base will be driven to a high voltage.
• The transistor will be strongly turned on, with low
resistance, and thus F will be discharged toward 0 V. If the
anode is at a low voltage, the base will also be low.
•This keeps the transistor off (essentially infinite resistance)
allowing the output node to reach a logic 1 voltage level.
•Gates constructed as in above have a limit to the number of gate
inputs to which their output can be connected. This is called
fan-out.
 Transistor-Transistor Logic
•We can think of a bipolar transistor as two diodes placed very
close together, with the point between the diodes being the
transistor base.
•Thus, we can use transistors in place of diodes to obtain logic
gates that can be implemented with transistors and resistors
only.
•This is called transistor-transistor logic (TTL), and it is the most
widely used family of components available today.
A two-input TTL NAND gate is shown below

Two-input TTL NAND gate

Transistor-Transistor Logic
•This configuration has one significant advantage over the
diode implementation. Besides being voltage--controlled
switches, transistors also act as amplifiers.

•When the transistor base is undergoing a change in voltage,

the transistor can amplify this change, thus speeding up the
rate at which the transistor turns on or off. The result is
faster gate switching.
 How It Work
•In simplified terms, the circuit works as follows;
•When one of the inputs A or B is low, the current available
through R1 at the transistor base is diverted to ground. No
current flows from the base to the collector, and therefore no
current reaches the base of the output transistor.
•Thus, the output transistor is off. The pull-up resistor R2 charges
the output node to the high-voltage state. Only when both inputs
are high can the current flow through R1 from base to collector to
turn on the output transistor. In this case, the output path
discharges to ground.
TTL Circuits and Noise Margin
•A major achievement of TTL logic is the ease with which
different circuits can be interfaced and cascaded to form more
complex logic functions.
• In part, this is due to the concepts of guaranteed voltage levels
and noise margins

•A guaranteed voltage is one at which circuits always detect the

correct voltage level, within a specified temperature range
(0-70\xa1 C), voltage range (5 V ± 5%), loading, and the
parametric variance of the semiconductor devices themselves.
•TTL circuits are characterized by four voltage specifications: V , V ,
oh ol
V , and V .
ih il

•V (output high voltage) is the minimum voltage at which the circuit

oh
delivers a logic 1. Vol (output low voltage) is the maximum voltage at
which the circuit can produce a logic 0.

•Similarly, Vih (input high voltage) is the minimum voltage at which a

circuit detects a logic 1. Vil (input low voltage) is the maximum
voltage at which it recognizes a logic 0.

•For TTL circuits, V =2.4V, V =0.4V, V =2V, and V =0.8V.

oh ol ih il
•The input and output voltages differ by 0.4V. This permits the
output signals to be degraded by the wires between circuits but
still be recognized as good logic values. The difference between
Voh and Vih is called the high-state DC noise margin.

•The difference between Vol and Vil is called the low-state DC

noise margin.
 Field Effect Transistors
•We now turn our attention to logic functions constructed from
Field Effect Transistors, (FETs) the dominant technology of
today.

•Up until this point, our analysis of transistor logic circuits has
been limited to the TTL design paradigm, whereby bipolar
transistors are used, and the general strategy of floating inputs
being equivalent to "high" (connected to Vcc) inputs -- and
correspondingly, the allowance of "open-collector" output
stages -- is maintained.
•This, however, is not the only way we can build logic gates.
 IGFET logic gates (insulated-gate Field-effect
transistors)
•insulated-gate variety, may be used
in the design of gate circuits. Being
voltage-controlled rather than
current-controlled devices, IGFETs
tend to allow very simple circuit
designs.

•Example the inverter circuit built

using P- and N-channel IGFETs:
IGFET inverter
 How It Works
•Notice the "Vdd" label on the positive power supply terminal: it
stands for the constant voltage applied to the drain of a field
effect transistor, in reference to ground.

•When this gate circuit is connected to a power source and input

switch, it takes an applied voltage between gate and drain
(actually, between gate and substrate) of the correct polarity to
bias them on
• The upper transistor is a P-channel IGFET. When the channel
(substrate) is made more positive than the gate (gate negative in
reference to the substrate), the channel is enhanced and current is
allowed between source and drain. So, in the above illustration, the
top transistor is turned on.

• The lower transistor, having zero voltage between gate and substrate
(source), is in its normal mode: off. Thus, the action of these two
transistors are such that the output terminal of the gate circuit has a
solid connection to Vdd and a very high resistance connection to
ground. This makes the output "high" (1) for the "low" (0) state of the
input.
• move the input switch to its other position and see what happens.
Now the lower transistor (N-channel) is saturated because it has
sufficient voltage of the correct polarity applied between gate and
substrate (channel) to turn it on (positive on gate, negative on the
channel).
• The upper transistor, having zero voltage applied between its gate
and substrate, is in its normal mode: off. Thus, the output of this gate
circuit is now "low" (0). Clearly, this circuit exhibits the behavior of an
inverter, or NOT gate.
• Using FET instead of bipolar transistors has greatly simplified the
design of the inverter gate
• it has a natural "totem-pole" configuration, capable of both sourcing
and sinking load current
• Key to this gate circuit's elegant design is the complementary use of
both P- and N-channel IGFETs
Note;
•Since IGFETs are more commonly known as MOSFETs
(Metal-Oxide-Semiconductor Field Effect Transistor), and
this circuit uses both P- and N-channel transistors together,
•the general classification given to gate circuits like this one is
CMOS
CMOS: Complementary Metal Oxide Semiconductor.
nMOS logic Gate
A Vin T OUTP F
UT
0 0 OFF VDD 1

1 +5 ON VSS 0
nMOS NOR Gate
A B T1 T2 Output F

0 0 OFF OFF VDD 1

0 1 OFF ON 0 0

1 0 ON OFF 0 0

1 1 ON ON 0 0

Instead of a Resitor, we can use an nMOS in

Depletion mode to save power (low rate of heat
dissipation)
nMOS NAND Gate

A B T1 T2 Output F

0 0 OFF OFF VDD 1

0 1 OFF ON VDD 1

1 0 ON OFF VDD 1

1 1 ON ON 0 0

Instead of a Resitor, we can use an nMOS in

Depletion mode to save power (low rate of heat
dissipation)
Depletion and Enhancement of nMOS
Devices
• Depletion mode nMOS is use instead of the the resistors to reduce
power dissipation.
• This improve the use of nMOS as a logic Gate in terms of power
dissipation.
 Logic Gates from MOS Devices
•An nMOS transistor conducts when the gate voltage
is asserted in positive logic.
• The pMOS transistor conducts when the gate is
asserted in negative logic.

•This is why there is a polarity bubble on the gate of

the pMOS transistor's symbol.
•Any logic gate can be constructed from a
combination of nMOS and pMOS transistors
Logic Gates from MOS Devices

(a)Inveter (b)NAND (c)NOR

 Operation
• The power supply (+5 V) and ground (0 V) represent logic 1 and logic 0,
respectively.
• The inverter is constructed from an nMOS and a pMOS transistor
connected in series between power and ground.
• When A is a logic 1, the nMOS transistor is conducting and the pMOS
transistor is not.
• The only unbroken connection path is from ground to the output node.
Thus, a logic 1 at the input yields a logic 0 at the output.
• When A is a logic 0, Now the pMOS transistor conducts while the nMOS
transistor does not. The output node is connected to a logic 1. A 0 at the
input yields a 1 at the output.
• The series transistors implement an inverter.
Basic CMOS inverter

A Vin T1 T2 OUT F
PUT
0 0 ON OFF VDD 1

1 +5 OFF ON 0 0
NAND logic gate implementations with
CMOS
Truth Table
A B T1 T2 T3 T4 Outp F
ut
0 0 ON ON OF OF 0 0
T1 F F
0 1 ON OF OF ON VDD 1
F F
T2 1 0 OF ON ON OF VDD 1
F F
1 1 OF OF ON ON VDD 1
F F
T3 T4
NAND logic gate implementations with
CMOS
• constructed from two nMOS transistors in series between the output
node and ground and two pMOS transistors in parallel between the
output node and the power supply.
• A path between the output node and ground can be established only
when both of the nMOS transistors are conducting. This happens only if
A and B are both at a logic 1. In this case, the two pMOS transistors are
not conducting, breaking all paths between the output node and the
logic 1 at the power supply. This is the case A = B = 1, output = 0.

• Now what happens if one or both of A and B are at a logic 0? Let's take
the case A = 0 and B = 1
• The nMOS transistor controlled by A is not conducting, breaking the
path from the output to ground. The pMOS transistor it controls is
conducting, establishing the path from the power supply to the
output. The other path, controlled by B, is broken, but this has no
effect on the output node as long as some path exists between it and
some voltage source.

• The case A = 1 and B = 0 is symmetric. If both inputs are 0, there are

now two paths between the power supply's logic 1 and the output
node. Of course, this doesn't change the logic signal at the output: it
is still a logic 1.

• it should be obvious that the circuit configuration performs the

function of a NAND gate.
Observation
•
NOR logic gate implementations with CMOS
A B T1 T2 T3 T4 Out F
put
0 0 ON ON OF OF VD 1
T1 T2 F F D
0 1 ON OF OF ON 0 0
F F
1 0 OF ON ON OF 0 0
F F
T4
1 1 OF OF ON ON 0 0
F F
T3
•Using the observation we just made, the pull-up network is A ̅·B ̅,
the pull-down network is A + B, and the function is 0 when A + B
is true and is 1 when A ̅·B ̅, ( (A+B) ̅) is true.
•Analysing the transistor network directly, the output node can
be 1 only if both transistors between it and the power supply
are conducting.

•Thus the output is 1 if both inputs are 0. If either or both inputs

are 1, then the path to the power supply is broken while at least
one path from the output to ground is established. The network
does indeed implement the NOR function.
 CMOS Transmission Gate
• it turns out that pMOS transistors are great at transmitting a logic 1
voltage without signal loss, but the same cannot be said about logic 0
voltages. Having 0 V at one side of a conducting pMOS transistor yields a
voltage at the other side somewhat higher than 0 V.
• NMOS transistors have a -complementary problem: they are great at
passing logic 0 but awful at passing logic 1.
• In the circuits we have looked at so far, pMOS transistors in the pull-up
network passed only ones while the nMOS transistors in the pull-down
network passed only zeros. So everything works out fine.
•
As you may guess, the best possible transmission behavior can be
-obtained by combining both kinds of transistors. This yields the CMOS
transmission gate,
•
CMOS transmission gate
Advantage of CMOS transmission gate
•The use of CMOS transmission gates to implement digital
subsystems requires fewer transistors than would be the
case if traditional gates were used.
The "buffer" gate
• If we were to connect two inverter gates together so that the output
of one fed into the input of another, the two inversion functions
would "cancel“ each other out so that there would be no inversion
from input to final output
The "buffer" gate
Why The "buffer" gate
• While this may seem like a pointless thing to do, it does have
practical application.
• Remember that gate circuits are signal amplifiers, regardless of
what logic function they may perform. A weak signal source (one
that is not capable of sourcing or sinking very much current to a
load) may be boosted by means of two inverters like the pair
shown in the previous illustration.
• The logic level is unchanged, but the full current-sourcing or
-sinking capabilities of the final inverter are available to drive a
load resistance if needed.
Summary;
Terminology
• The fan-out of a logic gate output is the number of gate inputs it can
feed or connect to.
• Fan-in is the number of inputs a gate can handle
• Pull-up
• Pull-down