126 Chapter 3 CMOS Processing Technology

Reduction in Q occurs because of the resistive loss in the conductors used to build the
inductor (Rs), and the eddy current loss in the resistive silicon substrate (Rp). In an effort
to increase Q, designers have resorted to removing the substrate below the inductor using
MEMS techniques [Yoon02]. The easiest way to improve the Q of monolithic inductors is
to increase the thickness of the top-level metal. The Q can also be improved by using a
patterned ground shield in polysilicon under the inductor to decrease substrate losses.

(a)

s w

(b)

FIGURE 3.26 Microstrip and coplanar waveguide

3.4.3.4 Transmission Lines A transmission line can be used on a chip to provide a known
impedance wire. Two basic kinds of transmission lines are commonly used: microstrips and
coplanar waveguides.
A microstrip transmission line, as shown in Figure 3.26(a), is composed of a wire of
width w and thickness t placed over a ground plane and separated by a dielectric of height
h and dielectric constant k. In the chip case, the wire might be the top level of metalliza-
tion and the ground plane the next metal layer down.
A coplanar waveguide does not require a sublayer ground plane and is shown in Fig-
ure 3.26(b). It consists of a wire of width w spaced s on each side from coplanar ground
wires. The reader is referred to [Wadell91] for detailed design equations.

3.4.3.5 Bipolar Transistors Bipolar transistors were mentioned previously in our discus-
sion of SiGe process options. Both npn and pnp bipolar transistors can be added to a
CMOS process, which is then called a BiCMOS process. These processes tend to be used
for specialized analog or high-voltage circuits. In a regular n-well process, a parasitic verti-
cal pnp transistor is present that can be used for circuits such as bandgap voltage refer-
ences. This transistor is shown in Figure 3.27 with the p-substrate collector, the n-well
base, and the p-diffusion emitter. Both process cross-section and layout are shown. This
transistor, in conjunction with a parasitic npn, is the cause of latchup (see Section 7.3.6).

3.4.3.6 Embedded DRAM Dynamic RAM (DRAM) uses a single transistor and a capaci-
tor to store a bit of information. It is about five times denser than static RAM (SRAM)
conventionally used on CMOS logic chips, so it can reduce the size of a chip containing
large amounts of memory. DRAM was conventionally manufactured on specialized pro-
cesses that produced low-performance logic transistors. DRAM requires specialized struc-
tures to build capacitors in a small area. One common structure is a trench, which is etched