3.

4 CMOS Process Enhancements 127

Base

p+ diode

Emitter Base Collector n+ well

Contact

p+ diffusion Emitter
n+ p+
n-well
n-well
Collector

p-substrate p+ substrate Contact p-substrate

Cross-Section Representative Layout

FIGURE 3.27 Vertical pnp bipolar transistor

down into the substrate. Some recent processes have introduced compact capacitor struc-
tures for building embedded DRAM alongside high-performance logic. Section 12.3 dis-
cusses DRAM in more depth.

3.4.3.7 Non-Volatile Memory Non-volatile memory (NVM) retains its state when the
power is removed from the circuit. The simplest NVM is a mask-programmed ROM cell
(see Section 12.4). This type of NVM is not reprogrammable or programmable after the
device is manufactured. A one-time programmable (OTP) memory can be implemented
using a fuse constructed of a thin piece of metal through which is passed a current that
vaporizes the metal by exceeding the current density in the wire. The first reprogrammable
memories used a stacked polysilicon gate structure and were programmed by applying a
high voltage to the device in a manner that caused Fowler-Nordheim tunneling to store a
charge on a floating gate. The whole memory could be erased by exposing it to UV light
that knocked the charge off the gate. These memories evolved to electrically erasable mem-
ories, which are today represented by Flash memory.
A typical Flash memory transistor is shown in Figure 3.28 [She02]. The source and
drain structures can vary considerably to allow for high-voltage operation, but the dual-
gate structure is fairly common. The gate structure is a stacked configuration commencing
with a thin tunnel oxide or nitride. A floating polysilicon gate sits on top of this oxide and
a conventional gate oxide is placed on top of the floating gate. Finally, a polysilicon control
gate is placed on top of the gate oxide. The operation of the cell is also shown in Figure

Control Gate 0V 20 V 0V
Gate Oxide
Floating Gate
Tunnel Oxide 0V 1.2 V Floating 1.2 V Floating Floating
p-well 0V 0V 20 V
n-well Normal Program Deprogram
p-substrate Operation

FIGURE 3.28 Flash memory construction and operation