3.

6 Manufacturing Issues 135

The design community is presently debating a move toward restrictive design rules to
facilitate RET and reduce manufacturing variability by limiting designers to a smaller set
of uniform layout features. These rules might come at the expense of greater area. For
example, Intel introduced restrictive design rules for polysilicon in the 45 nm process to 50 +m
control variation and facilitate 193 nm double-patterning lithography [Webb08]. Under
these rules, polysilicon is limited to one pitch and direction in layout. This also simplified
contact and metal1 rules: the contact pitch is the same as the gate pitch, and metal1 paral-
lel to the gates also has the same pitch. Wide poly pads for contacts and orthogonal poly-
silicon routing were eliminated by introducing a trench contact suitable for local
interconnect. Intel found that the restrictive rules did not impact standard cell density and
that excellent yield is achieved.

3.6.4 Metal Slotting Rules

Some processes have special rules requiring that wide (e.g. > 10–40 Rm) metal wires have
slots. Slots are long slits, on the order of 3 Rm wide, in the wire running parallel to the
direction of current flow, as shown in Figure 3.37. They provide stress relief, help keep the
wire in place, and reduce the risk of electromigration failure (see Section 7.3.3.1). Design
rules vary widely between manufacturers.

3.6.5 Yield Enhancement Guidelines

To improve yield, some processes recommend increasing certain widths and spacings where
they do not impact area or performance. For example, increasing the polysilicon gate exten- FIGURE 3.37 Slots in
sion slightly reduces the risk of transistor failures from poly/diffusion mask misalignment. wide metal power bus
Increasing space between metal lines where possible reduces the risk of shorts and also
reduces wire capacitance. Other good practices to improve yield include the following:
 Space out wires to reduce risk of short circuits and reduce capacitance.
 Use non-minimum-width wires to reduce risk of open circuits and to reduce
resistance.
 Use at least two vias for every connection to avoid open circuits if one via is
malformed, and to reduce electromigration wearout.
 Surround contacts and vias by landing pads with more than the minimum overlap
to reduce resistance variation and open circuits caused by misaligned contacts.
 Use wider-than-minimum transistors; minimum-width transistors are subject to
greater variability and tend not to perform as well.
 Avoid non-rectangular shapes such as 45-degree angles and circles. For specialized
circuits such as RAMs that strongly benefit from 45-degree angles, verify masks
after optical proximity correction analysis.
 Place dummy transistors or cells at the edge of arrays and sensitive circuits to
improve uniformity and matching.
 If it looks nice, it will work better.

3.37 Pitfalls and Fallacies