3.

3 Layout Design Rules 115

n-well

Active

p-select

n-select

Poly

(a)

n-well

n-diffusion

p-diffusion

Poly

Substrate Contact n-transistor Gate Extension p-transistor Well Contact

(b)
FIGURE 3.15 CMOS n-well process transistor and well/substrate contact construction

 Metal to polysilicon
 Metal to well or substrate
Depending on the process, other contacts such as buried polysilicon-active contacts
may be allowed for local interconnect.
Because the substrate is divided into well regions, each isolated well must be tied to the
appropriate supply voltage; i.e., the n-well must be tied to VDD and the substrate or p-well
must be tied to GND with well or substrate contacts. As mentioned in Section 1.5.1, metal
makes a poor connection to the lightly doped substrate or well. Hence, a heavily doped
active region is placed beneath the contact, as shown at the source of the nMOS transistor
in Figure 3.16.
Whenever possible, use more than one contact at each connection. This significantly
improves yield in many processes because the connection is still made even if
one of the contacts is malformed.
Mask Summary: The only mask involved with contacts to active or poly
is the contact mask, commonly called CONT or CA. Contacts are normally of Substrate Contact
uniform size to allow for consistent etching of very small features.
p+
3.3.1.4 Metal Rules Metal spacing may vary with the width of the metal line n+ n+
(so called fat-metal rules). That is, above some metal wire width, the mini-
mum spacing may be increased. This is due to etch characteristics of small ver-
sus large metal wires. There may also be maximum metal width rules. That is,
single metal wires cannot be greater than a certain width. If wider wires are
desired, they are constructed by paralleling a number of smaller wires and FIGURE 3.16 Substrate contact