176 Chapter 4 Delay

pipeline and enormous power consumption. Microarchitects predicted that performance

would be maximized at a cycle time of only 8 FO4 delays/cycle [Hrishikesh02].
The short cycle times came at the expense of vast numbers (20–30) of pipeline stages
and enormous power consumption (nearly 100 W). As will be seen in the next chapter,
power became as important as performance specifications. The number of gates per cycle
rebounded to a more power-efficient point. [Srinivasan02] observed that 19–24 FO4
delays per cycle provides a better trade-off between performance and power.
Application-specific integrated circuits have generally operated at much lower fre-
quencies (e.g., 200–400 MHz in nanometer processes) so that they can be designed more
easily. Typical ASIC cycle times are 40–100 FO4 delays per cycle [Mai05, Chinnery02],
although performance-critical designs sometimes are as fast as 25 FO4s.

Summary
The VLSI designer’s challenge is to engineer a system that meets speed requirements
while consuming little power or area, operating reliably, and taking little time to design.
Circuit simulation is an important tool for calculating delay and will be discussed in depth
in Chapter 5, but it takes too long to simulate every possible design; is prone to garbage-
in, garbage-out mistakes; and doesn’t give insight into why a circuit has a particular delay
or how the circuit should be changed to improve delay. The designer must also have simple
models to quickly estimate performance by hand and explain why some circuits are better
than others.
Although transistors are complicated devices with nonlinear current-voltage and
capacitance-voltage relationships, for the purpose of delay estimation in digital circuits,
they can be approximated quite well as having constant capacitance and an effective resis-
tance R when ON. Logic gates are thus modeled as RC networks. The Elmore delay
model estimates the delay of the network as the sum of each capacitance times the resis-
tance through which it must be charged or discharged. Therefore, the gate delay consists
of a parasitic delay (accounting for the gate driving its own internal parasitic capacitance)
plus an effort delay (accounting for the gate driving an external load). The effort delay
depends on the electrical effort (the ratio of load capacitance to input capacitance, also
called fanout) and the logical effort (which characterizes the current driving capability of
the gate relative to an inverter with equal input capacitance). Even in advanced fabrication
processes, the delay vs. electrical effort curve fits a straight line very well. The method of
Logical Effort builds on this linear delay model to help us quickly estimate the delay of
entire paths based on the effort and parasitic delay of the path. We will use Logical Effort
in subsequent chapters to explain what makes circuits fast.

Exercises
4.1 Sketch a 2-input NOR gate with transistor widths chosen to achieve effective rise
and fall resistances equal to a unit inverter. Compute the rising and falling propaga-
tion delays of the NOR gate driving h identical NOR gates using the Elmore delay
model. Assume that every source or drain has fully contacted diffusion when making
your estimate of capacitance.
4.2 Sketch a stick diagram for the 2-input NOR. Repeat Exercise 4.1 with better capac-
itance estimates. In particular, if a diffusion node is shared between two parallel