3.

2 CMOS Technologies 111

by evaporation or sputtering. Evaporation is performed by passing metal1

a high electrical current through a thick aluminum wire in a vac-
uum chamber. Some of the aluminum atoms are vaporized and
deposited on the wafer. An improved form of evaporation that
S G D
suffers less from contamination focuses an electron beam at a
container of aluminum to evaporate the metal. Sputtering is Contact
achieved by generating a gas plasma by ionizing an inert gas
using an RF or DC electric field. The ions are focused on an alu- n+ n+
p-well
minum target and the plasma dislodges metal atoms, which are
then deposited on the wafer.
Wet or dry etching can be used to remove unwanted metal.
Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen
peroxide that is used to clean wafers of organic and metal con- FIGURE 3.11 Aluminum metallization
taminants or photoresist after metal patterning. Plasma etching
is a dry etch process with fluorine or chlorine gas used for met-
allization steps. The plasma charges the etch gas ions, which are
attracted to the appropriately charged silicon surface. Very sharp etch profiles can be
achieved using plasma etching. The result of the contact and metallization patterning
steps is shown in Figure 3.11.
Subsequent intermetal vias and metallization are then applied. Some processes offer
uniform metal dimensions for levels 2 to n–1, where n is the top level of metal. The top
level is normally a thicker layer for use in power distribution and as such has relaxed width
and spacing constraints. Other processes use successively thicker and wider metal for the
upper layers, as will be explored in Section 6.1.2.
Polysilicon over diffusion normally forms a transistor gate, so a short metal1 wire is
necessary to connect a diffusion output node to a polysilicon input. Some processes add
tungsten (W) layer above polysilicon and below metal1; this layer is called local intercon-
nect and can be drawn on a finer pitch than metal1. Local interconnect offers denser cell
layouts, especially in static RAMs. Figure 3.12 shows a scanning electron micrograph of a
partially completed SRAM array. The oxide has been removed to show the diffusion,
polysilicon, local interconnect, and metal1. Local interconnect is used to connect the
nMOS and pMOS transistors without rising up to metal1. SRAM cells are discussed fur-
ther in Section 12.2.

metal1
VDD
Unit Cell

Contact Stud

Local interconnect
between n and p
Polysilicon
diffusion
Wordline
n-diffusion

FIGURE 3.12 Partially completed 6-transistor SRAM array using local interconnect
(Courtesy of International Business Machines Corporation. Unauthorized use not
permitted.)