RFID and GSM Based Vehicle Number Plate Recognition

RFID and GSM based Number Plate Recognition And Ignition Cut off
INTRODUCTION
The term RFID is a data collection technology that uses electronic tags for storing
data and remotely retrieving data using devices and can be applied to or incorporated into a
product or person for the purpose of identification using radio waves. Some can be read from
several meters away and beyond the line of sight of the reader.
GSM is a cellular network, which means that mobile phones connect to it by

searching for cells in the immediate vicinity. There are five different cell sizes in a GSM
network—macro, micro, pico, femto and umbrella cells. The coverage area of each cell
varies according to the implementation environment. Macro cells can be regarded as cells
where the base station antenna is installed on a mast or a building above average roof top
level. Micro cells are cells whose antenna height is under average roof top level; they are
typically used in urban areas. Picocells are small cells whose coverage diameter is a few
dozen metres; they are mainly used indoors. Femtocells are cells designed for use in
residential or small business environments and connect to the service provider’s network via
a broadband internet connection. Umbrella cells are used to cover shadowed regions of
smaller cells and fill in gaps in coverage between those cells.
MAIN OBJECTIVE
The recent past has seen a marked increase in the number of thefts of vehicles. These
stolen vehicles are used for anti-social activities. This project emphasizes on the need to
reduce these activities and proposes a model for number plate recognition of vehicles and
their ignition cut off using RFID and GSM. Here, an RFID card is placed in the vehicles with
predetermined identification code. Each time a vehicle passes the check post or any other
check points, the RFID reader reads the ID number and provides the total information about
the vehicles. The information is displayed using the monitor and if it is identified to be a theft
vehicle, it provides an alert signal to the people concerned at the check point. The vehicle
ignition cut off is done using GSM. An attempt to change the RFID card or the SIM card
inside the modem in the vehicle without any authorization leads to the ignition being
disconnected and an sms is sent to a pre-determined number. Hardware interface of the
SIMCOM SIM300 module connects to the specific application and the air interface.
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Block Diagram Description:
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HARDWARE DESCRIPTION:
1.RFID MODULE
How do RFIDs work.
Shown below is a typical RFID system. In every RFID system the transponder Tags
contain information. This information can be as little as a single binary bit , or be a large
array of bits representing such things as an identity code, personal medical information, or
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literally any type of information that can be stored in digital binary format.
Shown is a RFID transceiver that communicates with a passive Tag. Passive tags have no
power source of their own and instead derive power from the incident electromagnetic
field. Commonly the heart of each tag is a microchip. When the Tag enters the generated
RF field it is able to draw enough power from the field to access its internal memory and
transmit its stored information.
`When the transponder Tag draws power in this way the resultant interaction of the
RF fields causes the voltage at the transceiver antenna to drop in value. This effect is
utilized by the Tag to communicate its information to the reader. The Tag is able to control
the amount of power drawn from the field and by doing so it can modulate the voltage
sensed at the Transceiver according to the bit pattern it wishes to transmit.
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COMPONENTS OF RFID
A basic RFID system consist of three components:
• An antenna or coil
• A transceiver (with decoder)
• A transponder (RF tag) electronically programmed with unique information
1. ANTENNA
The antenna emits radio signals to activate the tag and read and write data to it. Antennas are
the conduits between the tag and the transceiver, which controls the system's data acquisition
and communication. Antennas are available in a variety of shapes and sizes; they can be built
into a door frame to receive tag data from persons or things passing through the door, or
mounted on an interstate tollbooth to monitor traffic passing by on a freeway. The
electromagnetic field produced by an antenna can be constantly present when multiple tags
are expected continually. If constant interrogation is not required, a sensor device can
activate the field.
Often the antenna is packaged with the transceiver and decoder to become a reader (a.k.a.
interrogator), which can be configured either as a handheld or a fixed-mount device. The
reader emits radio waves in ranges of anywhere from one inch to 100 feet or more,
depending upon its power output and the radio frequency used. When an RFID tag passes
through the electromagnetic zone, it detects the reader's activation signal. The reader decodes
the data encoded in the tag's integrated circuit (silicon chip) and the data is passed to the host
computer for processing.
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2. TAGS (Transponders)
An RFID tag is comprised of a microchip containing identifying information and an antenna

that transmits this data wirelessly to a reader. At its most basic, the chip will contain a
serialized identifier, or license plate number, that uniquely identifies that item, similar to the
way many bar codes are used today. A key difference, however is that RFID tags have a
higher data capacity than their bar code counterparts. This increases the options for the type
of information that can be encoded on the tag, including the manufacturer, batch or lot
number, weight, ownership, destination and history (such as the temperature range to which
an item has been exposed). In fact, an unlimited list of other types of information can be
stored on RFID tags, depending on application needs. An RFID tag can be placed on
individual items, cases or pallets for identification purposes, as well as on fixed assets such
as trailers, containers, totes, etc.
RFID transponder tags up to 1 ¾” - 3” inches away depending on the tag (see list below).
The RFID Reader Module can be used in a wide variety of hobbyist and commercial
applications, including access control, automatic identification, robotics navigation,
inventory tracking, payment systems, and car immobilization.
• Fully-integrated, low-cost method of reading passive RFID transponder tags
• 1-wire, 9600 baud Serial TTL interface to PC, and other processors
• Requires single +5VDC supply
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• Bi-color LED for visual indication of activity

• 0.100” pin spacing for easy prototyping and integration
Each transponder tag contains a unique identifier (one of 240, or

1,099,511,627,776, possible combinations) that is read by the RFID Reader Module and
transmitted to the host via a simple serial interface.
Tags come in a variety of types, with a variety of capabilities. Key variables include:
"Read-only" versus "read-write"
There are three options in terms of how data can be encoded on tags: (1) Read-only tags
contain data such as a serialized tracking number, which is pre-written onto them by the tag
manufacturer or distributor. These are generally the least expensive tags because they cannot
have any additional information included as they move throughout the supply chain. Any
updates to that information would have to be maintained in the application software that
tracks SKU movement and activity. (2) "Write once" tags enable a user to write data to the
tag one time in production or distribution processes. Again, this may include a serial number,
but perhaps other data such as a lot or batch number. (3) Full "read-write" tags allow new
data to be written to the tag as needed—and even written over the original data. Examples for
the latter capability might include the time and date of ownership transfer or updating the
repair history of a fixed asset. While these are the most costly of the three tag types and are
not practical for tracking inexpensive items, future standards for electronic product codes
(EPC) appear to be headed in this direction.
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RFID TAGS
Data capacity
The amount of data storage on a tag can vary, ranging from 16 bits on the low end to
as much as several thousand bits on the high end. Of course, the greater the storage capacity,
the higher the price per tag.
Form factor
The tag and antenna structure can come in a variety of physical form factors and can
either be self-contained or embedded as part of a traditional label structure (i.e., the tag is
inside what looks like a regular bar code label—this is termed a 'Smart Label') companies
must choose the appropriate form factors for the tag very carefully and should expect to use
multiple form factors to suit the tagging needs of different physical products and units of
measure. For example, a pallet may have an RFID tag fitted only to an area of protected
placement on the pallet itself. On the other hand, cartons on the pallet have RFID tags inside
bar code labels that also provide operators human-readable information and a back-up should
the tag fail or pass through non RFID-capable supply chain links.
Passive versus active
“Passive” tags have no battery and "broadcast" their data only when energized by a
reader. That means they must be actively polled to send information. "Active" tags are
capable of broadcasting their data using their own battery power. In general, this means that
the read ranges are much greater for active tags than they are for passive tags—perhaps a
read range of 100 feet or more, versus 15 feet or less for most passive tags. The extra
capability and read ranges of active tags, however, come with a cost; they are several times
more expensive than passive tags. Today, active tags are much more likely to be used for
high-value items or fixed assets such as trailers, where the cost is minimal compared to item
value, and very long read ranges are required. Most traditional supply chain applications,
such as the RFID-based tracking and compliance programs emerging in the consumer goods
retail chain, will use the less expensive passive tags.
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Frequencies
Like all wireless communications, there are a variety of frequencies or spectra

through which RFID tags can communicate with readers. Again, there are trade-offs among
cost, performance and application requirements. For instance, low-frequency tags are cheaper
than ultra high-frequency (UHF) tags, use less power and are better able to penetrate non-
metallic substances. They are ideal for scanning objects with high water content, such as
fruit, at close range. UHF frequencies typically offer better range and can transfer data faster.
But they use more power and are less likely to pass through some materials. UHF tags are
typically best suited for use with or near wood, paper, cardboard or clothing products.
Compared to low-frequency tags, UHF tags might be better for scanning boxes of goods as
they pass through a bay door into a warehouse. While the tag requirements for compliance
mandates may be narrowly defined, it is likely that a variety of tag types will be required to
solve specific operational issues. You will want to work with a company that is very
knowledgeable in tag and reader technology to appropriately identify the right mix of RFID
technology for your environment and applications.
EPC Tags
EPC refers to "electronic product code," an emerging specification for RFID tags,
readers and business applications first developed at the Auto-ID Center at the Massachusetts
Institute of Technology. This organization has provided significant intellectual leadership
toward the use and application of RFID technology. EPC represents a specific approach to
item identification, including an emerging standard for the tags themselves, including both
the data content of the tag and open wireless communication protocols. In a sense, the EPC
movement is combining the data standards embodied in certain bar code specifications, such
as the UPC or UCC-128 bar code standards, with the wireless data communication standards
that have been developed by ANSI and other groups.
3. RF Transceiver:
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The RF transceiver is the source of the RF energy used to activate and power the passive
RFID tags. The RF transceiver may be enclosed in the same cabinet as the reader or it may
be a separate piece of equipment. When provided as a separate piece of equipment, the
transceiver is commonly referred to as an RF module. The RF transceiver controls and
modulates the radio frequencies that the antenna transmits and receives. The transceiver
filters and amplifies the backscatter signal from a passive RFID tag.
Electronic Connections
Pin Pin Name Type Function

1 VCC Power System power, +5V DC input.
2 /enable Input Module enable pin. Active LOW digital
input. Bring this pin LOW to
enable the RFID reader and activate the
antenna.
3 Sout Output Serial Out. TTL-level interface,
9600bps, 8 data bits, no parity, 1 stop
bit.
4 GND Ground System ground. Connect to power
supply’s ground (GND) terminal
Communication Protocol
Implementation and usage of the RFID Reader Module is straightforward.
The RFID Reader Module is controlled with a single TTL-level active-low /ENABLE pin.
When the /ENABLE pin is pulled LOW, the module will enter its active state and enable the
antenna to interrogate for tags.
The current consumption of the module will increase dramatically when the module is
active. A visual indication of the state of the RFID Reader Module is given with the on-board
LED. When them module is successfully powered-up and is in an idle state, the LED will be
GREEN. When the module is in an active state and the antenna is transmitting, the LED will
be RED. The face of the RFID tag should be held parallel to the front or back face of the
antenna (where the majority of RF energy is focused). If the tag is held sideways
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(perpendicular to the antenna) you'll either get no reading or a poor reading. Only one
transponder tag should be held up to the antenna at anytime. The use of multiple tags at one
time will cause tag collisions and confuse the reader. The two tags used here have a read
distance of approximately 3 inches. Actual distance may vary lightly depending on the size
of the transponder tag and environmental conditions of the application. When a valid RFID
transponder tag is placed within range of the activated reader, the unique ID will be
transmitted as a string via the TTL-level SOUT (Serial Output) pin . RFID Reader Module
can connect directly to any TTL-compatible UART or to an RS232-compatible interface by
using an external level shifter.
The GSM Network

2.1 Introduction :
The GSM network was designed keeping in mind the voice activities of the user and
its main purpose was to provide voice connectivity like Public Switched Telephone Networks
but with mobility. So Call Processing activities were the major criteria to decide and fix the
implementation standards of GSM. The data communication was of secondary importance to
this network but to support this also, designers have considered the circuit switching itself the
mechanism for transmitting data packets.
2.2 GSM Architecture
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HLR/
UM VLR
Handset
A-bis A SS7
BSC MSC
PSTN
X.25
BTS OMC
(Operation & Maintenance
Center)
Operation Data Terminal

SIM Terminal
card
Mobile Radio Network sub-system PSTN

station sub-system
Figure 2.2 GSM Architecture
The Mobile Station (MS) directly interacts with one of the Base Transceiver Stations,
which in turn interacts with a Base Station Controllers (BSC). BTS and BSC combined
together forms the BSS. More than one BTSs are connected with one BSC. The BSC further
interacts with Mobile Station Controller (MSC) which is a the heart of the GSM network.
MSC further gives connectivity to the PSTN and other PLMNs. MSC is also responsible to
interact with HLR and VLR, which form the Permanent and Temporary data bases for all the
subscribers static and dynamic information.
2.3 GSM Protocol Stack
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Figure 1.3 GSM Protocol Stack
2.3.1 Protocols on the Um interface
• Layer 1: Physical layer.
• Layer 2: Here the LAP-Dm protocol is used (similar to ISDN LAP-D). LAP-Dm has the
following functions :
- Connectionless transfer on point-to-multipoint signaling channels.
- Setup and take-down of layer 2 connections on point-to-point signaling
channels.
- Connection-oriented transfer with retention of the transmission sequence, error
detection and error correction.
• Layer 3: Contains the following sublayers which control signaling channel functions
(BCH,CCCH and DCCH).
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- Radio Resource Management (RR) : The role of the RR management layer is to

establish and release stable connection between mobile stations(MS) and an MSC for
the duration of a call, and to maintain it despite user movements. The following
functions are performed by the MSC
- Call selection
- Handover
- Allocation and take-down of point-to-point channels
- Monitoring and forwarding of radio connections
- Introduction of encryption
- Change in transmission mode
- Mobility Management (MM) : Mobility Management handles the control functions

required for mobility e.g.
- Authentication
- Assignment of TMSI
- Management of subscriber location
- Connection Management (CM) : Connection Management is used to setup, maintain

and take down call connections; it is comprised of three subgroups :
- Call Control(CC) :- Manages call connections.

- Supplementary Service Support(SS) :- Handles special services.
- Short Message Service Support(SMS) :- Transfers brief texts.
Neither the BTS nor the BSC interpret CM and MM messages. They are simply exchanged
with the MSC or the MS using the Direct Transfer Application Part (DTAP) protocol on the
A interface. RR messages are mapped to or from the Base Station System Application Part
(BSSAP) in the BSCREF for exchange with the MSC.
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2.4 General behaviors
2.4.1 SIM Insertion, SIM Removal
SIM card Insertion and Removal procedures are supported. There are software functions
relying on positive reading of the hardware SIM detect pin. This pin state (open/closed) is
permanently monitored. When the SIM detect pin indicates that a card is present in the SIM
connector, the product tries to set up a logical SIM session. The logical SIM session will be
set up or not depending on whether the detected card is a SIM Card or not. The AT+CPIN?
command delivers the following responses:
• If the SIM detect pin indicates “absent”, the response to AT+CPIN? Is “+CME
ERROR 10” (SIM not inserted).
• If the SIM detect pin indicates “present”, and the inserted Card is a SIM Card, the
response to AT+CPIN? is “+CPIN: xxx” depending on SIM PIN state.
• If the SIM detect pin indicates “present”, and the inserted Card is not a SIM Card, the
response to AT+CPIN? is CME ERROR 10.
• These last two states are not given immediately due to background initialization.
Between the hardware SIM detect pin indicating “present” and the previous results
the AT+CPIN? sends “+CME ERROR: 515” (Please wait, init in progress).
• When the SIM detect pin indicates card absence, and if a SIM Card was previously
inserted, an IMSI detach procedure is performed, all user data is removed from the
product (Phonebooks, SMS etc.). The product then switches to emergency mode.
2.4.2 Attention (AT) Commands
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GSM modem can be controlled by standard set of AT (Attention) commands. These

commands can be used to control majority of the functions of GSM modem. Few commands
used in this project are described below
2.4.2.1 Select message service +CSMS
Description :
The supported services are originated (SMS-MO) and terminated short message
(SMS-MT) + Cell Broadcast Message (SMS-CB) services.
Syntax :
Defined values :
<service>
0: SMS AT commands are compatible with GSM 07.05 Phase 2 version 4.7.0.
1: SMS AT commands are compatible with GSM 07.05 Phase 2 + version .
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2.4.2.2 Preferred Message Format +CMGF
Description :
The message formats supported are text mode and PDU mode. In PDU mode, a
complete SMS Message including all header information is given as a binary string (in
hexadecimal format). Therefore, only the following set of characters is allowed:
{‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’,’8’,’9’, ‘A’, ‘B’,’C’,’D’,’E’,’F’}. Each pair or characters is
converted to a byte (e.g.: ‘41’ is converted to the ASCII character ‘A’, whose ASCII code is
0x41 or 65).
In Text mode, all commands and responses are in ASCII characters. The format
selected is stored in EEPROM by the +CSAS command.
Syntax :
Example, sending an SMS Message in PDU mode
Defined values :
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The <pdu> message is composed of the SC address (« 00 means no SC address given,

use default SC address read with +CSCA command) and the TPDU message.In this example,
the length of octets of the TPDU buffer is 14, coded as GSM 03.40 In this case the TPDU is :
0x01 0x03 0x06 0x91 0x21 0x43 0x65 0x00 0x00 0x04 0xC9 0xE9 0x34 0x0B, which means
regarding GSM 03.40 :
<fo> 0x01 (SMS-SUBMIT, no validity period)
<mr> (TP TP-MR) 0x03 (Message Reference)
<da> (TP TP-DA) 0x06 0x91 0x21 0x43 0x65 (destination address +123456)
<pid> (TP TP-PID) 0x00 (Protocol Identifier)
<dcs> (TP TP-DCS) 0x00 (Data Coding Scheme : 7 bits alphabet)
<length> (TP TP-UDL) 0x04 (User Data Length, 4 characters of text)
TP-UD 0xC9 0xE9 0x34 0x0B (User Data : ISSY)
TPDU in hexadecimal format must be converted into two ASCII characters, e.g. octet
with hexadecimal value 0x2A is presented to the ME as two characters ‘2’ (ASCII 50) and
‘A’ (ASCII 65).
2.4.2.3. New message indication +CNMI
Description :
This command selects the procedure for message reception from the network.
Syntax :
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Defined values :
<mode> : controls the processing of unsolicited result codes
Only <mode>=2 is supported.
Any other value for <mode> (0,1 or 3) is accepted (return code will be OK), but the
processing of unsolicited result codes will be the same as with<mode>=2.
<mode>
0: Buffer unsolicited result codes in the TA. If TA result code buffer is full, indications
can be buffered in some other place or the oldest indications may be discarded and
replaced with the new received indications
1: Discard indication and reject new received message unsolicited result codes when
TA-TE link is reserved. Otherwise forward them directly to the TE
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2: Buffer unsolicited result codes in the TA when TA-TE link is reserved and flush them
to the TE after reservation. Otherwise forward them directly to the TE
3: Forward unsolicited result codes directly to the TE. TA-TE link specific inband used
to embed result codes and data when TA is in on-line data mode
<mt> : sets the result code indication routing for SMS-DELIVERs. Default is 0.
<mt>
0: No SMS-DELIVER indications are routed.
1: SMS-DELIVERs are routed using unsolicited code : +CMTI: “SM”,<index>
2: SMS-DELIVERs (except class 2 messages) are routed using unsolicited code : +CMT
: [<alpha>,] <length> <CR> <LF> <pdu> (PDU mode) or +CMT : <oa>,[<alpha>,]
<scts> [,<tooa>, <fo>, <pid>, <dcs>, <sca>, <tosca>, <length>] <CR><LF><data>
(text mode)
3: Class 3 SMS-DELIVERS are routed directly using code in <mt>=2 ;
Message of other classes result in indication <mt>=1
<bm>: set the rules for storing received CBMs (Cell Broadcast Message) types depend on
its coding scheme, the setting of Select CBM Types (+CSCB command) and <bm>.
Default is 0.
<bm>
0: No CBM indications are routed to the TE. The CBMs are stored.
1: The CBM is stored and an indication of the memory location is routed to the
customer
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application using unsolicited result code: +CBMI: “BM”, <index>
2: New CBMs are routed directly to the TE using unsolicited result code.
+CBM:<length><CR><LF><pdu> (PDU mode) or
+CBM:<sn>,<mid>,<dcs>,<page>,<pages>(Text mode) <CR><LF> <data>
3: Class 3 CBMs : as <bm>=2. Other classes CBMs : as <bm>=1.
<ds> for SMS-STATUS-REPORTs. Default is 0.
<ds>
0: No SMS-STATUS-REPORTs are routed.
1: SMS-STATUS-REPORTs are routed using unsolicited code : +CDS : <length>

<CR> <LF> <pdu> (PDU mode) or +CDS : <fo>,<mr>, [<ra>], [<tora>],
<scts>,<dt>,<st> (Text mode)
2: SMS-STATUS-REPORTs are stored and routed using the unsolicited result code :
+CDSI: “SR”,<index>
<bfr> Default is 0.
<bfr>
0: TA buffer of unsolicited result codes defined within this command is flushed to the
TE when <mode> 1…3 is entered (OK response shall be given before flushing
the codes)
1: TA buffer of unsolicited result codes defined within this command is cleared when
<mode> 1…3 is entered.
2.4.2.4 Read message +CMGR
Description :
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This command allows the application to read stored messages. The messages are read from
the memory selected by +CPMS command.
Syntax :
Command syntax : AT+CMGR=<index>
2.4.2.5 List message +CMGL
Description :
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This command allows the application to read stored messages, by indicating the type
of the message to read. The messages are read from the memory selected by the +CPMS
command.
Syntax :
Command syntax : AT+CMGL=<stat>
Note :
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For SMS Status Reports, only “ALL” / 4 and “READ” / 1 values of the <stat> parameter will
list messages ; other values will only return OK.
2.4.2.6 Send message +CMGS
Description :
The <address> field is the address of the terminal to which the message is sent. To send the
message, simply type, <ctrl-Z> character (ASCII 26). The text can contain all existing
characters except <ctrl-Z> and <ESC> (ASCII 27). This command can be aborted using the
<ESC> character when entering text. In PDU mode, only hexadecimal characters are used
(‘0’…’9’,’A’…’F’).
Syntax :
The message reference, <mr>, which is returned to the application is allocated by the
product. This number begins with 0 and is incremented by one for each outgoing message
(successful and failure cases); it is cyclic on one byte (0 follows 255).
Note:
this number is not a storage number – outgoing messages are not stored.
2.4.2.7 Delete message +CMGD
Description :
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This command is used to delete one or several messages from preferred message storage
(“BM” SMS CB ‘RAM storage’, “SM” SMSPP storage ‘SIM storage’ or “SR” SMS Status-
Report storage).
Syntax :
2. MICROCONTROLLERS USED
AT89S52
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with
8K
bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s
high-density nonvolatile memory technology and is compatible with the industry-standard
80C51 instruction set and pinout. The on-chip Flash allows the program memory to be
reprogrammed in-system or by a conventional nonvolatile memory programmer. By
combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,
the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-
effective solution to many embedded control applications.
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The AT89S52 provides the following standard features: 4K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-
vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock
circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes.The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port,
and interrupt system to continue functioning. The Power-
down mode saves the RAM contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
Fig. Pin Diagram of AT89S52
MICROCONTROLLER AT89S52
4.1.1 Features of AT 89S52

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• Compatible with MCS®-51 Products
• 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 10,000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Fast Programming Time
• Flexible ISP Programming (Byte and Page Mode)
• Green (Pb/Halide-free) Packaging Option
4.1.2 Description
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The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with

8K bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the industry-
standard 80C51 instruction set and pin out. The on-chip Flash allows the program memory to
be reprogrammed in-system or by a conventional nonvolatile memory programmer. By
combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip,
the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-
effective solution to many embedded control applications. The AT89S52 provides the
following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog
timer,two datapointers,three 16-bit Timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the
AT89S52 is designed with static logic for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode stops the CPU while allowing the
RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-
down mode saves the RAM contents but freezes the oscillator, disabling all other chip
functions until the next interrupt or hardware reset.
Vcc
Supply voltage.
Gnd
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can
sink eight TTL Inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data
bus during accesses to external program and data memory. In this mode, P0 has internal pull-
ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during program verification. External pull-ups are required during program verification.
Port 1
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Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. In
addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the
following table. Port 1 also receives the low-order address bytes during Flash programming
and verification.
Port 2
externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memories that use 16-bit addresses (MOVX @ DPTR). In
this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to
external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of
the P2 Special Function Register. Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives
some control signals for Flash programming and verification. Port 3 also serves the functions
of various special features of the AT89S52, as shown in the following table.
29
Table 4.2
RST
Reset input.
A high on this pin for
two machine
cycles while the
oscillator is running
resets the device. This
pin drives high for 98
oscillator periods after
the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to
disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is
enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each access to external data memory. If
desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit
set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external
execution mode.
PSEN
30
Program Store Enable (PSEN) is the read strobe to external program memory. When
the AT89S52 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to
external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH. Note,
however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should
be strapped to VCC for internal program executions. This pin also receives the 12-volt
programming enable voltage (VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
AT89C2051
Features •
Compatible with MCS®-51Products
• 2K Bytes of Reprogrammable Flash Memory – Endurance: 10,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-bit Timer/Counters
31
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-chip Analog Comparator
• Low-power Idle and Power-down Modes
• Green (Pb/Halide-free) Packaging Option
Description
The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer

with 2K bytes of Flash programmable and erasable read-only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit
CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a power-ful microcomputer
which provides a highly-flexible and cost-effective solution to many embedded control
applications. The AT89C2051 provides the following standard features: 2K bytes of Flash,
128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and
clock circuitry. In addition, the AT89C2051 is designed with static logic for opera-tion down
to zero frequency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to
continue functioning. The power-down mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset
Pin Configuration
32
2.1 20-lead PDIP/SOIC 3.
Block Diagram
Description
VCC Supply voltage.
GND Ground.
Port 1 The Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal
pull-ups. P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive
input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog
comparator. The Port 1 out-put buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are
used as inputs and are externally pulled low, they will source current (IIL) because of the
internal pull-ups. Port 1 also receives code data during Flash programming and verification.
4.4 Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-
ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not
accessible as a gen-eral-purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s
are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as
33
inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL)
because of the pull-ups. Port 3 also serves the functions of various special features of the
AT89C2051 as listed below: Port 3 also receives some control signals for Flash
programming and verification.
4.5 RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST
pin high for two machine cycles while the oscillator is running resets the device. Each
machine cycle takes 12 oscillator or clock cycles.
4.6 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock
operating circuit. Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial
output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer
0 external input) P3.5 T1 (timer 1 external input)4 0368H–MICRO–6/08 4.7 XTAL2 Output
from the inverting oscillator amplifier.
SENSORS
This sensors provide no immunity to ambient light hence they are best suited for indoor
applications where there is least interference from external light sources. In an indoor
environment this sensor can give a range of 30 to 50 cms.
While building the sensor, experiment with the distance between the IR LED and
Photodiode. LED emit radiations in a particular angle only, hence the distance between the
IR LED and the Photodiode plays a significant role in the range of the sensor. I got best
results when the LEDs were placed of 0.7-1 cm apart.
The object sensor I built is shown below –
The PCB artwork is shown below. The PCB is single layered as single sided boards are
easier to etch. You can use the artwork to build your own sensor. Just save it to your
computer and print it to scale in high resolution
Debugging
34
The cheapest way to figure out if your IR LED is emitting IR rays is to point a camera at it.
IR radiations come just after visible light in the spectrum and hence we cannot see them. But
most cameras can. IR LEDs heat up quickly which is another sign of a working IR LED, but
parts getting heated up means something else in electronics…
SCHEMATICS - TACTILE BUMP SENSOR CIRCUIT
Tactile Bump Sensors are great for collision detection, but the circuit itself also works fine
for user buttons and switches as well. There are many designs possible for bump switches,
often depending on the design and goals of the robot itself. But the circuit remains the same.
They usually implement a mechanical button to short the circuit, pulling the signal line high
or low. An example is the microswitch with a lever attached to increase its range, as shown
above.
There are several versions below, depending on how you plan to use the circuit and your
available switches. For the resistor use a very high value, such as 40kohms.
Tactile Bump Sensor Circuits
Voltage Voltage
goes high goes low
with contact with contact
More efficient switch for 3 lead switches

(use for microswitches)
35
Bridge Rectifier
When four diodes are connected as shown in figure, the circuit is called as bridge rectifier.
The input to the circuit is applied to the diagonally opposite corners of the network, and the
output is taken from the remaining two corners. Let us assume that the transformer is
working properly and there is a positive potential, at point A and a negative potential at point
B. the positive potential at point A will forward bias D3 and reverse bias D4. The negative
potential at point B will forward bias D1 and reverse D2. At this time D3 and D1 are forward
biased and will allow current flow to pass through them; D4 and D2 are reverse biased and
will block current flow. One advantage of a bridge rectifier over a conventional full-wave
rectifier is that with a given transformer the bridge rectifier produces a voltage output that is
nearly twice that of the conventional full-wave circuit. Assume that the same transformer is
used in both circuits. The peak voltage developed between points X and y is 1000 volts in
both circuits. In the conventional full-wave circuit, the peak voltage from the center tap to
either X or Y is 500 volts. Since only one diode can conduct at any instant, the maximum
voltage that can be rectified at any instant is 500 volts. The maximum voltage that appears
across the load resistor is nearly-but never exceeds-500 v0lts, as result of the small voltage
drop across the diode. In the bridge rectifier shown in view B, the maximum voltage that can
be rectified is the full secondary voltage, which is 1000 volts. Therefore, the peak output
voltage across the load resistor is nearly 1000 volts. With both circuits using the same
36
transformer, the bridge rectifier circuit produces a higher output voltage than the
conventional full-wave rectifier circuit.
FIG: Bridge Rectifier
FIG: Wave Diagram
Voltage Regulators
Voltage regulators comprise a class of widely used ICs. Regulator IC units contain the
circuitry for reference source, comparator amplifier, control device, and overload protection
all in a single IC. IC units provide regulation of either a fixed positive voltage, a fixed
negative voltage, or an adjustably set voltage. The regulators can be selected for operation
with load currents from hundreds of milli amperes to tens of amperes, corresponding to
37
power ratings from milli watts to tens of watts. A fixed three-terminal voltage regulator has
an unregulated dc input voltage, Vi, applied to one input terminal, a regulated dc output
voltage, Vo, from a second terminal, with the third terminal connected to ground. The series
78 regulators provide fixed positive regulated voltages from 5 to 24 volts. Similarly, the
series 79 regulators provide fixed negative regulated voltages from 5 to 24 volts.
REGULATOR:
A discrete voltage regulator fabricated on a single chip, it is called monolithic voltage

regulator. These regulators have:
i. High performance (ideal 100% regulation)

ii. Low cost.
iii. Reduced size.
iv. Easier to use.
Usually monolithic voltage regulator is available as 3 terminals IC7805 as shown in

below figure. The 3 terminals are denoted as IN (input), COM (common), OUT (output).
This +5V regulator is useful in power up to 500mw.It must have a heat sink for high current.
A 1mf high quality and tantalum capacitor should be placed from output to ground for
stability. By using this regulator circuit we are deriving 5v from 12v battery.
38
PCB Fabrication
The fabrication of a PCB includes four steps.
a) Preparing the PCB pattern.

b) Transferring the pattern onto the PCB.
c) Developing the PCB.
d) Finishing (i.e.) drilling, cutting, smoothing, turning etc.
Pattern designing is the primary step in fabricating a PCB. In this step, all
interconnection between the components in the given circuit are converted into PCB tracks.
Several factors such as positioning the diameter of holes, the area that each component would
occupy, the type of end terminal should be considered.Transferring the PCB Pattern
The copper side of the PCB should be thoroughly cleaned with the help of alcoholic
spirit or petrol. It must be completely free from dust and other contaminants.
The mirror image of the pattern must be carbon copied and to the laminate the
complete pattern may now be made each resistant with the help of paint and thin brush.
Developing
In this developing all excessive copper is removed from the board and only the
printed pattern is left behind. About 100ml of tap water should be heated to 75 ° C and 30.5
grams of FeCl3 added to it, the mixture should be thoroughly stirred and a few drops of HCl
may be added to speed up the process.
39
The board with its copper side facing upward should be placed in a flat bottomed
plastic tray and the aqueous solution of FeCl 2 poured in the etching process would take 40
to 60 min to comple
After etching the board it should be washed under running water and then held
against light .the printed pattern should be clearly visible. The paint should be removed with
the help of thinner.
Finishing Touches
After the etching is completed, hole of suitable diameter should be drilled, then the
PCB may be tin plated using an ordinary 35 Watts soldering rod along with the solder core,
the copper side may be given a coat of varnish to prevent oxidation.
Drilling
Drills for PCB use usually come with either a set of collects of various sizes or a 3-
Jaw chuck. For accuracy however 3-jaw chunks aren’t brilliant and small drill below 1 mm
from grooves in the jaws preventing good grips.
Soldering
Begin the construction by soldering the resistors followed by the capacitors and the
LEDs diodes and IC sockets. Don’t try soldering an IC directly unless you trust your skill in
soldering. All components should be soldered as shown in the figure. Now connect the
switch and then solder/screw if on the PCB using multiple washers or spaces. Soldering it
directly will only reduce its height above other components and hamper in its easy fixation in
the cabinet. Now connect the battery lead.
40
Assembling
The circuit can be enclosed in any kind of cabinet. Before fitting the PCB suitable
holes must be drilled in the cabinet for the switch, LED and buzzer. Note that a rotary switch
can be used instead of a slide type.
Switch on the circuit to be desired range. It will automatically start its timing cycles.
To be sure that it is working properly watch the LED flash. The components are selected to
trigger the alarm a few minutes before the set limit.
SOFTWARES USED
Proteus 7.0
Proteus 7.0 is a Virtual System Modelling (VSM) that combines circuit simulation, animated
components and microprocessor models to co-simulate the complete microcontroller based
designs. This is the perfect tool for engineers to test their microcontroller designs before
constructing a physical prototype in real time. This program allows users to interact with the
design using on-screen indicators and/or LED and LCD displays and, if attached to the PC,
switches and buttons. One of the main components of Proteus 7.0 is the Circuit Simulation --
a product that uses a SPICE3f5 analogue simulator kernel combined with an event-driven
digital simulator that allow users to utilize any SPICE model by any manufacturer.
Proteus VSM comes with extensive debugging features, including breakpoints, single
stepping and variable display for a neat design prior to hardware prototyping.
In summary, Proteus 7.0 is the program to use when you want to simulate the interaction
between software running on a microcontroller and any analog or digital electronic device
connected to it.
41
42
DIPTRACE
 PCB Layout — PCB design with an easy-to-use manual routing tools, shape-based
autorouter and auto-placer.
 Schematic — Schematic Capture with multi-level hierarchy and export to PCB Layout,
Spice or Netlist.
 Component and Pattern Editors — allow you to make new parts and footprints.
 Standard Libraries - include 100,000+ parts.
 Import/Export Features - allow you to exchange designs and libraries with other EDA
tools.
43
The Microsoft .NET Framework is a software framework that can be installed on

computers running Microsoft Windows operating systems. It includes a large library of
coded solutions to common programming problems and a virtual machine that manages the
execution of programs written specifically for the framework. The .NET Framework is a
Microsoft offering and is intended to be used by most new applications created for the
Windows platform.
The framework's Base Class Library provides a large range of features including user
interface, data access, database connectivity, cryptography, web application development,
numeric algorithms, and network communications. The class library is used by programmers,
who combine it with their own code to produce applications.
Programs written for the .NET Framework execute in a software environment that
manages the program's runtime requirements. Also part of the .NET Framework, this runtime
environment is known as the Common Language Runtime (CLR). The CLR provides the
appearance of an application virtual machine so that programmers need not consider the
capabilities of the specific CPU that will execute the program. The CLR also provides other
important services such as security, memory management, and exception handling. The class
library and the CLR together constitute the .NET Framework.
Version 3.0 of the .NET Framework is included with Windows Server 2008 and
Windows Vista. The previous stable version of the framework, 3.5, is included with
Windows 7, and can also be installed on Windows XP and the Windows Server 2003 family
of operating systems.[2] Version 4 of the framework was released as a public beta on 20 May
2009.[3] In February 2010, Microsoft released a .NET Framework 4 release candidate.[4] On
April 12, 2010, the final version of the .NET Framework 4 was released.
The .NET Framework family also includes two versions for mobile or embedded
device use. A reduced version of the framework, the .NET Compact Framework, is available
on Windows CE platforms, including Windows Mobile devices such as smartphones.
Additionally, the .NET Micro Framework is targeted at severely resource constrained
devices.
44
WORKING PRINCIPLE
ALGORITHM:
Step 1: Start
Step 2: Read the ID number of the approaching vehicle.
Step 3: Display the date base of vehicle
Step 4: check whether the vehicle is allowed through the check post.
Step 5: If yes then the vehicle can proceed.
Step 6: if no then message is send to the GMS module to cut the ignition.
Step 7: stop
FLOWCHART:
45
ADVANTAGES
 No "line of sight" requirements
 Greater data capacity
 Reduce transaction costs in terms of time and effort
 Simplified self-charging/discharging
 High reliability
46
 High-speed inventorying
 Long tag life
DIADVANTAGES
 High cost
 Vulnerability to compromise
 Removal of exposed tags
CONCLUSION
47

RFID and GSM Based Vehicle Number Plate Recognition

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RFID and GSM Based Vehicle Number Plate Recognition

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RFID and GSM based Number Plate Recognition And Ignition Cut off

GSM is a cellular network, which means that mobile phones connect to it by

Block Diagram Description:

How do RFIDs work.

A basic RFID system consist of three components:

• A transceiver (with decoder)

• A transponder (RF tag) electronically programmed with unique information

An RFID tag is comprised of a microchip containing identifying information and an antenna

• Bi-color LED for visual indication of activity

Each transponder tag contains a unique identifier (one of 240, or

"Read-only" versus "read-write"

Passive versus active

Like all wireless communications, there are a variety of frequencies or spectra

Pin Pin Name Type Function

The GSM Network

2.2 GSM Architecture

Operation Data Terminal

Mobile Radio Network sub-system PSTN

Figure 2.2 GSM Architecture

2.3 GSM Protocol Stack

Figure 1.3 GSM Protocol Stack

2.3.1 Protocols on the Um interface

• Layer 1: Physical layer.

- Radio Resource Management (RR) : The role of the RR management layer is to

- Mobility Management (MM) : Mobility Management handles the control functions

- Connection Management (CM) : Connection Management is used to setup, maintain

- Call Control(CC) :- Manages call connections.

2.4 General behaviors

2.4.1 SIM Insertion, SIM Removal

2.4.2 Attention (AT) Commands

GSM modem can be controlled by standard set of AT (Attention) commands. These

2.4.2.1 Select message service +CSMS

1: SMS AT commands are compatible with GSM 07.05 Phase 2 + version .

2.4.2.2 Preferred Message Format +CMGF

Example, sending an SMS Message in PDU mode

The <pdu> message is composed of the SC address (« 00 means no SC address given,

<fo> 0x01 (SMS-SUBMIT, no validity period)

<mr> (TP TP-MR) 0x03 (Message Reference)

<pid> (TP TP-PID) 0x00 (Protocol Identifier)

<dcs> (TP TP-DCS) 0x00 (Data Coding Scheme : 7 bits alphabet)

<length> (TP TP-UDL) 0x04 (User Data Length, 4 characters of text)

TP-UD 0xC9 0xE9 0x34 0x0B (User Data : ISSY)

2.4.2.3. New message indication +CNMI

<mode> : controls the processing of unsolicited result codes

Only <mode>=2 is supported.

0: No SMS-DELIVER indications are routed.

1: SMS-DELIVERs are routed using unsolicited code : +CMTI: “SM”,<index>

3: Class 3 SMS-DELIVERS are routed directly using code in <mt>=2 ;

Message of other classes result in indication <mt>=1

application using unsolicited result code: +CBMI: “BM”, <index>

+CBM:<length><CR><LF><pdu> (PDU mode) or

+CBM:<sn>,<mid>,<dcs>,<page>,<pages>(Text mode) <CR><LF> <data>

3: Class 3 CBMs : as <bm>=2. Other classes CBMs : as <bm>=1.

<ds> for SMS-STATUS-REPORTs. Default is 0.

0: No SMS-STATUS-REPORTs are routed.

1: SMS-STATUS-REPORTs are routed using unsolicited code : +CDS : <length>

2.4.2.4 Read message +CMGR

Command syntax : AT+CMGR=<index>

2.4.2.5 List message +CMGL

Command syntax : AT+CMGL=<stat>

2.4.2.6 Send message +CMGS

2.4.2.7 Delete message +CMGD