CMOS Inverter Layout

Click the LH mouse button to begin the animation

Input Output
Vdd

well tap

n-well

substrate
tap
Vss
 CMOS Inverter Structure
Input Output
Vdd
p+
metal
well tap n-well

polysilicon p+
n-well
p-substrate
polysilicon
n+
gate oxide
substrate n+
tap
field oxide
Vss
 CMOS Inverter Structure
Input Output
Vdd
p+
metal
well tap n-well

polysilicon p+
n-well
p-substrate
polysilicon
n+
gate oxide
substrate n+
tap
field oxide
Vss
Polysilicon Design Rule
Click the LH mouse button to begin the animation
 Polysilicon Design Rule
Input Output

No overlap of channel. Insufficient overlap of cut.

 Polysilicon Design Rule
Input Output

Faulty m1-p
connection

Current not Current not

controlled controlled
by gate by gate
 Polysilicon Design Rule
Input Output

Adequate overlap of channel. Sufficient overlap of cut.

Polysilicon Design Rule
Input Output