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Input Output
Vdd
well tap
n-well
substrate
tap
Vss
CMOS Inverter Structure
Input Output
Vdd
p+
metal
well tap n-well
polysilicon p+
n-well
p-substrate
polysilicon
n+
gate oxide
substrate n+
tap
field oxide
Vss
CMOS Inverter Structure
Input Output
Vdd
p+
metal
well tap n-well
polysilicon p+
n-well
p-substrate
polysilicon
n+
gate oxide
substrate n+
tap
field oxide
Vss
Polysilicon Design Rule
Click the LH mouse button to begin the animation
Polysilicon Design Rule
Input Output
Faulty m1-p
connection