EXPERIMENT-3

AIM: To study the following characteristics of an nmos transistor.

 Variations of drain current ID with VGS and VDS.
 Variation of transconductance gm with ID, VGS and VGS-VTH, W/L .
 Channel length modulation parameter λ vs VDS.
 Effect of body bias and sub threshold conduction with VGS.

SOFTWARE REQUIRED: Cadence Virtuoso 6.1.7 – 64b.

THEORY:
N-type metal-oxide-semiconductor logic uses n-type field-effect transistors (MOSFETs) to
implement logic gates and other digital circuits. These nMOS transistors operate by creating
an inversion layer in a p-type transistor body. This inversion layer, called the n-channel, can
conduct electrons between n-type "source" and "drain" terminals.

BODY EFFECT: To understand the body effect let source and drain voltage be 0. The gate
voltage is less than VTH. Now if the body is connected to some negative voltage then more
holes are attracted towards the bottom and the depletion region width may increase further
leading to increase in threshold voltage VTH. This is called as body effect or Back gate effect.

CHANNEL LENGTH MODULATION: The actual length of the inverted channel gradually
decreases as the potential difference between the gate and the drain increases. In other words
L’ is a function of VDS. This effect is called as channel length modulation. Lambda is called
as the channel length modulation coefficient. The parameter represents the relative variation
in length for a given increment in VDS.

SUBTHRESHOLD CONDUCTION: In the analysis of MOSFET we have assumed that the

device terms of abruptly as VGS drops below VTH. In reality for VGS approximately equal to
VTH a weak inversion layer still exists and some current flows from drain to source. Even for
VGS less than VTH, Id is finite but it exhibits and exponential dependence on VGS called as sub
threshold conduction.

TRANSCONDUCTANCE: In processing signals we deal with the changes in voltages and

currents we define the figure of merit as the change in the drain current divided by change in
the gate source voltage. This is called as Transconductance. It represents the sensitivity of the
device. For a high gm a small change in VGS results in the large change in ID.
SCHEMATIC DIAGRAM:

ID vs VGS (AT CONSTANT VDS):

ID vs VGS (AT DIFFERENT VDS):

ID vs VGS (AT DIFFERENT W):

ID vs VDS (AT CONSTANT VGS):

ID vs VDS (AT DIFFERENT VGS):

gm vs VGS-VTH :

gm vs ID :
gm/ID vs ID :

gm vs W/L :
CHANNEL LENGTH MODULATION:

SUBTHRESHOLD CONDUCTION:
BODY BIAS SCHEMATIC:

BODY BIAS:
PRECAUTIONS:
1. Whenever any modification is done to the schematic, it must be checked and saved.
2. All the model library files must be added before performing the simulation.
3. Directions of input and output ports must be taken care.
4. To perform the parametric analysis the design variables must not be a fixed value.

RESULT: