5 4 3 2 1

SLP_S3#(SUSB#): 4 39
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components NBSWON#
when system transitions to S3, S4, or S5 states. 5 +5VPCU +5V_S5
SLP_S4#(SUSC#): MOS
S5_ON PQ33
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components 6
when system transitions to S4 or S5 state. (S5D)
2 +3VPCU +3V_S5
1 MOS
AC Adapter +3VPCU PQ12
Always System power
BATT Charger VIN
D Regulator 7 D

PU2 +5VPCU
Battery EC_RSMRST#
PU2 RSMRST#
10 8
3
DNBSWON#
SUSON(SUSD) PWRBTN#

13 SUSC# 9
SLP_S4#
MAINON(MAIND)
EC SUSB#
14 SLP_S3#
MAIND +3VPCU/+5VPCU +3V
MOS +5V 22
23 PCH
ECPWROK
TPT_PWROK
PWRGD
MAIND +1.5VSUS
+1.5V
MOS
100ms
C
MAINON C

+RC VIN 15
+1.05V
VR

HWPG_1.05V VRM_PWRGOOD

16
CPU_PG PLTRST#

VIN +VCC_CORE
17
Regulator VCCGFX
PU8
HWPG_SYS
+3.3V_PRIME_ON IMVP_PWRGD/ HWPG_VCCGFX 18
(From EC)
19a 21
+3V 19b HWPG CK505 24 25
+3V_PRIME
MOS EN
PQ9 H_PWRGD PLTRST_N
B B
20 HWPG_1.8V D
+3VSUS
MOS MAINON_ON_G NMOS
+1.8V HWPG_1.5V G
PU7 S
D
GND
NMOS MAINON_ON_G 12
G For Power Down Sequence PWRGD RESET_L
S For Power Down Sequence
DDR3_VCCA_PWROK
GND
MAINON +0.75V_DDR_VTT
VIN
CPU
SUSON Regulator +SMDDR_VREF
+1.5VSUS
PU5 DDR3_DRAM_PWROK
11
+3VPCU
SUSD MOS +3VSUS
PQ22
A A

Quanta Computer Inc.

PROJECT : ZE7
Size Document Number Rev
power sequence block diagram 1B

Date: Wednesday, November 02, 2011 Sheet 39 of 40

5 4 3 2 1