Introduction To VLSI Design PYQs-2022

1. Answer any seven of the following as directed:

1. (a) What is depletion mode device?

Ans. A MOSFET that normally turns ON without applying any gate voltage when you connect is known as a
depletion mode MOSFET. In this MOSFET, the flow of current is from the drain terminal to the source. This type
of MOSFET is also known as normally on the device.

• Once a voltage is applied at the gate terminal of the MOSFET, the drain to the source channel will become
more resistive. When the gate-source voltage enhances more the flow of current from the drain to the source
will reduce until the flow of current from the drain to the source stops.
Depletion Mode MOSFET Symbol

The depletion mode MOSFET symbols for p-channel and

n-channel are shown below. In these MOSFETs, the arrow
symbols represent the type of MOSFET like P-type or N-
type. If the arrow symbol is inside direction then it is n-
channel and if the arrow symbol is outside, then it is p-
channel.
 1. (b) What is body effect?

Ans. The transistor will experience the body effect if the voltage difference between the source and the body
is greater than zero. Whenever there is a voltage (potential) difference between the source and substrate
(body), this leads to an increase or decrease in the threshold voltage of the transistor. This is called a “Body
effect.”

Now to understand the Body effect, let's take three cases, here we are taking NMOS into the p substrate, the p
substrate has a majority of carrier holes.
 Case 1: Negative Body voltage

• In NMOS let's assume that the Gate voltage Vg is 2V and the Base terminal is tied with the negative
terminal, so in this case, As Vb becomes more negative, more holes are attracted to the substrate
connection, and leaving a larger negative charge behind, so the depletion region becomes wider as
compare to normal.

• Now we know that threshold voltage is a function of the total charge in the depletion region. Now to invert
this wide depletion region, we need less threshold voltage(Vt), so due to this threshold voltage will
decrease. This phenomenon is called the "body effect" or the "back-gate effect."

“The threshold voltage decreases with a negative bulk voltage of NMOS”

 Case 2: Zero Body voltage (no Body effect)

• In NMOS let's assume that the Gate voltage Vg is 2V and the Base terminal is tied with zero. Now as the
source and body terminal are tied with zero, no effect will create by the body, so the depletion region
becomes normal.

• So, due to this threshold voltage will be normal. This phenomenon we can say that there is no body effect
when Source and Bulk are tied to zero terminal.

"The threshold voltage is normal with zero bulk voltage of NMOS"

 Case 3: Positive Body voltage

• In NMOS let's assume that the Gate voltage Vg is 2V and the Base terminal is tied with the positive
terminal, so in this case, As Vb becomes more positive, more electrons are attracted to the substrate
connection, and leaving a larger positive charge behind, so the depletion region becomes narrow as
compared to normal.

• Now to form a channel, we need more voltage to the gate, so due to this threshold voltage will
increase.

"The threshold voltage is increased with a positive bulk voltage of NMOS"

How to reduce body effect

• Provide a Strong Bulk connection

• Good Ohmic contact with the body
• Maintain Source and Body (bulk) terminal as the same potential
1. (c) What is the cause of storage time in a bipolar transistor?

Ans. It is usually defined as when the collector current falls from ICS to 0.9 ICS and collector-emitter voltage
VCE rises from VCE to 0.1 VCC.

• At saturation, the collector-to-emitter voltage is the minimum drop possible occurring due to the non-zero
internal resistance of the BJT. Since it cannot decrease further, the current IC cannot increase further. The
BJT is said to be saturated. However, the base current, IB, can keep increasing with the input voltage and
hence, in saturation, the relation IC = βIB is not satisfied. In the saturation region, βIB > IC is the correct
relation.

• Bipolar transistors, and particularly power transistors, have long base-storage times when they are driven
into saturation. The saturation storage time can slow the overall switching time significantly.
Example: For the graph which depicts collector current, find the
ON time.

Ans. On time is the time taken by BJT to change from the OFF
state to the ON state. It is the sum of the delay time and the rise
time. Rise time is the time taken by current to increase from 10%
to 90% of saturation and delay time is time taken by current to
increase from 0 to 10% of the saturation.

ton = td + tr = t2 – t1 + t3 – t2 = 2 – 1 + 4 – 2 = 3ms.

Example: Find the storage time for the current variation.

Ans. Storage time is the time taken by IC to decrease from ICsat to

90% of ICsat.

TS = t5 – t4 = 16 - 6 = 10ms.
1. (d) What is meant by the fan-out of a logic gate?

Ans. The fan-out is defined as the maximum number of inputs (load) that
can be connected to the output of a gate without degrading the normal
operation.

• Fan Out is calculated from the amount of current available in the output
of a gate and the amount of current needed in each input of the
connecting gate.

• Suppose the current sourcing capability of a NAND gate is IOH when the
output of it is in logic high and the inputs of the logic gates which are fed
from the output of this logic gate is IIH.

• Now the maximum number of inputs which this output of the logic gate
will be able to drive is IOH/ IIH. This will be applicable when the when
that output will be in high state.
• Now considering the case when the output is in the state of logic LOW
then the let us take the maximum current sinking capability as IOL. And
then again just as the previous one the sinking current which is fed to all
the connected inputs of various logic gates is IIL.

• For this case the maximum number of input drives which will be driven
by the output of that logic gate will be equal to IOL / IIL.

• So we have found that the maximum number of logic gate inputs that can
be fed from the output of a single logic gate will be IOH / IIH when the
logic is high and it will be IOL / IIL when the logic is in low state.

• So the number of logic gate inputs which can be driven from the output
of a single logic gate is termed as Fan Out of Logic Gates.
1. (e) Charge moves from _______ to _______when V DS is applied. (Fill in the blanks)

Ans. When a drain-source bias, VDS is applied to a NMOS device in the threshold conducting state, electrons
move in the channel inversion layer from source to drain.

• As VDS increases, the inversion-layer charge density at the drain end of the channel is reduced; therefore, ID
does not increase linearly with VDS.

• When VDS reaches VGS − VT, the channel is “pinched off” at the drain end, and ID saturates (i.e. it does not
increase with further increases in VDS).
1. (f) What is sheet resistance?

Ans. Sheet resistance, is the resistance of a square piece of a thin

material with contacts made to two opposite sides of the square. It
is usually a measurement of electrical resistance of thin films that
are uniform in thickness.
• It is commonly used to characterize materials made by semiconductor doping, metal deposition, resistive paste
printing, and glass coating. Examples of these processes are: doped semiconductor regions.

• Mathematically, we can derive sheet resistance as,

• It is convenient to use Sheet resistance instead of resistivity because Resistivity and thickness are
characteristics which cannot be controlled by the circuit designer, and it is expressed as the single sheet
resistance parameter.

“Is sheet resistance an “inherent” property of a material, or is it a function of thickness?”

Resistivity is the inherent property of the material which gives it electrical resistance. It is sometimes called
Specific Resistance. Sheet resistance is the resistance of a thin sheet of material which when multiplied by the
thickness (in cm) gives the value of resistivity.
1. (g) What is a dynamic logic?

Ans. Dynamic circuit class, which relies on temporary storage of signal values on
the capacitance of high impedance circuit nodes. The Dynamic logic is presented
that obtains a similar result, while avoiding static power consumption.

• With the addition of a clock input, it uses a sequence of precharge and

conditional evaluation phases. The basic construction of an (n-type) dynamic
logic gate is shown in Figure.

• The PDN (pull-down network) is constructed exactly as in complementary

CMOS. The operation of this circuit is divided into two major phases: precharge
and evaluation, with the mode of operation determined by the clock signal CLK.
Precharge:

• When CLK = 0, the output node Out is precharged to VDD by the PMOS
transistor Mp. During that time, the NMOS transistor Me is off, so that the pull-
down path is disabled. The FET Me, eliminates any static power that would be
consumed during the precharge period.

Evaluation:

• For CLK = 1, the precharge transistor Mp is off, and the evaluation transistor Me
is turned on. The output is conditionally discharged based on the input values and
the pull-down topology. If the inputs are such that the PDN conducts, then a low
resistance path exists between Out and GND and the output is discharged to
GND.
1. (h) List different timings used in a memory cell.

Ans. This is a measurement reflective of how quickly the memory can be ready for a new set of commands. New
memory types, like DDR4, have significantly faster Clock Cycle Times than older memory.

Timings are most commonly broken down to the four values: CAS Latency (CL), Row Column Delay (tRCD),
Row Precharge Time (tRP), and Row Active Time (tRAS).

• CL : This is the time it takes for a memory module to have data ready upon request of the memory controller.
• tRCD : The time it takes to read memory after the memory is ready.
• tRP : The time it takes for memory to have a new row ready for using data.
• tRAS : Minimum time required for a row to be active to ensure data can be accessed from it.
1. (i) What do you understand by propagation delay?

Ans.

Propagation delay is the time it takes for the input to reach the output. Propagation delay in VLSI is normally
described as the time difference between when the transitional input reaches 50% of its final value and when
the output reaches 50% of its final value.

• It is represented by the symbol ‘tpd’. It is also known as gate delay. Modern integrated circuits can
contain billions of gates and operate at extraordinary speeds. Inconsistent propagation delay in an
integrated circuit can result in data mistakes on the chip.

• As a result, propagation delay is a significant consideration in high-speed circuit design and a limiting
factor in the processing speed, or frequency (in hertz), that a processor can operate at.
The propagation delay of a logic gate is not constant and is determined by two factors:

1. Input transition time causes output transition:

The longer the transition time at the input, the longer the cell’s propagation delay. Signals should transition
quicker to reduce propagation delays.

2. Output load of the logic gate:

The greater the capacitive load at the cell’s output, the greater the effort (time required) to charge it. As a
result, the propagation increases.
1. (j) What is meant by logical effort?

The method of logical effort is an easy way to estimate delay in a CMOS circuit. The method also specifies the
proper number of logic stages on a path and the best transistor sizes for the logic gates.

• The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the
logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of
the gate.

• Thus a NAND gate has more delay than an inverter with similar transistor sizes that drives the same load. The
method of logical effort quantifies these effects to simplify delay analysis for individual logic gates and
multistage logic networks.
• The first step in modeling delays is to isolate the effects of a particular integrated circuit fabrication
process by expressing all delays in terms of a basic delay unit τ particular to that process. τ is the delay
of an inverter driving an identical inverter with no parasitics.

• Thus we express absolute delay as the product of a unitless delay of the gate d and the delay unit that
characterizes a given process:
dabs = dτ

• The delay incurred by a logic gate is comprised of two components, a fixed part called the parasitic
delay p and a part that is proportional to the load on the gate’s output, called the effort delay or stage
effort f . (Appendix A lists all of the notation used in this book.)The total delay, measured in units of τ,
is the sum of the effort and parasitic delays:
d=f+p
• The effort delay depends on the load and on properties of the logic gate driving the load. We introduce
two related terms for these effects: the logical effort g captures properties of the logic gate, while the
electrical effort h characterizes the load. The effort delay of the logic gate is the product of these two
factors:
f = gh

• The logical effort g captures the effect of the logic gate’s topology on its ability to produce output current.
It is independent of the size of the transistors in the circuit.

• The electrical effort h describes how the electrical environment of the logic gate affects performance and
how the size of the transistors in the gate determines its load-driving capability. The electrical effort is
defined by:

where Cout is the capacitance that loads the output of the logic gate and
Cin is the capacitance presented by the input terminal of the logic gate.
• Electrical effort is also called fanout by many cmos designers. Note that fanout, in this context, depends on
the load capacitance, not just the number of gates being driven. Combining equations, we obtain the basic
equation that models the delay through a single logic gate, in units of τ :
d = gh + p

• This equation shows that logical effort g and electrical effort h both contribute to delay in the same way.
This formulation separates τ , g, h, and p, the four contributions to delay.

• The process parameter τ represents the speed of the basic transistors. The parasitic delay p expresses the
intrinsic delay of the gate due to its own internal capacitance, which is largely independent of the size of
the transistors in the logic gate.

• The electrical effort, h, combines the effects of external load, which establishes Cout, with
the sizes of the transistors in the logic gate, which establish Cin. The logical effort g
expresses the effects of circuit topology on the delay free of considerations of loading or
transistor size. Logical effort is useful because it depends only on circuit topology.
• Reduced output current means slower operation, and thus the logical effort number for a logic gate tells
how much more slowly it will drive a load than would an inverter. Equivalently, logical effort is how
much more input capacitance a gate must present in order to deliver the same output current as an
inverter.

• More complex logic functions have larger logical effort. Moreover, the logical effort of most logic gates
grows with the number of inputs to the gate. Larger or more complex logic gates will thus exhibit
greater delay.
• The parasitic delay of a logic gate is fixed, independent of the size of the logic gate and of the load
capacitance it drives, because wider transistors providing greater output current have correspondingly
greater diffusion capacitance.

• This delay is a form of overhead that accompanies any gate. The principal contribution to parasitic delay is
the capacitance of the source or drain regions of the transistors that drive the gate’s output. note that
parasitic delays are given as multiples of the parasitic delay of an inverter, denoted as pinv. A typical value
for pinv is 1.0 delay units.
Example : Estimate the delay of a fanout-of-4 (FO4) inverter, as shown in
Figure.

Solution : Because each inverter is identical,

Cout = 4Cin,
h=4
The logical effort g = 1 for an inverter. Thus the FO4 delay, according to
equation, is
d = gh + p = 1 × 4 + pinv
=4+1=5

It is sometimes convenient to express times in terms of FO4

inverter delays because most designers know the FO4 delay in
their process and can use it to estimate the absolute
performance of your circuit in their process.
• The graph shows that we can adjust the total delay by adjusting the electrical effort or by choosing a logic
gate with a different logical effort.
Introduction To VLSI Design PYQs-2022
2. (a) Explain why the drain current keeps on increasing even after the VDsat voltage whereas it should
have been fixed for an ideal MOS transistor.

Ans. An increase in VDS does not increase IDS because the channel is pinched-off. For a MOSFET operating in
the saturation region, the effective channel length is reduced as the inversion layer near the drain vanishes, while
the channel-end voltage remains essentially constant and equal to VDSAT.

• Note that the pinched-off (depleted) section of the channel absorbs most of the excess voltage drop (VDS -
VDSAT) and a high-field region forms between the channel-end and the drain boundary.

• Electrons arriving from the source to the channel-end are injected into the drain-depletion region and are
accelerated toward the drain in this high electric field, usually reaching the drift velocity limit.

• The pinch-off event, or the disruption of the continuous channel under high drain bias, characterizes the
saturation mode operation of the MOSFET.
• Thus, the drain current ID becomes a function only of the gate-to-
source voltage VGS, beyond the saturation boundary.

• Note that this constant saturation current approximation is not very

accurate in reality, and that the saturation-region drain current
continues to have a certain dependence on the drain voltage.

• The parabolic boundary between the linear and the saturation regions
is indicated here by the dashed line.

• The current-voltage characteristics of the MOS transistor can also be

visualized by plotting the drain current as a function of the gate
voltage, as shown in Figure.

• This ID-VGS transfer characteristic in saturation mode (VDS > VDSAT)

provides a simple view of the drain current increasing as a second-
order function of the gate-to source voltage. The current is obviously
equal to zero for any gate voltage smaller than the threshold voltage
VT0.
2. (b) What is the physical origin of latch-up problem in CMOS? How can the latch-up problem be prevented?

Ans. Latch-up occurs as a result of triggering a parasitic device just like an SCR
(silicon controlled rectifier), a four-layer pnpn device formed by at least one pnp and
at least one npn transistor connected. Latch-Up is a condition where a low impedance
path is created between a supply pin and ground.

• An SCR is a normally off device in a "blocking state", in which negligible current

flows. Its behavior is similar to that of a forward-biased diode, but conducts from
anode, A, to cathode, K, only if a control signal is applied to the gate, G.
• In its normally off state, the SCR presents a high impedance path between supplies. When
triggered into its conducting state as a result of excitation applied to the gate, the SCR is said
to be "latched".

• It enters this state as a result of current from the gate injected into the base of Q2, which
causes current flow in the base-emitter junction of Q1. Q1 turns on causing further current to
be injected into base of Q2. This positive-feedback condition ensures that both transistors
saturate; and the current flowing through each transistor ensures that the other remains in
saturation.
• When thus latched, and no longer dependent on the trigger source applied to the gate
(G), a continual low-impedance path exists between anode and cathode.

• Since the triggering source does need not be constant, it could simply be a spike or a
glitch; removing it will not turn off the SCR. As long as the current through the SCR is
sufficiently large, it will remain in its latched state.

• If, however, the current can be reduced to a point where it falls below a holding-current
value, IH, the SCR switches off.
In CMOS, one PMOS and one NMOS; these could be connected together as an inverter or as the switch channel.
The parasitic transistors responsible for latch-up behavior, Q1 (vertical PNP) and Q2 (lateral NPN) are also shown.
Prevention Techniques for Latch-Up in VLSI:

• Chips can be designed to be latch-up resistant by including an insulating oxide layer (called a trench) that
covers both the NMOS and PMOS transistors. The parasitic silicon-controlled rectifier (SCR) structure
between these transistors is therefore broken.

• Devices made from lightly doped epitaxial layers grown on heavily doped substrates are less prone to latch
up. The heavily doped layer serves as a current sink, allowing surplus minority carriers to recombine fast.

• Most silicon-on-insulator devices are latch-up resistant by design. The latch-up connection is a low-
resistance connection between the tub and the power supply rails.

• To avoid the latch, each transistor has its own tap connection.
3. (a) Explain the method of threshold voltage extraction from the current-voltage characteristics of MOSFET.

Ans. There are two popular methods for extracting the threshold voltage (Vth). Depending on the device and
application, these methods offer varying degrees of precision and relevance.

a. Linear Extrapolation Method (ELR)

• The linear extrapolation method (ELR) determines Vth by locating the gate voltage (Vg) axis intercept of the
linear extrapolation of the drain current (Id) –Vg curve at its point of maximum transconductance (gm).

• The value of Vth is calculated by subtracting Vd/2 to Vg intercept point to minimize the effect of different
values of drain voltage (Vd). As shown in Figure 1, there are four key steps:
i. Find gm_peak
ii. Calculate Id_appx based on Id at gm_peak
iii. Find Vcross based on Id_appx
iv. Substract Vcross by Vd/2 to get the value of Vth

However, the ELR method has certain limitations.

Mobility degradation effects and the impact of
significant source and drain series parasitic
resistances can skew the Id-Vg curve, thereby
rendering the extracted threshold voltage value
imprecise.
b. Constant Current Method (CC)

• The constant-current method (CC) evaluates the threshold

voltage as the value of the gate voltage, Vg, corresponding
to a given arbitrary constant drain current (Id). Usually,
drain voltage (Vd) is less than 100mV to bias the transistor
at a linear region. Both source and body nodes are
connected to the ground.

• Id is equal to (Wm/Lm) * Icon, where Wm and Lm are the

mask channel width and length respectively. Icon is an
arbitrary value. While a typical value of Icon is 1e-7, it may
be different for different process nodes.

• Despite the simplicity of the CC method, the outcome

heavily depends on the assigned drain current value Icon.
This selection can introduce significant variations in the
extracted threshold voltage.
3. (b) Consider a MOS system with the following parameters:

Gate oxide thickness (tox)=200 Å

Gate to substrate contact potential (ɸGC)=0.85 V
Substrate doping (NA)=2×1015 cm−3
Trapped oxide charge (Qm) = 𝑞2 x 1011 C/cm²
Determine the threshold voltage VT0 under zero bias at room temperature (T=300 K).
Given Ɛox = 3.97 Ɛ0 and Esi = 11.7 Ɛ0

Ans.
4. (a) What do you understand by constant voltage scaling? What is the effect of constant field scaling on (i) power
dissipation and (ii) delay time?

Ans. In constant field scaling, power dissipation decreases by S, while in constant voltage scaling, drain current
increases by S. Hence, constant field scaling can be used in low power applications, while constant voltage
scaling can be used in high switching speed applications.
• The major disadvantage of low power design through voltage scaling is the increased propagation delay in
logic circuits. Power dissipation and propagation delay are inversely related because of the
nonlinear capacitance present in MOSFETs.

• By increasing the supply and substrate bias voltages, the applied capacitance increases, decreasing the
switching time between logic states. However, this also allows more current to flow during switching as the
MOSFET capacitances charge up, which increases the average current during a given clock cycle.
4. (b) Explain the method of channel length modulation parameter extraction from the current-voltage
characteristics of MOSFET.

Ans. Analysis of MOSFET circuits is based on three possible operating modes: cutoff, triode or linear, and
saturation. In cutoff, the gate-to-source voltage is not greater than the threshold voltage, and the MOSFET
is inactive.

• In triode, the gate-to-source voltage is high enough to allow current flow from drain to source, and the
nature of the induced channel is such that the magnitude of the drain current is influenced by the gate-
to-source voltage and the drain-to-source voltage.
• As the drain-to-source voltage increases, the triode region
transitions to the saturation region, in which drain current is
(ideally) independent of drain-to-source voltage and thus
influenced only by the physical characteristics of the FET and the
gate-to-source voltage.

• The saturation-region relationship between gate-to-source

voltage (VGS) and drain current (ID) is expressed as follows:
• Unfortunately, the “pinching off” isn’t the end of the influence exerted by the drain-to-source voltage.
Further increases continue to affect the channel because the pinch-off point moves closer to the source.

• The resistance of the channel is inversely proportional to its width-to-length ratio; reducing the length
leads to decreased resistance and hence higher current flow. Thus, channel-length modulation means that
the saturation-region drain current will increase slightly as the drain-to-source voltage increases.

• So we need to modify the saturation-region drain-current expression to account for channel-length

modulation. We do this by incorporating the incremental channel-length reduction into the original
expression:
• By assuming that the incremental change is much less than the length of the physical channel (i.e., the
distance between the source and drain regions), we can rearrange this as follows:

• Now we just need to come up with a parameter that accounts for how a certain semiconductor process
technology responds to changes in the drain-to-source voltage. How about we call this parameter lambda
(λ), such that

• This brings us to our channel-length-modulation-compliant expression for saturation-region drain current:

You might also see the following variant:

Note that the above expression incorporates the assumption that ΔL is much less than L.
5. (a) Define VIL VIH, VOH and VOL voltage levels in the voltage transfer characteristics of an inverter. Show
that the VIL for a CMOS inverter is given by

Ans. Noise margin is the amount of noise that a CMOS circuit could withstand
without compromising the operation of circuit. Noise margin does makes sure
that any signal which is logic ‘1’ with finite noise added to it, is still
recognized as logic ‘1’ and not logic ‘0’. It is basically the difference between
signal value and the noise value.

• For very low input voltage levels, the output voltage V is equal to the high
value of VOH (output high voltage).

• In this case, the driver nMOS transistor is in cut-off, and hence, does not
conduct any current. Consequently, the voltage drop across the load device
is very small in magnitude, and the output voltage level is high.
• As the input voltage V increases, the transistor starts conducting a
certain drain current, and the output voltage eventually starts to
decrease.

• Notice that this drop in the output voltage level does not occur
abruptly, such as the vertical drop assumed for the ideal inverter
VTC, but rather gradually and with a finite slope.

• We identify two critical voltage points on this curve, where the

slope of the Vt(Vin) characteristic becomes equal to -1, i.e.,
• The smaller input voltage value satisfying this condition is called the input low voltage VIL and the larger
input voltage satisfying this condition is called the input high voltage VIH.

• Both of these voltages play significant roles in determining the noise margins of the inverter circuit. As the
input voltage is further increased, the output voltage continues to drop and reaches a value of VOL (output
low voltage) when the input voltage is equal to VOH.

• The inverter threshold voltage Vt., which is considered as the transition voltage, is defined as the point where
Vin = Vout., on the VTC.

• Thus, a total of five critical voltages, VOL, VOH, VIL, VIH, and Vth, characterize the DC input-output
voltage behavior of the inverter circuit.
VOH : Maximum output voltage when the output level is logic " 1“
VOL : Minimum output voltage when the output level is logic "0“
VIL : Maximum input voltage which can be interpreted as logic "0“
VIH : Minimum input voltage which can be interpreted as logic " 1“

• According to the definitions above, any input voltage level between

the lowest available voltage in the system (usually the ground
potential) and V1L is interpreted as a logic "0" input, while any
input voltage level between the highest available voltage in the
system (usually the power supply voltage) and VIH is interpreted as
a logic " 1 " input.

• Any output voltage level between the lowest available voltage in

the system and VOL is interpreted as a logic "0" output, while any
output voltage level between the highest available voltage in the
system and VOH is interpreted as a logic " 1 "output.
• These observations lead us to the definition of noise tolerances
for digital circuits, called noise margins and denoted by NM.

• The noise immunity of the circuit increases with NM. Two noise
margins will be defined: the noise margin for low signal levels
(NML) and the noise margin for high signal levels (NMH).

• Fig shows a graphical illustration of the noise margins. Here, the shaded
areas indicate the valid regions of the input and output voltages, and the
noise margins are shown as the amount of variation in the signal levels that
can be allowed while the signal is transmitted from the output of one gate
to the input of the next gate.
Hence, if input voltage (Vin) lies somewhere between VOL and VIL, it would be
detected as logic ‘0’, and would result in an output which is acceptable.

Similarly, if input voltage (Vin) lies between VIH and VOH, it would be detected
as logic ‘1’ and would result in an output which is acceptable.
In a CMOS inverter operating in steady-state, the drain current of the nMOS transistor is always equal to the
drain current of the pMOS transistor, according to KCL. MOS Inverters: IDn = IDp

CMOS inverter static characteristics, by calculating the critical voltage points on the VTC. It has already
been established that VOn = VDD and VOL = 0 for this inverter.

(i) Calculation of VIL

By definition, the slope of the VTC is equal to (-1), i.e., dV0/dVin = -1 when the input voltage is V = VIL.
Note that in this case, the nMOS transistor operates in saturation while the pMOS transistor operates in the
linear region. From IDn= ID p we obtain the following current equation:
5. (b) Consider a CMOS inverter with the following device parameters:

nMOS: VTo,n = 0.6 V μn Cox = 60μA / 𝑽𝟐

pMOS: VT0,p = - 0.8 V μp Cox = 20μA / 𝑽𝟐

Determine the (W/L) ratios of the nMOS and pMOS transistor such that the switching threshold (Vth) is 1.5 V.
Given: VDD = 3 V, λ= 0.
 6. What is a transmission gate (TG)? Design a circuit for 2-input TG based XOR gate.

Ans. The CMOS transmission gate consists of one nMOS and one pMOS transistor, connected in parallel. The
gate voltages applied to these two transistors are also set to be complementary signals.

• As such, the CMOS TG operates as a bidirectional switch between the nodes A and B which is controlled by
signal C. If the control signal C is logic-high, i.e., equal to VDD, then both transistors are turned on and
provide a low-resistance current path between the nodes A and B.

• If, on the other hand, the control signal C is low, then both transistors will be off, and the path between the
nodes A and B will be an open circuit. This condition is also called the high-impedance state.

• Note that the substrate terminal of the nMOS transistor is connected to ground and the substrate terminal of
the pMOS transistor is connected to VDD. Thus, we must take into account the substrate-bias effect for both
transistors, depending on the bias conditions
• Figure also shows three other commonly used symbolic representations of
the CMOS transmission gate. For a detailed DC analysis of the CMOS
transmission gate, we will consider the following bias condition, shown in
figure.

• The input node (A) is connected to a constant logic-high voltage, Vin =

VDD. The control signal is also logic-high, thus ensuring that both
transistors are turned on.

• The output node (B) may be connected to a capacitor, which represents

capacitive loading of the subsequent logic stages driven by the
transmission gate.
'XOR' gate using pass transistor logic:

The truth table of 'XOR' gate is as shown in Table. In this gate if the B input is low
then left NMOS transistor is ON and the logic value of A is copied to the output F.

When B input is high right NMOS transistor is ON and the inverted logic value of
A is copied to the output F, which satisfies the truth table of the XOR gate.
7. (a) Explain the problem of charge sharing in dynamic CMOS designs and its probable solution.

Ans. In digital electronics, charge sharing is an undesirable signal integrity phenomenon observed most
commonly in the Domino logic family of digital circuits.

• The charge sharing problem occurs when the charge which is stored at the output node in the precharge phase
is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge
sharing may degrade the output voltage level or even cause erroneous output value.

• In the dynamic CMOS circuit technique, clock pulse is given between a PMOS and a NMOS and the NMOS
logic is associated between them.

• The circuit operation is based on first precharging the output node capacitance and subsequently estimating
the output level according to the applied inputs. Together these operations are scheduled by a single clock
signal which drives one NMOS and one PMOS transistors in each dynamic stage.
• When the clock signal is high then precharge transistor p1 turns off and n1 turns on. If the input signal forms a
conducting path between the output node and ground then output capacitance will discharge to 0V.

• When the clock signal is low the PMOS transistor p1 is conducting and the complementary NMOS transistor
n1 is off .The output capacitance of the circuit is charged up through the conducting PMOS transistor to a logic
high level of VDD.

• One simple solution to eliminate charge sharing problem is just to add a weak PMOS pull-up device(with a
small W/L ratio) to the dynamic CMOS stage output, which basically forces a high output level except there is
a strong pull-down path amongst the output and the ground.

• It can be observed that the weak PMOS transistor will be turned on only when the precharge node voltage is
retained high. Otherwise it will be turned off as output voltage becomes high.
7. (b) Compare the BiCMOS logic with CMOS in terms of delay and power consumption. Why was BiCMOS
logic used in Intel Pentium and Pentium Pro but discarded in Pentium II?

Ans. Advantages of BiCMOS over CMOS:

• Low Power Consumption: In BICMOS gates perform same as the CMOS inverter when it comes to
power consumption, because both gates display almost no static power consumption.

• The major dissipation is done by the discharging of the capacitors. When comparing BICMOS and
CMOS in driving small capacitive loads, their performance are comparable, however, making BICMOS
consume more power than CMOS.
• On the other hand, driving larger capacitive loads makes BICMOS in the advantage of
consuming less power than CMOS, because the construction of CMOS inverter chains are
needed to drive large capacitance loads, which is not needed in BICMOS.

• BICMOS has better performance in terms of delay and power consumption, in compared
to CMOS. In latest trend of VLSI circuit design is High speed and Low power.
8. (a) Explain the dual rail domino logic. Design XOR/XNOR gate using dual rail domino logic.

Ans. Dual-Rail Domino is also known as “Differential Cascade Voltage Switch” (DCVS). Domino only
performs non inverting functions like AND, OR but not NAND, NOR, or XOR. Dual-rail domino solves this
problem by taking true and complementary inputs and producing true and complementary outputs.

• There are also some other limitations associated with domino CMOS logic gates. First, only non-inverting
structures can be implemented using domino CMOS. If necessary, inversion must be carried out using
conventional CMOS logic. Also, charge sharing between the dynamic stage output node and the intermediate
nodes of the nMOS logic block during the evaluation phase may cause erroneous outputs.
8. (b) Implement the full adder using transmission gates.

Ans. The circuit diagram of a 3-bit full adder is shown in the figure.
The output of XOR gate is called SUM, while the output of the AND
gate is the CARRY.

• The AND gate produces a high output only when both inputs are
high. The XOR gate produces a high output if either input, but not
both, is high.

• The truth table of 3-bit full adder is given. The 3-bit full adder
circuit has a provision to add the carry generated from the lower
bits.

• Complementary MOS Logic Style consists of Pull-Up Network

(PUN), which has PMOS transistors and the Pull-Down Network
(PDN), which consists of NMOS transistors.
• The Pull-Up Network connects the output of the gate with Vdd whenever
the output of the gate is high. The Pull-Down Network connects gate
output and GND when the gate output is low. This logic style consists of
28 transistors.

Full Adder using Transmission Gate :

• It consists on n-channel and p-channel transistors with common

connections for source and drain and separate gate connection.

• The circuit has a total of 20 transistors, comprising of transmission gates,

PMOS and NMOS. The use of transmission gates enables the circuit to
have high speed and low power dissipation.
• On comparing performance analysis, it is observed that 1-bit full adder
using CMOS and Transmission gate, the average power for CMOS is
more than the Transmission gate for different technology.

• In CMOS technology, it is found that keeping the voltage constant, as

technology decreases from 180nm to 32nm, the transistor count remains
the same but the average power decreases from 7.057uW to
1.474uW.The minimum power is 1.474uW for 32nm.

• In Transmission gate technology, it is found that keeping the voltage

constant, as technology decreases from 180nm to 32nm, the transistor
count remains the same but the average power decreases from 6.792uW
to 1.193uW.The minimum power is 1.193uW for 32nm.

• CMOS 1-bit full adder contains more number of transistors than

Transmission gate 1-bit full adder, hence it is bulky.
9. (a) Explain the working of 4T SRAM cell with neat diagram.

Ans. To achieve a reduction in area consumption by SRAM cell, a simpler

design, i.e., 4T SRAM cell was designed as shown in Figure. The 4T SRAM
consists of four NMOS and two poly-load resistors. The PMOS transistors
of the 6T cell are replaced by very high polysilicon resistors to reduce
transistor count and area consumed by the cell.

Advantages: This cell comprises of lesser number of transistors as well as

consumes lesser area compared to the 6T cell.

Disadvantages: This cell is sensitive to noise and soft error because of the
very high resistances involved in the design.
• The basic operation of any SRAM is performed in three different modes.
The modes are Standby Mode, Write Mode and Read Mode.

• These operation are performed by using two nMOS, two pass transistor
both of which are driven by row select line or the “word line”. The 4T
SRAM Cell is accessed through two Bit Lines. This arrangement is more
reliable.

Standby Mode :
• In this mode the word line is not asserted. The pass transistor will disconnect the cell from the bit lines. So if
the word line is not asserted then the access transistor or pass transistor does not let the memory cell to
connect with the bit lines (Bit and Bit bar).

• This will cause the two cross coupled inverter formed to continue to strengthen
each other to the supply. When cell is in standby mode no action could be taken
and to store the data more power is consumed by the SRAM. So there is need of
techniques to reduce the leakage current.
Read Mode :

• The read operation is started by enabling the word line (WL) and joining
the bit lines Bit and Bit bar to the internal nodes of the cell. The voltage
of column Bit is remained high and volume of Bit bar is pulled down.

• Now the difference in the voltages of both the columns are detected and
the difference is amplified as a logic “1” output. The read operation for
“0” is performed vice-versa. The difference between Bit and Bit bar
should be minimum and this difference is sensed and amplified as logic
“0”.
Write Mode :

• The write operation is performed by applying the desired value to the bit line “Bit”.
Like if we wish to write logic “1” then we make “Bit” to high and “Bit bar” to low.

• Similarly if we want to write logic “0” then we perform the operation in vice-versa.
The word line WL should be asserted for this mode.
9. (b) Explain the working of a 3T DRAM with neat diagram.

Ans. The simplest DRAM cell is the 3T scheme. A 3T DRAM cell has a higher density than a SRAM cell;
moreover in a 3T DRAM, there is no constraint on device ratios and the read operation is nondestructive.

• In this cell, the storage capacitance is the gate capacitance of the readout device, so making this scheme
attractive for embedded memory applications; however, a 3T DRAM shows still limited performance and low
retention time to severely limit its use in advanced integrated circuits.

• 3T DRAM utilizes gate of the transistor and a capacitance to store the data value. When data is to be written,
write signal is enabled and the data from the bit line is fed into the cell. When data is to be read from the cell,
read line is enabled and data is read through the bit line. 3T DRAM cell occupies less area compared to the
4T DRAM cell.
Three-Transistor (3T) DRAM Cell

• The circuit diagram of a typical three-transistor dynamic RAM cell

is shown in figure as well as the column pull-up (precharge)
transistors and the column read/write circuitry.

• Here, the binary information is stored in the form of charge in the

parasitic node capacitance C1.

• The storage transistor M2 is turned on or off depending on the

charge stored in C1, and the pass transistors Ml and M3 act as access
switches for data read and write operations.

• The cell has two separate bit lines for "data read" and "data write,"
and two separate word lines to control the access transistors.
• The operation of the three-transistor DRAM cell and its peripheral
circuitry is based on a two-phase non-overlapping clock scheme.

• The precharge events are driven by ϕ1, whereas the "read" and
"write" events are driven by ϕ2. Every "data read" and "data write“
operation is preceded by a precharge cycle, which is initiated with
the precharge signal PC going high.

• During the precharge cycle, the column pull-up transistors are

activated, and the corresponding column capacitances C2 and C3
are charged up to logic-high level.

• With typical enhancement type nMOS pull-up transistors (Vt0=1.0

V) and a power supply voltage of 5 V, the voltage level of both
columns after the precharge is approximately equal to 3.5 V.
• All "data read" and "data write" operations are performed during
the active 2 phase, i.e., when PC is low.

• Figure depicts the typical voltage waveforms associated with the 3-

T DRAM cell during a sequence of four consecutive operations:
write " 1," read "1,“ write "0," and read "0." The four precharge
cycles shown in figure are numbered 1, 3,5, and 7, respectively.

• Figure, illustrates the transient currents charging up the two

columns (Din and Dout) during a precharge cycle. The precharge
cycle is effectively completed when both capacitance voltages
reach their steady-state values.

• Note here that the two column capacitances C2 and C3 are at least
one order of magnitude larger than the internal storage capacitance
C.
• For the write "1" operation, the inverse data input is at the logic-low level, because the data to be written
onto the DRAM cell is logic "1." Consequently, the "data write“ transistor MD is turned off, and the
voltage level on column Din remains high.

• Now, the "write select" signal WS is pulled high during the active phase of ϕ2. As a result, the write access
transistor Ml is turned on. With Ml conducting, the charge on C2 is now shared with Cl, as shown in
figure. Since the capacitance C2 is very large compared to C1, the storage node capacitance Cl attains
approximately the same logic-high level as the column capacitance C2 at the end of the charge-sharing
process.
• After the write "1" operation is completed, the write access transistor MI is turned off. With the storage
capacitance C charged-up to a logic-high level, transistor M2 is now conducting. In order to read this stored
"1," the "read select" signal RS must be pulled high during the active phase of ϕ2, following a precharge cycle.

• As the read access transistor M3 turns on, M2 and M3 create a conducting path between the "data read“ column
capacitance C3 and the ground. The capacitance C3 discharges through M2 and M3, and the falling column
voltage is interpreted by the "data read" circuitry as a stored logic "1."

• The active portion of the DRAM cell during the read "1" cycle is shown in figure. Note that the 3-T DRAM cell
may be read repeatedly in this fashion without disturbing the charge stored in C.
• For the write "0" operation, the inverse data input is at the logic-high level,
because the data to be written onto the DRAM cell is a logic "0."
Consequently, the data write transistor is turned on, and the voltage level on
column Din is pulled to logic "0."

• Now, the "write select" signal WS is pulled high during the active phase of ϕ2.
As a result, the write access transistor Ml is turned on. The voltage level on
C2, as well as that on the storage node Cl, is pulled to logic "0" through MI
and the data write transistor, as shown in figure.

• Thus, at the end of the write "0" sequence, the storage capacitance C1 contains
a very low charge, and the transistor M2 is turned off since its gate voltage is
approximately equal to zero. In order to read this stored "0," the "read select"
signal RS must be pulled high during the active phase of ϕ2, following a
precharge cycle.
• The read access transistor M3 turns on, but since M2 is off, there is no
conducting path between the column capacitance C3 and the ground, figure.
Consequently, C3 does not discharge, and the logic-high level on the Dout
column is interpreted by the data read circuitry as a stored "0" bit.
• As we already pointed out in the beginning of this section, the charge stored in C1 cannot be held
indefinitely, even though the "data read" operations do not significantly disturb the stored charge.

• The drain junction leakage current of the write access transistor Ml is the main reason for the gradual
depletion of the stored charge on C1. In order to refresh the data stored in the DRAM cells before they are
altered due to leakage, the data must be periodically read, inverted (since the data output level reflects the
inverse of the stored data), and then written back into the same cell location.
• This refresh operation is performed for all storage cells in the DRAM array every 2 to 4 ms. Note that all bits
in one row can be refreshed at once, which significantly simplifies the procedure. It can be seen that the three-
transistor dynamic RAM cell examined here does not dissipate any static power for data storage, since there is
no continuous current flow in the circuit.

• Also, the use of periodic precharge cycles instead of static pull-up further reduces the dynamic power
dissipation. The additional peripheral circuitry required for scheduling the non-overlapping control signals and
the refresh cycles does not significantly overshadow these advantages of the low-power dynamic memory.