Unit-2

DIGITAL LOGIC FAMILY

 Most electronic systems which are responsible for modern advances
are based on digital technology.
 All digital systems, computers and microprocessors are assembled
from simple circuits called logic circuits.
 The basic building blocks of logic circuits are logic gates. And logic
gates themselves are simple electronic circuits comprising of diodes,
transistors and resistors.
CLASSIFICATION OF LOGIC FAMILIES:
CLASSIFICATION OF LOGIC FAMILY
Logic families are mainly classified as
1.Bipolar Logic Families: It mainly uses bipolar devices like diodes, transistors in addition to
passive elements like resistors and capacitors. These are sub classified as saturated bipolar
logic family and unsaturated bipolar logic family.
Saturated Bipolar Logic Family:
In this family the transistors used in ICs are driven into saturation. For example:
1. Transistor-Transistor Logic (TTL)
2. Resistor-Transistor Logic (RTL)
3. Direct Coupled Transistor Logic (DCTL)
4. Diode Transistor Logic (DTL)
5. High Threshold Logic(HTL)
6. Integrated Injection Logic (IIL or I 2 L)
Unsaturated bipolar logic family:
In this family the transistors used in IC is not driven into saturation. For example:
7. Schottky TTL
8. Emitter Coupled Logic(ECL)
2.Unipolar Logic Families:
It mainly uses Unipolar devices like MOSFETs in addition to passive elements like resistors
and capacitors.
These logic families have the advantages of high speed and lower power consumption than
Bipolar families. These are classified as:
1. PMOS or P-Channel MOS Logic Family
2. NMOS or N-Channel MOS Logic Family
3. CMOS Logic Family
Characteristics of Digital logic families
In case of integrated circuits belonging to different logic families, digital system should
ensure compatibility interfacing techniques.
And that is the reason why we must be clear about different logic families and use the best
combination of integrated circuits during the design of a digital system.
The characteristics which are bound to be identical and used to compare performance are:
1.Propagation delay
2.Fan-in
3.Fan-out
4.Power dissipation
5.Logic levels
6.Noise margin
7.Figure of merit
 DEFINITIONS
Fan-in:
Fan in or gate is the number of inputs that can practically be supported without
degrading practically input voltage level.
Fan Out:
 The maximum number of digital input that the output of a single logic gate can feed and
the gate must be same logic family.
 Fan Out is calculated from the amount of current available in the output of a gate and the
amount of current needed in each input of the connecting gate.
 It is specified by manufacturer and is provided in the data sheet.
 Exceeding the specified maximum load may cause a malfunction because the circuit will
not be able supply the demanded power.
Figure of Merit of a Logic Family:
 The product of propagation delay and average power dissipation is called Figure of merit.
 It is also called Speed-power Product(SPP).
 The speed power product is smaller, the better the overall performance.
Speed power product =Propagation delay x Power dissipation
LOGIC LEVELS:
The voltages or currents that are used to represent to a LOW state (0 level) and HIGH state
(1 level).
Positive logic : HIGH = 1(i.e,+5 v) LOW = 0 (i.e ,0v)
Negative logic : HIGH = 0(i.e ,+5v) LOW = 1 (i.e ,0v)
Voltage requirements of TTL and CMOS IC’s
Continu…
when using a standard +5 volt supply any TTL voltage input between 2.0v and 5v
is considered to be a logic “1” or “HIGH” while any voltage input below 0.8v is
recognized as a logic “0” or “LOW”.
The voltage region in between these two voltage levels either as an input or as an
output is called the Indeterminate Region and operating within this region may
cause the logic gate to produce a false output.
The CMOS 4000 logic family uses different levels of voltages compared to the
TTL types as they are designed using field effect transistors, or FET’s.
 In CMOS technology a logic “1” level operates between 3.0 and 18 volts and a
logic “0” level is below 1.5 volts.
Then the following table shows the difference between the logic levels of
traditional TTL and CMOS logic gates.
Propagation Delay:
Propagation delay is the time between presentation of input and change of
output to a new logic level.
 For modern solid state logic gates propagation delays are in the range of
nanoseconds.
Noise Margin
 •Noise is present in all real systems. This adds random fluctuations to voltages
representing logic levels.
 •Hence, the voltage ranges defining the logic levels are more tightly
constrained at the output of a gate than at the input.
 • Small amounts of noise will not affect the circuit.
 The maximum noise voltage that can be tolerated by a circuit is termed its
noise immunity (noise Margin).
Continu…
Example:
A certain gate draws 1.8 mA when its output is HIGH and 3.2mA when its output is LOW.
What is its average power dissipation if VCC is 5 V and it is operated on 50% duty cycle?
Solution:
The average ICC is given as,
Icc(avg) = ICCH+ICCL/2
= 1.8+3.2/2
= 2.5mA
Then average power dissipation is given as,
PD(avg) = ICC(avg) X VCC
= 2.5mA X 5V
= 12.5mW.
Comparison of TTL,CMOS AND ECL:
 Inputs to the NOR gate shown above are ‘input1’ & ‘input2’. The inputs applied at these
terminals represent either logic level HIGH (1) or LOW (0).

 The logic level LOW is the voltage that drives corresponding transistor in cut-off region,
while logic level HIGH drives it into saturation region.

 If both the inputs are LOW, then both the transistors are in cut-off i.e. they are turned-off.
Thus, voltage Vcc appears at output I.e. HIGH.

 If either transistor or both of them are applied HIGH input, the voltage Vcc drops across
Rc and output is LOW.

 RTL family is characterized by poor noise margin, poor fan-out capability, low speed and
high power dissipation. Due to these undesirable characteristics, this family is now
obsolete.
Resistor-Transistor Logic (RTL) family
 The resistor-transistor logic, also termed as RTL, was most popular kind of logic before
the invention of IC fabrication technologies.
 As its name suggests, RTL circuits mainly consists of resistors and transistors that
comprises RTL devices.
 The basic RTL device is a NOR gate, shown in figure below.
Diode-Transistor Logic (DTL) family
The diode-transistor logic, also termed as DTL, replaced RTL family because of greater fan-
out capability and more noise margin.
As its name suggests, DTL circuits mainly consists of diodes and transistors that comprises
DTL devices.
The basic DTL device is a NAND gate, shown aside.
 Three inputs to the gate are applied through three diodes viz.
D1, D2 and D3. The diode will conduct only when
corresponding input is LOW.
 If any of the diode is conducting i.e. when at least one input is
LOW, the voltage at cathode of diode DA is such that it keeps
transistor T in cut-off and subsequently, output of transistor is
HIGH.
 If all inputs are HIGH, all diodes are non-conducting, transistor
T is in saturation, and its output is LOW.
 Due to number of diodes used in this circuit, the speed of the
circuit is significantly low. Hence this family of logic gates is
modified to transistor-transistor logic i.e. TTL family.
Transistor-Transistor Logic (TTL) family
TTL family is a modification to the DTL. It has come to existence so as to overcome the
speed limitations of DTL family. The basic gate of this family is TTL NAND gate.
Modifications to DTL NAND-
1. The diodes D1, D2 and D3 are replaced by emitter-base junctions of a multiple-emitter
transistor labeled T1.

2. Diode DA is replaced by collector-base junction of T1.

3. Diode DB is replaced by emitter-base junction of transistor labeled T2.

The working of this circuit is identical to that of DTL circuit.

Case1- When at least one input is logic LOW, transistor T2 and T3 are in cut-off and hence,
output of T3 is HIGH.

Case2- When all inputs are HIGH, T1 operates in active inverse mode, driving T2 & T3 in
saturation. Since T3 is ON, the output is LOW.

Case3- While all inputs are HIGH, if any of the inputs suddenly goes LOW, then T2 and T3
will be turned off only when stored base charge is removed. The collector-base junction of T1
is back-biased and T1 operates in normal active region.
 A large collector current of T1 is in such direction that it helps removing base charge of T2
and T3. In this way, the circuit speed is increased in TTL over speed of DTL.
What is a TTL output?
 A majority of systems we use rely on either 3.3V or 5 V TTL Levels.
 TTL is an acronym for Transistor-Transistor Logic.
 It relies on circuits built from bipolar transistors to achieve switching and maintain logic
states. ... Basically, this means that output voltage of the device driving HIGH will always
be at least 2.7 V.

Why does the TTL family use a totem pole circuit on the output?
 The main advantage of TTL with a "totem-pole" output stage is the low output resistance
at output logical "1".
 It is determined by the upper output transistor V3 operating in active region as an emitter
follower.
What is Totem-pole output?
 Totem-pole output, also known as a push-pull output, is a type of electronic circuit and
usually realized as a complementary pair of transistors.
 The High and Low level of the output are determined.
 The output of high level is 10 V max, low level is 0.5 V min.
 In any case, TTL gates in all the available series come in three different types of output
configuration:
1. Open-collector output.
2. Totem-pole output.
3. Three-state output.

TTL NAND GATE WITH TOTEM-POLE OUTPUTS

TTL outputs: Totem pole/ active pull-up
It is possible in TTL gates the charging of output capacitance without corresponding
increase in power dissipation with the help of an output circuit arrangement referred to as an
active pull-up or totem-pole output. In this case,
• Outputs must never be connected together.
• Connecting outputs causes excessively high currents to flow.
• Outputs will eventually be damaged.
• The standard TTL output configuration with a HIGH output and a LOW output transistor,
only one of which is active at any time.
• A phase splitter transistor controls which transistor is active.
Operation:

If A or B is low, the base-emitter junction of Q1 is forward biased and its base-collector
junction is reverse biased. Then there is a current from Vcc through R1 the base emitter
junction of Q1 and into the LOW input, which provides a path to the ground for the current.
Hence there is no current into the base of Q2 and making it into cur-off. The collector of Q2
is HIGH and turns Q3 into saturation. Since Q3 acts as a emitter follower, by providing a
low impedance path from Vcc to the output, making the output into HIGH. At the same
time, the emitter of Q2 is at ground potential, keeping Q4 OFF.

When A and B are high, the two input base emitter junctions of Q1 are reverse biased and
its base collector junction is forward biased. This permits current through R1 and the base
collector junction of Q1 into the base of Q2, thus driving Q2 into saturation. As a result Q4
is turned ON by Q2, and producing LOW output which is near ground potential. At the
same time, the collector of Q2 is sufficiently at LOW voltage level to keep Q3 OFF.
Emitter Coupled Logic (ECL) family
 ECL logic family implements the gates in differential amplifier configuration in which
transistors are never driven in the saturation region thereby improving the speed of circuit to
a great extent. The ECL family is fastest of all logic families.
 The basic gate of ECL family is NOR gate (OR and NOR together) as shown in diagram.
The output1 is OR output while ouput2 is NOR output.
 Transistor T1 is applied with input and additional inputs are applied to transistors (T1’,
T1’’, . . .) in parallel with T1. Thus transistor(s) T1 and T2 are connected in differential
amplifier configuration.

 Transistors T3 and T4 are emitter-followers used for DC level-shifting of output voltages.

 The positive supply terminal of the circuit is grounded while negative supply terminal is at
negative 5.2V. This is done to minimize the effect of noise introduced by the power supply
and also to protect the gate from short-circuit that might occur accidently.

 Both the outputs (HIGH/LOW) for OR and NOR are negative. Thus, to interface this logic
family with other, a translator circuit is needed which converts negative voltages to
compatible positive voltage levels.
MOS Logic family
 MOS logic family implements the logic gates using MOSFET devices. MOSFETs are high
density devices which can easily and economically fabricated on ICs. MOS logic gates can
be fabricated using either only NMOS or only PMOS devices.
 MOS logic is vastly used in LSI and VLSI devices, such as microprocessor chips, due to
their high density characteristic.
 NMOS NOR gate is shown in figure.
 If both transistors T1 and T2 are off i.e. A = B = LOW, then output is HIGH = VDD.
 If either of the inputs is HIGH, then corresponding transistor(s) is/are ON, thus connecting
output to GND i.e. LOW.
 If both inputs are ON, then only both T1 and T2 are ON and output is LOW; otherwise (when
either or both transistors are OFF,) the output is HIGH.
 This is NAND operation on applied inputs.
CMOS Logic family
 CMOS stands for complementary-MOS, in which both p-channel and n-channel
enhancement MOSFET devices are fabricated on same chip. This causes density to be
reduced and complex fabrication process. However, CMOS devices consume negligible
power and hence are preferred over MOS devices in battery operated applications.
 A CMOS NAND gate is shown in figure below.
 T1 and T2 are n-channel MOSFETs while T3 and T4 are p-channel MOSFETs.
 When both inputs A & B are HIGH, then T1 & T2 are ON while T3 & T4 are OFF.
Hence, output is connected to GND i.e. LOW.
 If either input is LOW, then either T3 or T4 is ON, connecting output is +Vcc i.e. HIGH.

 Similar is working of CMOS NOR gate shown in figure above. Here, p-channel devices
are in series and n-channel devices are in parallel.