Digital Electronics (Logic Families)

IC Logic Families

Objectives

Upon completion of this chapter, you will be able to:

 Understand the terminologies associated with IC technology

 Design and compare the performance of logic gates using different logic families

Introduction

Digital Logic has advanced rapidly from Small Scale Integration (SSI) with 12 gates per chip
to Very Large Scale Integration (VLSI) with tens of thousands of gates per chip. ICs pack a lot
more circuitry in a small package as compared to discrete components and this results in
smaller size of the circuit. ICs differ in the components that they use in their circuitry like TTL
family uses BJT and CMOS logic family uses MOSFET.

Characteristics of logic family

Propagation delay (tPD)

 It is measured in nsec.
t t
 t  PHL PLH
pd 2
 t is the propagation delay when output goes from HIGH to LOW and t is the
PHL PLH
propagation delay when output goes from LOW to HIGH.

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 Digital Electronics (Logic Families)

 Propagation delay is always measured from 50% value of the input and output
waveforms.
 In Transistors, ON to OFF time is more compare to OFF to ON time due to saturation or
storage time.

Power dissipation

Power dissipation by each logic gate P  V I mW

diss cc avg

Where Vcc is the collector voltage or supply voltage and Iavg is the average supply current.

Figure of Merit (FOM)

FOM  P t joule
diss pd

 I2L have best FOM.

 The desirable condition is the low value of FOM.

Fan out

 It is maximum number of logic gate that can be driven by a logic gate.

I
fanout  OH
H I
IH

I
fanout  OL
L I
IL


 Maximum fan out is min value of fanout , fanout
H L 
 TTL have max fan out.

 IOH is the output current of a gate when output of gate is high and IOL is the output
current of gate in low state.

 IIH is the output current of a gate when output of gate is high and IIL is the output current
of gate in low state.

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 Digital Electronics (Logic Families)

Noise Margin

 It is the maximum noise voltage that can be added to the logic family which will not affect
the output.

V 0 0V
IL OL

V 1 1V
lH OH

 V V V V
OH IH IL OL
 NM  V  V and NM  V  V
H OH IH L IL OL

 Overall noise margin = NM ,NM
H L min 
Solved Examples

Problem: If I  400A, I  40A, I  16mA, I  1.6mA Find fanout?

OH IH OL IL

400 16
Solution: fanout   10 fanout   1.0
H 40 L 1.6

Maximum fan out 10,10 min  10

Construction of gates

AND Gate

A B D D Y
A B
0 0 ON ON 0
0 1 ON OFF 0
1 0 OFF ON 0
1 1 OFF OFF 1

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 Digital Electronics (Logic Families)

OR Gate

A B D D Y
A B
0 0 OFF OFF 0
0 1 OFF ON 1
1 0 ON OFF 1
1 1 ON ON 1

NOT

If A = 0, T is cutoff, Y = 1.
r

If A = 1, T is Sat. , Y = 0.
r

NAND

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

NOR

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

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 Digital Electronics (Logic Families)

Solved Examples

Problem:

Solution: V  AB  CD
0

Note:

 When logic gate is input is 0 (Transistor OFF) it will act as current source.
 When logic gate input is 1 (Transistor ON) it will act as current sink.

 In cutoff and saturation region transistor will act as switch.

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 Digital Electronics (Logic Families)

J J Region
E C
RB RB cutoff
RB FB Re verse active
FB RB Active
FB FB Saturation

RTL (Register Transistor logic) family

 Basic gate: NOR gate.

 t  50ns ; FOM = 500 pJ
pd
 NM = 0.2V
 Fan-out = 3
 Wired AND used

Disadvantage
 Lower speed of operation.
 Low noise margin.
 Lowest fan out.

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 Digital Electronics (Logic Families)

DCIL (Direct coupled transistor logic) Family

 In RTL logic family if input resistance removed then resultant is DCIL.

 t  40nsec
pd

A B T T Y
1 2
0 0 OFF OFF 1
0 1 OFF ON 0
1 0 ON OFF 0
1 1 ON OFF 0

Disadvantage

Current hogging: In DCIL logic, if the switches used have different characteristics then the
Transistor having lower V will be first ON and it will not allow other Transistor to turn
BE SAT
ON, this phenomenon is known as current hogging.

2
Integrated Injection logic I L

 It is injecting current into base.

 When A is high the current flows through the base of Transistor .i.e. Transistor must be
ON.
 I2L covers less space. i.e. I2L have high density.
 It is equivalent to NOT gate.

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 Digital Electronics (Logic Families)

 There is no problem of current hogging.

 FOM = 0.1PJ - 0.7PJ
 Best FOM among all the logic families.
 t  40ns
pd
 Fan out = 8.
SSI  1  12 

MSI  B  99  no. of gates used
 
LSI  100  1000  in this int egration.
VISI   1000  
 In I2L logic, due to integration of PNP and NPN Transistor. It occupies less area hence
density is more in I2L logic. It is mostly used in MSI and LSI logic family.
 Also called MTL (merged logic family) due to integration of transistor.

DTL (Diode Transistor logic) Family

AND gate followed by NOT gate

A B T Y
1
0 0 OFF 1
0 1 OFF 1
1 0 OFF 1
1 1 ON 0

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 Digital Electronics (Logic Families)

 20k resistor used only for discharging the transition capacitance. The capacitance which is
discharge is transition capacitance C .
c
 The circuit is called Basic DTL gate.
 In this any one of the inputs is low or all the inputs are low, D or D will become
A B
forward biased whereas D and D will become reverse biased due to Transistor T is OFF
1 2 1
and output is 1.
 When all the inputs are high then D and D become reverse biased and D and D will
A B 1 2
become forward biased and T is ON and output is low.
1

NAND Gate

 To increase fan out we introduce Transistor in place of diode.

 It provides wired AND operation.
 5K resistor used to lower the I current.
1
 t  30ns.
pd
 P  8mw
diss
 FOM = 240PJ.
 NM = 0.75V.
 Fan out = 3.

High Threshold logic (HTL) Family

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 Digital Electronics (Logic Families)

 Zener diode is used in place of D

2
 NM = 4 – 5V (Highest noise margin)
logic 0  2V 
  Higher voltage swing
logic 1  12V 
 t  90ns
pd
 P  55mw
diss
 FOM = 4950 PJ - 5000 PJ
 Fan out = 8
 Basic gate = NAND gate

Solved Examples

Problem: Consider the DTL circuit shown in figure given below. The output Y of the given
circuit is

Solution: When any of the inputs is low, Q1, D2 and Q2 are OFF and hence the output is
HIGH and when all inputs are HIGH, then Q1, D2 and Q2 conduct pulling the output logic
LOW.

TTL (Transistor Transistor logic) Family

T = Multi emitter transistor.

1

 The circuit shown in fig. is standard TTL logic family. It basically have three stage.
1. Multi-emitter I/P stage.
2. Phase splitter.

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 Digital Electronics (Logic Families)

3. Totem pole or active pull up output stage.

(Active =use for Transistor and Pull up= Transistor connect to VCC )

Operation:-

 Any one of input is low or all inputs are low, then the EB junction is Forward Biased.

 JE  FB  and collector base  JC  RE is Reverse Biased. Transistor is in active mode due to
this transistor T and T are OFF (in cut-off region) whereas T is in saturation. Hence,
2 3 4
output is 1.
 When all the inputs are high then J (EB junction) of T is Reverse Biased. And J (CB
E 1 C
junction) is Forward Biased. (The mode of operation is Reverse active). T and T are in
2 3
saturation and T is in cutoff. Hence output is zero.
4
 V  2V , V  2.4V , V  0.8 , V  0.4 , t  10ns
IH OH IL OL pd
 P  10mw
diss
 Fanout  10
 NM = 0.4V
 Diode D is used to cutoff T T when T is ON.
r 4 3

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 Digital Electronics (Logic Families)

Advantage of Totem pole

 Lower power dissipation.

 Higher speed of operation.
 Higher fan out.

Disadvantage of Totem pole

 It is not used in wired logic.
 To provide wired AND logic open collector configuration is used.
 130Ω resistor used in collector in output stage to reduce ripple or noise generation in the
high frequency of operation.
 In TTL if any input is open it behaves as logic 1.
 Clamping diodes are connected in input stage to protect transistor during high frequency
of operation.
 There are different type of TTL
1. Standard TTL
2. High speed TTL
3. Low speed TTL
4. Schottky TTL

High speed TTL

 In standard TTL logic family if resistor value reduce then t reduce and known as high
pd
speed logic family. t  6nsec
pd
 Power dissipation increases.

Low speed TTL

 In TTL logic family if resistor value increased then power dissipation reduced and resultant
known as low power logic family.

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 Digital Electronics (Logic Families)

Schottky TTL

 It Schottky Diode is used between collector and base region then it will remove storage
time and saturation delay. The family known as Schottky TTL.

t  2nsec
pd

ECL (Emitter Coupled logic Family)

 It is never go in saturation region.

 Work only in cutoff and active region.
 It is fastest logic family due to work in active and cutoff region. (Because it is non-
saturated)

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 Digital Electronics (Logic Families)

 t  1 nsec
pd
 Fan out = 25
 It basically contains two stage.
1. Differential amplifier Input stage.
2. Common Collector or Emitter follower output stage.
 Due to used of Differential amplifier complementary output are available in ECL logic
family. (NOR/OR) gate.
 Due to use of Common Collector stage in the output fan out is high.
 ECL uses negative power supply. Due to this any spikes or negative voltage not affect
operation.

 t  1ns
pd
 P  55mw
diss
 FOM = 55PJ
 Fan out = 25
 NM = 0.3 V
logic 0  1.7V 
  It is logic 1 mode only volatge supply is negative
logic 1  0.85V 

 ECL provide wired and logic

 If any input is open then it is logic ‘0’

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MOS (Metal Oxide Semiconductor)

 N–channel MOS

Logic ‘0’ = OFF

Logic ‘1’ = ON

 P–Channel MOS

Logic ‘0’ = ON

Logic ‘1’ = OFF

 Since FET in voltage variable resistor hence in MOS circuit in place of resistor we use
MOSFET.

 NMOS NOT Gate

A T Y
2
0 OFF 1
1 ON 0

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 NMOS NAND Gate

A B T T Y
2 3
0 0 OFF OFF 1
0 1 OFF ON 1
1 0 ON OFF 1
1 1 ON ON 0

 NMOS NOR Gate

t  250nsec
pd

P  1mw
diss

FOM = 250 PJ

Fan out = 5

NM = 1.5V

 PMOS NOT Gate

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

t  300nsec
pd

P  0.2mw
diss

FOM = 60 PJ

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Strong input 1 Strong input 0

PMOS  NMOS 
Weak input 0  Weak input 1

Where, V  threshold voltage

T

CMOS NOT Gate

A T T Y
1 2
0 ON OFF 1
1 OFF ON 0

 Transfer Characteristics

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 Lowest power dissipation

P  0.01mw
diss

t  70nsec
pd

FOM = 0.7 PJ

Fan out = 50

V
NM  DD
2

 Power dissipation

Static Power dissipation: During logic ‘0’ or logic ‘1’.

Dynamic Power dissipation: During transition from 0  1 or 1  0 , PD  cfV2

DD

CMOS NAND Gate

A B T T T T Y
1 2 3 4
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0

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Solved Examples

Problem: The expression for output “Y ” for the circuit given below is

Solution: Y  A(B  C)  A  (B  C)  A  BC = A+BC

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