Digital Converters (Data Converters)

Data Converters

Objective

Upon completion of this chapter you will be able to:

 Design different Digital to Analog Converters.

 Design and compare performances of different Analog to Digital Converters.

Introduction

In this digital age, all the processing is done in digital form but most of real world signals are
analog in nature. So, we need an interface between Analog and Digital Signals which are
called as Data Converters. There are two basic types of Data Converters Analog to Digital
Converter and Digital to Analog Converter.

Digital to Analog converter (DAC)

Important Terms

 Resolution/step size: It is the change in analog voltage corresponding one LSB

increment in the Input.

V
Re solution  r Where V = Reference voltage corresponding to logic 1.
n r
2 1
n = no. of bits.

 Analog output voltage: V  Re solution  Decimal equivalent of binary data

analog

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 Digital Converters (Data Converters)

 VFS: Full scale voltage is the maximum analog output voltage of DAC.

V
V  r  2n  1  V
FS n r
2 1

Resolution 1
 % Resolution   100   100
V 2n 1
FS

 Error/Accuracy: Error acceptable in ADC’s or DAC’s is equal to resolution or step size.

Solved Examples
Problem: In a 4 bit DAC reference voltage is 5V, if binary data 1001 is applied then analog
voltage is.
V
Solution: Resolution  r  5 1
3
2n  1 16  1
1
V   9  3V
analog 3

Digital to Analog Circuit

Weighted Resistor DAC (4 Bit)

b  MSB  more current

3
b  LSB  Less current
0
V
I  r *b
3 R 3
V
I  r *b
2 2R 2
V
I  r *b
2 2R 1
V
I  r *b
0 8R 0

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 Digital Converters (Data Converters)

I I I I I
f 3 2 1 0
V  I R
 0 f f
 LSB Resis tance   2n  1  MSB resis tance
 
 In weighted resistor DAC the accuracy is less due to use of different resistance. To
overcome this we use R – 2R ladder.

R – 2R ladder
R-2R Ladder

Normal ladder Inverted ladder

Non inverting Inverting

3 bit R – 2R ladder (Non-inverting)

 Adjacent to 2R is LSB.

 R 
V  1  f V
0  R  X
 l 

V = Resolution * Decimal equivalent of binary data.

X
V n1
 r *  2i bi
2n i  0

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 Digital Converters (Data Converters)

n1
2 1 0 2ibi
decimal equivalent of b b b binary data  b 2  b 2  b 2  
2 1 0 2 1 0
i0

V n1  R 
 V  r   2ibi *  1  f 
0
2n i  0 

R
i


 V = Resolution * Decimal * gain
0

3bit R – 2R ladder (Inverting)

 V = Resolution * decimal * gain

0
V n1  R 
 V  r   2ibi *  f 
0 n  R  R
2 i0  1 
V n1  1 
 I  r   2ibi *  
f n  R  R 
2 i0  1 

Inverter ladder type DAC circuit

 Since A and A’ both are ground then (logical or virtual ground and ground) the switch is
at same potential then charging and discharging of switch problem removed in previous
circuit.

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 Digital Converters (Data Converters)

V
I rR

I I I I
I  b I  b I  b I  b
3 2 3, 2 4 2 , 1 8 1, 0 16 0

I  V n  1 
1
 r i
1 0  2n  
 I  I  I  I  I  8b  4b  2b  b   2 b 
f 0 1 2 3 16  3 2 i R
i 0 
V n  1   R 
 V  r   2ib   f 
0 i  R
2n  i  0
 
 

Solved Examples

Problem: If a 12-bit (3-digit) DAC that uses the BCD input code has a full scale output of
9.99V, then the value of Vout for an input code of 0111 1001 0101 is __________ V.
9.99
Solution: Step size=  10mV
999
0111 1001 0101
7 9 5
Vout  795  10mV  7.95V

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 Digital Converters (Data Converters)

Analog to Digital Converter

Important terms

range
 Resolution 
2n  1
 VRange  V V
max min
1
 % Resolution   100
2n  1
 Dynamic Range  6n  1.76 dB  6ndB

Analog to Digital Converter circuits

Counter Type ADC

V V V V
1 2 0 ref

V  V  V  V
1 2 0 ref

 It is one bit quantizer.

 In counter type ADC a comparator is used in Input stage to compare Input analog voltage
with reference voltage provided by DAC feedback.
 A counter is used to count number of clock pulses applied.
 When analog voltage V
a   is greater than DAC voltage then output is 1. Then counter
counts and if analog voltage  V  is less than reference voltage (DAC voltage) then output is
a
0 and counter stops counting and it give corresponding digital output.

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 Digital Converters (Data Converters)

 Maximum number of clock pulses required for ‘n’ bit conversion is 2n  1 .


 Maximum conversion time  2n  1 T
CLK 
. Conversion time depends on Input analog

voltage.
 Also called Ramp type ADC.

Parallel Comparator Type ADC

2n  1 comprator required



 For n  bit 2n resistor required
 n
2  n Pr iority encoder required

 Also called Flash ADC (fastest ADC)

3 Bit Parallel Comparator Type ADC

 1 clock pulse is required.

 Therefore it is fastest ADC among all.
 Maximum number of clock pulse required for ‘n’ bit conversion is which is inside PIPO.

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 Digital Converters (Data Converters)

Range of analog output

7V
V  r 111
a 8
7V 6V
r V  r 110
8 a 8
6V 5V
r V  r 101
8 a 8
5V 4V
r V  r 100
8 a 8
4V 3V
r V  r 011
8 a 8
3V 2V
r V  r 010
8 a 8
2V V
r V  r 001
8 a 8
V
r V 000
8 a

SAR Type (Successive appropriation Register)

SOC: Start of conversion.

EOC: End of Conversion.

 Ring counter is used to set the base.


 Control circuit is used to reset when V  V
a r 
 In SAR Type ADC, ring counter will be present to successively set the base.
 Control circuit is used to reset, previously set bit when V  V
a r
 In SAR Type ADC, n clock pulse required for n bit conversion.

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 Digital Converters (Data Converters)

 Conversion time  nT
clock
 SAR type, conversion time is independent of Analog Input Voltage.
 SAR is mostly used in digital circuit to provide interface with microprocessor.

Dual slope Integrating type ADC

 V slope is always greater than V slope.

r a

 In dual slope, a counter is used to count clock pulse.

 Initially counter is reset to zero and switch is connected to V (analog voltage) where
a
integrator is integrating analog voltage.
 Output of integrator will become negative voltage, due to this comparator output
becomes 1 and counter counts clock pulses .
 After 2n pulses again counter output becomes zero.
 At this time t control circuit connect switch S to V . During V integration up to T
1 R R 2
time output of integrator is negative. Due to this counter again continue clock pulses at time
T output of integrator become positive and comparator output becomes 0 due to this
2
counter will stop.
 Let N is count when counter stops then,

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 Digital Converters (Data Converters)

V V
V   a T  r tT
o RC 1 RC 1   At time t  T , V  0
2 0

V V
0   
a .T  r T  T  V T  V T  T
RC 1 RC 2 1 a1 r 2 1  
V .2n.T
a CLK
 V NT
r 
CLK 
V 2n V
N a or V  r .N
a
V
r 2n

If V  2n then V  N
r a

 This is the most accurate ADC among all.

 All ripple and noise is separated or compressed by capacitor. (Therefore this have more
accuracy due to integrator.)
n n
 Maximum number of clock pulse = 2  2  1  2n  2n  2n  1
 Conversion Times for N bit ADCs.
Type of ADC Conversion Time (Clock Cycles)
Counter Type
2N
Successive Approximation Type N
Dual Slope Integration Type (N+1)
2
Flash Type 1

Application

 Mostly used in digital voltmeter.

Solved Examples

Problem: A 10 - bit successive approximation ADC has a resolution of 10 mV. Determine

digital output for analog input of 4.365 V.

4.365
Solution: Digital output= =436.510  43610
10 mV

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 Digital Converters (Data Converters)

Problem: For a dual slope type ADC, frequency of Clock is 1 MHz, Vreferance  1.0 . Fixed time
period T1 is 1ms, RC time constant is set to 2ms and Input voltage, Vi  5V . Value of Ramp
voltage Vs is ___________________V

tfix 1
Solution: Vs  Vin  5  2.5V
RC 2

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