Timing Constraints – Delays

1
Propagation Delay and Contamination Delay

Propagation Delay – Time from last input change until last output change. (Input at
steady state to output at steady state.)

Contamination Delay – Time from first input change until first output change. (Input
contaminated to output contaminated)

t1 t2 t3 t4
a
a
CL b

b
tcab tdab

2
 Example: Contamination and Propagation Delay of
Full Adder
a
g'
Q1 cout
Q5
p'
Q2
b
Q3
s
Q4
cin
What is
min a,b cin max a,b cin
Gate Delay g’ 80 - g’ 80 - tdas
(ps) p’ 120 - p’ 200 - tcas
Nand2 80 cout 200 120 cout 320 120
tdcs
OAI21 120 U3 200 80 U3 280 80
tccc
s 240 120 s 400 200
 a
g'
Q1 cout
Q5
p'
Q2
b
Q3
s
Q4
cin
What is
min a,b cin max a,b cin
Gate Delay g’ 80 - g’ 80 - tdas
(ps) p’ 120 - p’ 200 - tcas
Nand2 80 cout 200 120 cout 320 120
tdcs
OAI21 120 U3 200 80 U3 280 80
tccc
s 240 120 s 400 200
 a
g'
Q1 cout
Q5
p'
Q2
b
Q3
s
Q4
cin
What is
min a,b cin max a,b cin
Gate Delay g’ 80 - g’ 80 - tdas
(ps) p’ 120 - p’ 200 - tcas
Nand2 80 cout 200 120 cout 320 120
tdcs
OAI21 120 U3 200 80 U3 280 80
tccc
s 240 120 s 400 200
 What about an n-bit adder?

cout

a[n-1] cout Assume delay of FA is 1

a
s[n-1]
FA s
b[n-1] b
cin
What is
tdas

a[1] a
cout tcas
s
s[1]
FA
b[1] b
tdcs
cin
c[1]

tccs
a[0] a
cout

s s[0]
FA
b[0] b
cin
cin

6
 Edge-Triggered D Flip-Flop

d x
d q ts th
D Q
clk
tdCQ
tcCQ
clk
q x

7
Timing Constraints – Setup and hold

8
 Edge-Triggered D Flip-Flop

d x
d q ts th
D Q
clk
tdCQ
tcCQ
clk
q x

9
 Setup Time Constraint
c d a
Min D Q

a b c
tcy > t dCQ + t dMax + t s
Max D Q

clk

clk

a X

b f(X)

tdCQ tdab ts
tslack
 Hold Time Constraint

c
Min
d
D Q
a th < t cCQ + t cMin

a
Max
b
D Q
c
Unsafe at any speed
clk

clk

d tcXY – contamination delay

tdXY – propagation delay
tcCQ tccd

th tslack
 Example
c d a
Min D Q

tdCQ = tcCQ = ts = 150ps

th = 250ps
tdMax = 850ps
a b c
Max D Q

tcMin = 100ps clk

Is hold time constraint met?

c d a
Min D Q

What is the minimum cycle time?

a b c
Max D Q

clk
Timing Constraints – Clock skew

13
 Clock Skew
t cy > t dCQ + t dMax + t s + t k
c
Min
d
D Q
a t h < t cCQ + t cMin - t k

a b c
Max D Q

tk clk
tcCQ
clk
c
tccd

d
tk
clkd
th tslack
Example

tdCQ = tcCQ = ts = 150ps

th = 250ps
tdMax = 850ps
tcMin = 100ps
tk = 100ps

Is hold time constraint met?

What is the minimum cycle time?

15
 4-bit Prime or one Function in Verilog Code –
Result of synthesizing description using case
module prime ( in, isprime );
input [3:0] in;
output isprime;
wire n1, n2, n3, n4;
OAI13 U1 ( .A1(n2), .B1(n1), .B2(in[2]), .B3(in[3]), .Y(isprime) );
INV U2 ( .A(in[1]), .Y(n1) );
INV U3 ( .A(in[3]), .Y(n3) );
XOR2 U4 ( .A(in[2]), .B(in[1]), .Y(n4) );
OAI12 U5 ( .A1(in[0]), .B1(n3), .B2(n4), .Y(n2) );
endmodule
in[0]

in[3] n3 U5
U3

in[2] 0XX1
n4
U4 X101
X01X X011
X10X n2
isprime
U1
in[1] n1
U2
001X
16
 Synthesis Reports ****************************************
Report : timing
****************************************
-path full
Report : area
-delay max
Design : prime
-max_paths 1
Version: 2003.06
Design : prime
Date : Sat Oct 4 11:38:08 2003
Version: 2003.06
****************************************
Date : Sat Oct 4 11:38:08 2003
****************************************
Library(s) Used:
Operating Conditions:
GS30KA_W_125_1.35_CORE.db (File:
/home/imagine/from_ti/gs30ka_1.3/sun5/synop Wire Load Model Mode: enclosed
sys/lib/GS30KA_W_125_1.35_CORE.db)
Startpoint: in[2] (input port)
Number of ports: 5 Endpoint: isprime (output port)
Number of nets: 9 Path Group: (none)
Number of cells: 5 Path Type: max
Number of references: 4
Des/Clust/Port Wire Load Model Library
Combinational area: 7.000000 ------------------------------------------------
Noncombinational area: 0.000000 prime 2K_5LM
GS30KA_W_125_1.35_CORE.db
Net Interconnect area: undefined (Wire load has zero
net area)
Point Incr Path
Total cell area: 7.000000 --------------------------------------------------------
---
Total area: undefined
in[0] input external delay 0.000 0.000
r
in[2] (in) 0.000 0.000
r
in[3] n3 U5 U4/Y (EX210) 0.191 0.191
U3
f
in[2] U5/Y (BF051) 0.116 0.307
0XX1 r
n4 U1/Y (BF052) 0.168 0.475
U4 X101
f
X01X X011 isprime (out) 0.000 0.475
X10X n2 f
isprime data arrival time 0.475
U1 --------------------------------------------------------
---
in[1] n1 (Path is unconstrained)
U2
001X
 Summary
• Delays in digital systems
– Propagation delay
– Contamination delay
• Flip-flop timing constraints
– Setup time (ts)
– Hold time (th)
• Cycle time determined by maximum delay
tcy > t dCQ + t dMax + t s
• Correct operation depends on minimum delay
th < t cCQ + t cMin
• Clock skew affects both
t cy > t dCQ + t dMax + t s + t k
t h < t cCQ + t cMin - t k