Silicon (2023) 15:1003–1009

https://doi.org/10.1007/s12633-022-02080-0

ORIGINAL PAPER

Buried Metal Silicon‑on‑Insulator Junctionless Transistor for Low

Power CMOS Logic Circuits
Kaustubh K. Tiple1 · Ganesh C. Patil1 

Received: 16 May 2022 / Accepted: 25 August 2022 / Published online: 31 August 2022
© Springer Nature B.V. 2022

Abstract
This paper deals with an innovative structure of silicon-on-insulator junctionless transistor (SOIJLT) by incorporating a
buried metal layer of proper work-function which creates the Schottky junction between device layer and the buried metal
layer. The buried metal layer results in perfect volume inversion in OFF-state due to which in comparison to SOIJLT, the
off-state current (IOFF) of the proposed buried metal SOIJLT (BMSOIJLT) is significantly reduced. In addition, the short-
channel effects such as subthreshold swing (SS) and the drain-induced barrier lowering (DIBL) in the proposed BMSOIJLT
are reduced by 40% and 30% respectively over the SOIJLT device. The CMOS digital logic circuits such as inverter, NAND
gate and the NOR gate have also been implemented using the mixed-mode device/circuit simulations. Despite due to lower
ON-state drive current (ION) and the parasitic capacitances in the proposed BMSOIJLT, the propagation delay in SOIJLT
and the proposed BMSOIJLT based logic gates is comparable. Moreover, due to significant reduction in IOFF the static power
dissipation in the proposed BMSOIJLT based logic gates is significantly low.

Keywords  Schottky barrier · Buried metal · Scalability · Low-power CMOS

1 Introduction channel region. On the other hand, in ON-state the device

As the channel length scales down, it is difficult to maintain
the steep doping profiles at the source-channel and channel-
drain interfaces of the MOSFETs [1]. To overcome this
issue, the junctionless transistor (JLT) has been proposed to
avoid the p-n junctions at source-channel and channel-drain
interfaces. As compared to MOSFETs the JLTs have fol-
lowing advantages 1) the process flow is greatly simplified
as halo/extension and deep source/drain implants are not
required, and 2) after gate stack formation implant activa-
tion anneal step is removed, due to which thermal budget is
reduced [2]. However, short channel effects and the off-state
leakage (IOFF) are the major bottlenecks in JLTs.
In conventional MOSFETs the IOFF is controlled by
reversed p-n junction, whereas in silicon-on-insulator junc-
tionless transistor (SOIJLT) IOFF is controlled by the gate
work-function. As we increase the gate voltage, the deple-
tion region reduces and the carriers start accumulating at the
* Ganesh C. Patil
ganeshcpatil@cvn.vnit.ac.in
1
Center for VLSI and Nanotechnology, Visvesvaraya National
Institute of Technology, Nagpur 440010, India
achieves the flat-band and the depletion region completely
disappears and the on-state current (ION) starts flowing [3, 4].
Many studies have been carried out on JLTs and it has been
shown that the spacers reduce the IOFF and also helps in reduc-
ing the short channel effects [5, 6]. Therefore, silicon-nitride
­(Si3N4) has been used as the spacers for the simulated devices
of this work. In JLT, during OFF-state there is high vertical
electric field, whereas in ON-state there is low horizontal
field [7, 8]. New JLT structures studied in the literature are
junctionless multiple-gate MOSFETs [9], asymmetric short-
channel junctionless quadruple-gate FET [10], negative-capac-
itance JLT [11], vertically stacked nanosheet JLT [12], core-
shell junctionless nanotube tunnel field effect transistor [13],
silicon-on-nothing electrostatically doped junctionless tunnel
field effect transistor [14], junctionless silicon nanotube tun-
nel field effect transistor [15], δ-doped partially insulated JLT
[16], negative capacitance δ-bulk planar JLT [17] and dual-k
spacer bulk planar JLT [18]. The JLT includes thin uniformly
doped device layer whose resistance is modulated by the gate
electrode because of which the JLT works like a gated resistor.
Therefore, in order to use the JLT for the complemetry metal
oxide semiconductor (CMOS) applications, the ON/OFF of
the JLT is most important. To overcome this bottleneck, we

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1004 Silicon (2023) 15:1003–1009

propose the buried metal silicon-on-insulator junctionless Table 1  Device Parameters used in simulation
transistor (BMSOIJLT) in which a buried metal layer has been Parameter Unit SOIJLT BMSOIJLT
incorporated in between the buried oxide (BOX) and the device
layer. In the proposed device, at junctionless device layer and Physical gate length (LG) nm variable variable
the buried metal layer interface the metal-semiconductor (M-S) Buried oxide thickness (TBOX) nm 20 20
Schottky contact is formed (when the work-function of the bur- Channel thickness (TChannel) nm 10 10
ied metal is greater than the work-function of the semiconduc- Gate oxide thickness (TOX) nm 2 2
tor). Since carrier transport in the device layer above the buried Substrate thickness (TSubstrate) nm 20 20
oxide (BOX) is mainly due to drift-diffusion (DD) mechanism Buried metal thickness (Tmetal) nm – 10
and the carrier transport at Schottky junction is due to Schottky Spacer thickness (Tspacer) nm 5 5
barrier tunneling (SBT) [4], both DD and SBT models have Gate workfunction eV 4.45 4.45
been used in the sentaurus sdevice simulations. Channel doping density cm−3 1 × ­1018 1 × ­1018
Substrate doping density cm−3 1 × ­1017 1 × ­1017
Supply voltage (VDD) V 1 1
2 Device Structures and Simulation Models

Figure 1 shows the n-channel (NMOS) and p-channel (PMOS) simulations are saturation mobility model due to high electric
device structures of SOIJLT and the proposed BMSOIJLT used field, Philips unified mobility model for mobility degradation
in the sentaurus sdevice tool which is provided by the Synop- due to both impurity and carrier-carrier scattering, mobility
sys [19]. The device parameters and the dimensions used in the dependence model on transverse electric field, bandgap nar-
simulations are shown in the Table 1. The scaling of physical rowing model due to high Si doping in the channel, Shockley-
gate length (LG) has been carried out by varying the LG from Read-Hall (SRH) and Auger recombination models.
22 nm-to 10 nm in steps of 2 nm [20]. The threshold voltage
(VTH) of the proposed BMSOIJLT is found to be 0.3 V and
for SOIJLT it is 0.1 V at the gate work-function of 4.45 eV for 3 Results and Discussions
both the devices. The threshold voltages are calculated from
the gate-to-source voltage (VGS) for which the drain current 3.1 Impact of Metal Work Function on ­IOFF
(IDS) drops to the value 1­ 0−7 × W/LG. Here, W is the width and
the gate-to-drain voltage (VDS) is considered to be 1 V. Along From Fig. 2 it can be seen that, at equilibrium Fermi level is
with DD and SBT models, the remaining models utilized in the constant throughout the device. Further, due to buried metal
Fig. 1  (a) Conventional NMOS
SOIJLT, (b) proposed NMOS
BMSOIJLT, (c) conven-
tional PMOS SOIJLT and (d)
proposed PMOS BMSOIJLT
device structures

13
Silicon (2023) 15:1003–1009 1005

in the BMSOIJLT, Schottky junction is formed between 10

-3

channel and the metal which results in band bending at the -4

metal-channel interface. This band bending leads to sig- 10
nificant reduction in the IOFF of the proposed BMSOIJLT 10
-5

device. This is mainly because, the BM-SOILJLT is the -6

junctionless laterally and it also has the Schottky junction 10 =4.55 eV

(A/ m)
m
-7
isolation vertically. Due to this the depletion layer is being 10 =4.75 eV
m
created at the bottom of the device layer which leads to the -8
10 =5.15 eV
volume depletion and reduces the IOFF [3]. The Schottky m

OFF
barrier cannot be seen in SOIJLT as there is no buried metal. 10
-9
m
=5.35 eV
Therefore, leakage current is much less in BMSOIJLT com- 10
-10

pared to SOIJLT. Further, from Fig. 3 it can also be seen -11

that, as the metal work-function (ϕm) of the buried metal 10
increases, Schottky barrier height increases. Therefore, the 10
-12

presence of Schottky barrier reduces the current. Thus, to 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
obtain the lower leakage current Schottky barrier height at GS
(V)
the metal-channel interface should be higher.
Fig. 3  Impact of buried metal work function on off-state leakage cur-
rent in proposed NMOS BMSOIJLT
3.2 DC Performance

As discussed in Section 3.1 the optimized work-function of
5.15 eV is considered for both NMOS and PMOS devices
of the proposed BMSOIJLT architecture. Figure 4 shows
the ID-VGS characteristics of NMOS/PMOS BMSOIJLT
and SOJLT in log scale and linear scale. From Fig. 4 it
can be seen that, in comparison to SOIJLT, the presence
of buried layer in the proposed BMSOIJLT device reduces
the IOFF in both NMOS and PMOS devices. However, the
presence of Schottky barrier in proposed BMSOIJLT also
reduces the ION. Therefore, in comparison to SOIJLT ION
in proposed NMOS/PMOS BMSOIJLT is lower. From
Fig. 5, it can also be observed that, the difference in IOFF
of the BMSOIJLT and SOJLT devices is almost of four
decades and the difference in I ON of the BMSOIJLT and
SOJLT is comparable.
Figure 5 shows the ION/IOFF ratio of proposed NMOS/
PMOS BMSOIJLT and conventional SOIJLT devices.
Device is OFF at VGS = 0 V (IOFF is extracted). Device is

Fig. 2  Vertical band diagram

(a) SOIJLT and (b) proposed
BMSOIJLT NMOS at equilib-
rium

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1006 Silicon (2023) 15:1003–1009

10
-3
0.25 250
SOIJLT 200 SOIJLT
10
-4 BMSOIJLT 150 BMSOIJLT
0.20

DIBL (mV/V)
-5 100 NMOS
10 50
10
-6 0
0.15
(A/ m)

(mA/ m)
-50
-7
10 -100 PMOS
-8 PMOS NMOS 0.10 -150
10 -200
D

-9 -250
10

D
0.05 10 12 14 16 18 20 22
10
-10 Physical Gate Length (nm)
-11
10 0.00
-1.0-0.8-0.6-0.4-0.2 0.0 0.2 0.4 0.6 0.8 1.0 Fig. 6  DIBL variations with LG for NMOS/PMOS BMSOIJLT and
SOJLT devices
GS
(V)

Fig. 4  ID-VGS characteristics of proposed NMOS/PMOS BMSOIJLT 300

and SOJLT for LG = 20 nm and VDS = ± 1 V SOIJLT
250
BMSOIJLT
200
SS (mV/Decade) NMOS
150
4 500
8x10 100
Ratio

SOIJLT
Ratio

4
7x10 400
4 BMSOIJLT
6x10 -100
5x10
4 300
OFF

-150
OFF

4
4x10 200 -200
/

4
3x10
ON

/ ON

2x10
4
100 -250
4 NMOS PMOS
1x10 -300
500
10 12 14 16 18 20 22
4
8x10 Physical gate length (nm)
Ratio
Ratio

4
7x10 400
4
6x10
4 300 Fig. 7  SS variations with LG for NMOS/PMOS BMSOIJLT and
5x10
OFF
OFF

4 SOJLT devices
4x10 200
/

4
/

3x10
ON
ON

4
2x10 100
4 PMOS
1x10
0.18 0.20
10 12 14 16 18 20 22 SOIJLT
Physical gate length (nm) 0.17 BMSOIJLT 0.18
0.16
Fig. 5  ION/IOFF variations with LG for NMOS/PMOS BMSOIJLT and 0.16
0.15
(fF/ m)
(fF/ m)

SOJLT devices

0.14 0.14

ON when VGS > VTH and VDS > VGS-VTH (here at VDS = 1 V, 0.13

0.12
gd
gs

ION is extracted). From Fig. 5, ION/IOFF in proposed NMOS/

0.12
PMOS BMSOIJLT devices is improved significantly over
0.10
the NMOS/PMOS SOIJLT devices. 0.11

0.10 0.08
3.3 Short Channel Effects 0.0 0.2 0.4 0.6 0.8 1.0
GS
(V)
The drain induced barrier lowering (DIBL) is a short chan-
nel effect which reduces VTH at higher VDS. The DIBL is Fig. 8  Cgs and Cgd variations with VGS for NMOS BMSOIJLT and
given by [21, 22]. NMOS SOJLT devices. Here, LG = 20 nm and VDS = 1 V

13
Silicon (2023) 15:1003–1009 1007

18 0.72 SOIJLT
8 SOIJLT 0.64
15 BMSOIJLT
(nW/ m)

BMSOIJLT 0.56

OFF
6 12
0.48

( W)
x
9 0.40
4

DD
0.32
DD

static
( W/ m)
0.24
2
x

3
0.16
OFF

0 0.08
0
10 12 14 16 18 20 22 0.00
Physical Gate Length (nm) INVERTER NAND NOR

Fig. 9  Leakage power dissipation variations with LG for NMOS Fig. 11  Comparison of static power dissipation of the CMOS
BMSOIJLT and NMOS SOJLT devices inverter, NAND and the NOR gates based on proposed BMSOJLT
and SOIJLT NMOS/PMOS devices

VTLIN − VTSAT The subthreshold swing (SS) is defined as the amount of

DIBL = . gate-to-source voltage required to achieve one decade change
0.95
The saturation threshold voltage (V TSAT) of proposed
NMOS and PMOS BMSOIJLT is 0.3 V and − 0.3 V respec-
tively and the VTSAT of NMOS and PMOS SOIJLT is 0.1 V
and − 0.1 V whereas the linear threshold voltage (VTLIN) is
found to be comparable for both BMSOIJLT and SOIJLT
devices. From Fig. 6, as compared to SOIJLT NMOS/PMOS
devices, the DIBL of the proposed BMSOIJLT NMOS/
PMOS devices reduces. This is due to the fields arising from
the drain, which reduces the coupling near to source and
leads to reduction in DIBL of BMSOIJLT NMOS/PMOS
devices [3]. The VTLIN and VTSAT are the threshold voltages
at VDS = 50 mV and 1 V, respectively [18]. In order to equal-
ize the threshold voltages of NMOS/PMOS devices the gate
work function of the PMOS devices has been adjusted.
in drain current in sub-threshold regime. From Fig. 7 SS
increases with scaling LG, and it is reduced by ~40% in pro-
posed BMSOIJLT NMOS/PMOS devices over the SOIJLT
NMOS/PMOS devices. This reduction is mainly because of
the presence of buried metal layer in BMSOIJLT devices.
3.4 Parasitic Capacitances
From Fig. 8 it is observed that both gate-to-drain capaci-
tance (Cgd) and gate-to-source capacitance (Cgs) of pro-
posed BMSOIJLT is lower than SOIJLT which shows
that parasitic capacitances are lower in the proposed
BMSOIJLT device. This is due to buried metal in pro-
posed BMSOIJLT which absorbs charge from channel, as

Fig. 10  (a) CMOS inverter, (b)

NAND gate, and (c) NOR gate
circuits used in the mixed-mode
device/circuit simulations

13
1008
60
SOIJLT
Propagation Delay (pSec)
50 BMSOIJLT
40
pHL
30
20
pLH
10
0 of mixed-mode device circuit simulations. The NMOS and PMOS
Inverter NAND NOR
Fig. 12  Comparison of propagation delay of the CMOS inverter,
NAND and the NOR gates based on proposed BMSOJLT and SOI-
JLT NMOS/PMOS devices
metal have property to absorb point charge, this reduces
charge in channel.
3.5 Static Power Dissipation
Further, from Fig. 9 it is observed that static power dissipation
(IOFF × VDD) of proposed BMSOIJLT is significantly low in com-
parison to SOIJLT. This is mainly because of the Schottky bar-
rier due to the buried metal layer of the device. This significant
reduction in the static power dissipation shows the importance of
the proposed device architecture for low power digital CMOS.
3.6 CMOS Logic Circuit Performance
Figure 10 shows the inverter, NAND and the NOR CMOS logic
circuits implemented using SOIJLT and BMSOIJLT NMOS/
PMOS devices. The circuits shown in Fig. 10 are simulated by
using the mixed-mode device/circuit simulations. The details
regarding the doping concentrations, the meshing and the gate-
source/drain contacts information and the model details for
NMOS/PMOS devices have been further used for the mixed-
mode device/circuit simulations. The static power dissipation
(Pstatic) is being extracted using the DC analysis and the propa-
gation delay has been extracted from the high-to-low (Tphl) and
low-to-high (Tplh) propagation delays.
From Fig. 11 it is observed that, in comparison to SOIJLT
based inverter, NAND and NOR circuits the static power
dissipation (Pstatic) in BMSOIJLT based inverter, NAND and
NOR circuits is significantly low. This is mainly due to the
significant reduction in IOFF of the BMSOIJLT.
Figure 12 shows the comparison of high-to-low (Tphl) and low-to-
high (Tplh) propagation delay for inverter, NAND and NOR CMOS
logic circuits implemented using SOIJLT and BMSOIJLT NMOS/
13
Silicon (2023) 15:1003–1009
PMOS devices. The total propagation delay in the case of SOIJLT
based CMOS logic circuits is comparable with the BMSOIJLT
based circuits. However, due to higher ION in SOIJLT devices, the
propagation delay in the case of SOIJLT based CMOS logic circuits
is slightly lower than the BMSOIJLT based CMOS logic circuits.
In this work, the Tplh is extracted from the time between 50% input
(0.5 V) to output 50% (0.5 V) for low-to-high transition of output
whereas Tphl is extracted from the time between 50% input (0.5 V)
to output 50% (0.5 V) for high-to-low transition of output. To calcu-
late propagation delay, inputs in the form of pulses having 1 MHz
frequency have been applied. The physical devices are named as
NMOS and PMOS, and are defined in separate device statements
devices are connected to form the CMOS circuits shown in Fig. 10.
4 Conclusion
In this work, the impact of buried metal inserted between device
layer and the BOX layer of SOIJLT has been broadly studied by
using sentaurus sdevice (2D TCAD) tool provided by Synopsys.
The BMSOIJLT has been studied to evaluate the CMOS logic
circuit performance of the BMSOIJLT and SOIJLT devices. It
has been found that, the incorporation of buried metal layer in
BMSOIJLT forms the Schottky barrier due to which the leakage
current in the BMSOIJLT is lower than the SOIJLT NMOS/
PMOS devices. This results in significant reduction in static
power dissipation in inverter, NAND and NOR CMOS circuits
based on BMSOIJLT NMOS/PMOS devices. Thus, incorporat-
ing buried metal layer in SOIJLT makes it a promising device
for low-power CMOS logic circuits.
Author Contributions  All the authors contributed equally.
Data Availability  Not applicable.
Declarations 
Consent to Participate  Not applicable.
Consent for Publication Yes
Conflict of Interest  The authors declare no conflict of interest.
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