2015 Fifth International Conference on Advanced Computing & Communication Technologies

A study of conventional and junctionless MOSFET using TCAD Simulations

Neeraj Gupta Janak B. Patel A. K. Raghav

Assistant Professor Professor Director, Industrial R&D
Amity School of Engineering & Amity School of Engineering & Amity university Haryana
Technology Technology Gurgaon, Haryana
Gurgaon, Haryana Gurgaon, Haryana
neerajsingla007@gmail.com janakbpatel71@gmail.com akraghava@gmail.com

Abstract— As the transistors are scaling down, a

conventional MOSFET calls for stringent doping gradients
which are quite difficult to achieve. Moreover, the short
channel effects become more and more prominent with
scaling. Contrary to a conventional MOSFET a junctionless
transistor is devoid of junctions and its current drive is
controlled by the doping concentration instead of the gate
capacitance. Though it is quite unorthodox to accept a device
sans semiconductor junctions into the family of transistors.
A junctionless transistor displays very good performance in
comparison with a conventional MOSFET especially when
the channel is short. Basically, the conduction observed in
the junctionless transistor is bulk conduction whereas a
conventional MOSFET relies on surface conduction. This
paper presents simulation of a Junctionless Transistor in
Silvaco and comparison of its performance with that of a
conventional MOSFET. The parameters needed for the
comparison are to be obtained from the transfer
characteristics as well as the output characteristics.
Keywords- Effective oxide thickness, Sub threshold swing,
Short channel effect (SCE) and junctionless transistor.
opposed to surface conduction in traditional MOS). This
device will normally work in accumulation mode (As
opposed to inversion mode in traditional MOS). Scaling
of JNT will be somewhat easy because of the lack of
junction [8,9]. The operation is almost similar to the
traditional MOSFETs. Also most of the second order
effects are minimised in junctionless transistor [10, 11].
In this paper, there are four sections: Section-I includes
the introduction, Section-II described devices structure,
section-III covered analysis of electrical characteristics
along with output and transfer characteristics section-IV
includes the conclusion and future work.
II . Device Structure

I. Introduction JLT is as simple as a Silicon wire. One end of the wire is

People want devices with high speed, small size, low treated as Source and the other end as Drain. Region in

power consumption etc. The most common way to between source and drain will work as the channel. There

achieve this is by scaling down the devices. But scaling is no distinction between source, channel and drain. All

has reached its limits. With the Short Channel Effects the three are heavily and homogenously doped. The

(SCE) gaining the momentum, the MOSFET operation device structure obtained is given in the Fig 1.

began to get suffered with scaling [1,2]. A new method

must be found out to satisfy the high demands in the
electronics world. junctionless transistor can be the
answer for this. The great ancestor of the MOSFET as
envisioned by Julius Edgar Lilienfield was a junctionless
device whose conductivity can be modulated by the
voltage applied at the gate[3-5]. The junctionless
nanowire transistor (JNT) is a heavily-doped SOI
nanowire resistor with an MOS gate that controls current
flow [6,7]. A junctionless transistor will provide the most
idealized characteristics. The fabrication is also very easy
because there is no channel. Bulk conduction is the
Fig 1: Device structure of the junctionless transistor (JLT)
method of current flow in junctionless transistor (As

2327-0659/15 $31.00 © 2015 IEEE 53

DOI 10.1109/ACCT.2015.51
Fig 2 shows the device structure of a conventional channel of an inversion-mode MOSFET can fall to values
MOSFET used to conduct a comparative study between below 20 ܿ݉2/ܸ.‫( ݏ‬assuming EOT = 1nm and VG = 1V)
JLT and MOSFET. The structures formed are (Silicon- because of the high electric field in the channel. In a JLT,
On-Insulator) SOI structures with a Silicon thickness of the electric field in the channel perpendicular to the
10 nm with a channel length of 20 nm. Both the devices current flow is essentially equal to zero which ensures
are n-channel devices. For this the conventional MOSFET bulk mobility values [14].
requires a p-type body, while the JLT requires an n-type Transfer Characteristics
body. The transfer characteristics of the JLT and the MOSFET
are depicted in Fig 3. Here, the red curve corresponds to
transfer characteristics of the JLT whereas the green curve
is that of the conventional MOSFET. It clearly depicts
that the JLT has a higher current driving capability than
the conventional MOSFET. The higher current driving
capability is mainly due to the fact that in JLT, bulk
mobility is associated with the conduction [15-16].
Moreover, the threshold voltage of the JLT is smaller than
the MOSFET. This confirms that the Gate terminal has a
higher control over the channel in a JLT. The ‫ܫ‬on / ‫ܫ‬off
ratio of the JLT is larger compared to that of a
conventional MOSFET. Fig 4 depicts log(ID)-VGS
Fig 2: Device structure of conventional MOSFET characteristics. Junctionless transistor has a smaller sub-
threshold swing (SS) than a conventional MOSFET.
The JLT is heavily doped with a concentration of 5×1018
cm–3. The MOSFETs also are having Drain and Source
diffusions of 5×1018 cm–3. The buried oxide layer has a
thickness of 50 nm. The buried oxide is placed on a
substrate of 20 nm thickness.
III . Analysis of Electrical Characteristics
Though the physics of the JLT is quite different from that
of standard multi-gate FETs, the electrical characteristics
of the JLTs are remarkably identical to those of regular
MOSFETs. Depletion of the heavily doped nano-wire
creates a large electric field perpendicular to current flow
below threshold, but above threshold the field drops to
zero, because the conducting channel is electrically
neutral. This is the opposite of Inversion-Mode (IM) or
even Accumulation-Mode (AM) devices where the field is
highest in the channel when the device is turned on
Fig 3: ID-VGS characteristics of JLT and the
[12,13]. In the absence of strain-based mobility conventional MOSFET
enhancement techniques, the electron mobility in the

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Fig 4: Log(ID)-VGS curves of JLT and the conventional
MOSFET
Output Characteristics
The output characteristics of the Junctionless transistor is
shown in Fig 5 and plotted with the help of TCAD
Silvaco [17]. The red curve is the output characteristics of
the JLT and the green curve depicts that of the
conventional MOSFET. The output characteristics are
very similar in nature to that of a bulk MOSFET. The
characteristics reveal that, the JLT has a higher current
driving capability than the conventional MOSFET.
Moreover, the JLT has a smaller on resistance (Ron) in
the linear region in comparison to that of a traditional
MOSFET.
Fig 5: Output characteristics of JLT and the conventional
MOSFET
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IV. Conclusion and Future Work
As the technology nears the 10nm regime, conventional
MOSFETs offer a greater manufacturing challenge and its
properties are degraded by the Short Channel Effects
(SCEs). In such a situation, the Junctionless Transistor
(JLT) is good alternative to be considered. The
manufacturing process for a JLT is much easier and
cheaper compared to that of a conventional MOSFET.
This is mainly due to the absence of junctions or
concentration gradients in the device. Moreover, JLT can
offer nearly ideal characteristics even in smaller
dimensions and the SCEs are less prominent in a JLT.
Hence they are more reliable than MOSFETs for smaller
dimensions. The current driving capability of a JLT is
higher than its conventional counterpart for similar
dimensions. So, the JLT serves as a good candidate to be
considered for future technology nodes.
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