Evaluation of Stability, Performance of

Ultra-Low Voltage TFET SRAM Cell With

Write-Assist Circuits

Kota Vinay Mishra Vishal Khairnar Nirman Dr. Sri Adibhatla Sridevi
VLSI Design VLSI Design VLSI Design Department of Micro and
VIT University, Vellore VIT University, Vellore VIT University, Vellore Nano Electronics
Kota.vinay2019@gmail.com Mishra.vishal1996@gmail.c nirmankhairnar7@gmail.co VIT University, Vellore
om m

Abstract— The down-scaling of conventional MOSFETs has

led to an impending power crisis, in which static power
consumption is becoming too high. In order to improve the
energy-efficiency of electronic circuits, small swing switches are
used to replace the MOSFETs used today. The stability and
performance of the proposed TFET 8T cell are used on TCAD
simulations based on published design rules for 20 nm technology
node. Tunnel FETs, which are gated p-i-n diodes whose on-
current arises from band-to-band tunneling, are attractive new
devices for low-power applications due to their low off-current
and their potential for a small sub threshold swing.

Keywords— Band-to-band tunneling, gated p-i-n diode, sub

threshold swing, tunnel field effect transistor (FET). TFET SRAMs,
ultra-low voltage, write-assist circuits.
INTRODUCTION
The introduction to the TFET is as follows, it includes its structure
and operation. A derivation of a band-to-band tunneling transmission
is carried out, and then the non-constant sub threshold swing of the
Tunnel FET is done, and some definitions are given. and then the
most important models used for the simulations in this thesis are
presented. The Small swing switches are introduced, and then in
particular, the Tunnel FET is described and its operation explained
and Finally, the history and state of-the-art of the Tunnel FET are
given. Tunnel field-effect transistor (TFET) device with the band-to-
band tunneling as the major current transport mechanism enables
steeper than 60 mV/dec subthreshold swing, and is considered as a
promising device to replace MOSFET device for ultra-low
voltage/power operation.
SRAM
Static RAM is a memory unit, capable of storing one bit
(logic0/logic1)at a time.Two inverters are cross-coupled to form a
basic SRAM.Most of the electronics devices are manufactured with
this memory units.
READ AND WRITE OPERATION
Write access to the cell occurs through the write access transistors
and from the write bitlines, BL and BLB. Read access to the cell is
through the read access transistor and controlled by the read
wordline, RWL. The read bitline, RBL, is given to read access.
Fig:8T SRAM CELL
Write Operation:
During write 1 operation, Transistor M5 turns-on by enabling the
write word line signal. When the Bit Line‟ is imposed to logic1, then
Q node starts charging and turns on Transistor M1 which cause to flip
Qbar node to logic 0. Now Qbar node helps enabling the Transistor
M4 which facilitates writing good logic 1 at Q node. On the other
hand, during write 0 operation, the Bit Line is imposed to logic 0 and
Transistor M5 turns-on by enabling write word line signal. The Q
node starts discharging and turns on TransisitorM2 which in turn
flipped Qbar node to logic 1. Now Qbar node helps turning Transistor
M3 on, which facilitates discharging Q node properly and
consequently logic 0 is obtained at Q node.
Read Operation:
Read operation is performed by using MOSFETs M6, M7 and M8.
Node Qbar is connected to the gates of M7 and M8. In this case, a
current flows.
 Fig. (a). Design of 8T SRAM Circuit using MOSFET
READ AND WRITE WAVEFORMS:
The read and write waveforms of 8T SRAM cell are shown in Figure
below. During the read the output is taken from read path and word
line remains active high during write operation the input is applied at
Bit Lines and WL is asserted. During hold the WL remains off and
cell is in idle state.
Fig. (b).Output Waveform
SIMULATION RESULTS:
The threshold voltage of pull down transistor is reduced by
connecting body of the transistor to the negative terminal. Threshold
voltage of only NMOS transistor is increased because increase in Vth
results in increase in delay. That is speed of the circuit reducesto a
greater extent. In first proposed work the pull up PMOS transistors
are stacked and threshold voltage of pull down transistors is increased
by reverse biasing its body. In second circuit pull down transistor is
reverse biased and read Bit line path NMOS and PMOS are fixed. In
third circuit both pull up transistor and read line transistors are
stacked and pull down.
DEVICE DESIGN:
In this work, we consider the PNPN type TFET for its capability to
achieve sub-threshold swing below 60 mV/dec at room temperature.
The device structures of the PNPN TFET, NPNP TFET are shown in
Fig. a.Double-gate (DG) InAS structures are used, with the gate
length 20 nm, silicon body thickness 5 nm, equivalent oxide
thickness 0.6 nm, the source/drain doping of 4*10 19 cm-3 (p+) and
6*1017cm-3(n+).The TFET circuits are analyzed using TCAD
simulations.The PNPN TFET device can be seen to have superior
current drive and sub threshold slope at very low gate bias.While at
high gate bias, the current drive of PNPN TFET device is inferior to
the MOSFET.
Fig:n-type TFET and p-type TFET
TFET:
The basic TFET structure is similar to a MOSFET except that the
source and drain terminals of a TFET are doped of opposite type .
A common TFET device structure consists of a P-I-N (p-
type, intrinsic, n-type) junction, in which the electrostatic
potential of the intrinsic region is controlled by a gate terminal.
.
Fig. Basic Schematic Of TFET
DEVICE OPERATION:
The device is operated by applying gate bias so that electron
accumulation occurs in the intrinsic region. At sufficient gate bias,
band-to-band tunneling (BTBT) occurs when the conduction band of
the intrinsic region aligns with the valence band of the P region.
Electrons from the valence band of the p-type region tunnel into the
conduction band of the intrinsic region and current can flow across
the device. As the gate bias is reduced, the bands becomes misaligned
and current can no longer flow.
Direct BTBT: In direct band to band tunneling,electrons travel across
valence band and conduction band without absorbing or emitting
phonon.This type of tunneling takes place in GaAS,InAs etc.
InDirect BTBT: In indirect band to band tunneling,electrons
undergoes a change in momentum as they travel from valence band
to conduction band due to the absorption or emission of phonon. This
type of tunneling takes place in silicon,germanium etc.
DESIGN OF TCAD:
TCAD [R] stands for technology computer aided design. It is a
design technique for semiconductor devices and involves computer
simulation strategies to develop 2D/3D devices and simulate their
characteristics. Industry driving producer of TCAD tools is Synopsys
and they provide both device and process simulation tools. Sentaurus
TCAD, the TCAD suite from the house of Synopsys offers
construction of device structures, simulation, meshing, electrical
characteristics visualization, performance parameter extraction., and
curve plotting.First and foremost step in device simulation
is making and meshing the device using Sentaurus device editor
(SDE). Output of this stage may be a script file of scm format. This
script file is then run utilizing sde -e -l .scm. when completion,
TCAD can generate the device structure. Extension of device
structure file is tdr. The tdr file is opened utilizing Svisual tool in
TCAD suite, to look at the device. Parameter file specific to the
device is to be further before simulation of electrical characteristics
of the device. Parameters like tunneling are outlined, within the
parameter file. Device characteristics are generated by running the
command sdevice des.cmd. A plot file (.plt). Characteristics of the
device is aforethought by gap the plt file utilizing Svisual.
A picturing of TCAD tool flow is given in Fig.
Table 1.Device parameter for NTFET AND PTFET
Parameter NTFET PTFET
device device
Source Doping Concentration
Drain Doping Concentration
Intrinsic Channel Doping
Concentration
Gate Length(nm)
Oxide Thickness(nm)
Radius of Silicon core
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parameters NTFET PTFET

Threshold voltage(vtn) 0.24652V
Ion 16.8607ohm
Ioff 9.16544*10-6 A
Ron 0.00002573A
Idsat 0.000108155A

CONCLUSION:

The proposed 8T SRAM cell can be very useful for ultra-low power
applications operating voltage of 0.1V with reduced delay. The con-
ventional 8T SRAM cell is modified in two ways to optimize power
and delay. First, 8T with Read assist technique and second, 8T
SRAM using two Extra pass transistors.

ACKNOWLEDGMENT:
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REFERENCES: