EDMOSFET Switching Device using Metal Field Plate Design
Ashvini Gyanathan1,*, Yunpeng Xu1, Amitha Susan Eapen1, Appu Mathew Varkey1, Ming Li1
and Jeoung Mo Koo.1
1
Technology Development (TD-VAS), GLOBALFOUNDRIES Singapore Pte. Ltd.
*
Phone: +65 66704216, Email: ashvini.gyanathan@globalfoundries.com
Abstract
This paper explores a low-cost method to improve
the Breakdown Voltage (BV) of a Switching
Device without compromising on the Source-
Drain Resistance (RDSON). This can be achieved
by introducing a metal field plate over the Gate
and the extended Drain region of the EDMOSFET.
This switching device shows negligible
degradation in current-voltage performance (i.e.
Drain Current in the linear region and saturation
region).
(Keywords: CMOS, High Voltage, EDMOSFET,
Metal Field Plate)
Introduction
The compromise between a sufficiently high BV
and a low RDSON is the primary design challenge
afflicting High Power Metal-Oxide-
Semiconductor Field Effect Transistor (MOSFET)
devices [1]. One method to improve the BV while
retaining low RDSON is to include a metal field
plate (MFP) which reduces the electric field in the
channel/drain region of the device [2]-[5]. In this
paper, the electrical performance associated with
the implementation of the MFP design, thereby
enabling a device with switching characteristics, is
explored.
Device Fabrication
The cross-sectional schematic of the switching
device is illustrated in Fig 1 ai) and aii). The
device structure is similar to that of a typical
Extended Drain MOSFET (EDMOSFET) with an
additional MFP on top of the gate. This MFP
encroaches on part of the drain region. Fig 1 b)
shows the Scanning electron microscopy (SEM)
image of the EDMOSFET switching device. The
MFP overhang is annotated in the SEM image.
978-1-5386-6508-4/19/$31.00 ©2019 IEEE 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
Device Performance
Figure 2 a) shows the RDSON versus the BV
trend for the EDMOSFETs with and without
MFPs. These points were plotted against the
theoretical Silicon limit of the RDSON versus BV
curve [6]. The NMOS MFP with implant tuning
design was also investigated and used for
comparison in this paper, since a further BV
improvement was observed. The increase in BV
does not significantly increase the RDSON for the
MFP design scheme. Figure 2 b) depicts the BV
improvement trend using a MFP design for the
NMOS and PMOS devices.
Figure 3 a) and b) depicts the improved BV
performance of the MFP devices as compared to
the devices without the MFPs. There is a marked
improvement in BV with the inclusion of the
MFPs (i.e. NMOS ~ 5V; PMOS ~ 3V). The MFP
result in a reduced electric field below the gate, on
the surface of the channel and along the drain
region of the EDMOSFET; thus, less ionic charges
are accumulated on the surface of the device,
leading to an increase in the BV [2]-[3].
The device with the MFP has similar Current-
Voltage (IV) characteristics as that without the
MFP. Figure 4 shows the drain current (ID) when
the drain voltage (VD) is biased at 0.1V, in the
linear operating region for both the a) NMOS
devices, as well as the b) PMOS devices. The
threshold voltages for both devices are similar.
The NMOS and PMOS devices with MFPs also
show similar IDLIN (ID at maximum VG with
Drain Voltage at 0.1V) values. This further attests
to the robust design of the MFP which increases
the BV without affecting the electrical
performance of the device. The IDLIN for the
NMOS device without MFP, on the other hand, is
about 4% higher than the NMOS device with the
MFP and Implant tuning. This could be attributed
to the higher doping levels in the drain-side of the
NMOS device to further enhance the BV.
Figure 5 depicts the electrical performance of ID
in the saturation region (IDSAT) with the VG
biased at 3.3V. In Figure 5 a) the IDSAT curve of
the NMOS device with and without the MFP dips
when it saturates at higher Drain Voltage (VD).
This slight dip in the IDSAT curve is associated
with the self-heating effect within the transistor at
higher VD. This self-heating effect is eliminated in
the device with the MFP and Implant tuning. The
slightly larger difference in the IDSAT values of
the NMOS devices (i.e. with/without MFPs versus
with MFP and Implant tuning) can be attributed to
the larger doping concentrations in the drain
region of the NMOS switching device.
The snapback performance of the switching device
shown in Figure 6, is measured at room
temperature (i.e. 25C). The optimal switching
functionality of the device with the MFP can be
determined from this snapback measurement
(highlighted in orange). At lower VG, the device
can operate at higher VD; whereas at higher VG,
the device exhibits similar operational
functionality as the device without MFP. This
snapback performance defines the switching
characteristics of the device.
Conclusion
This paper has demonstrated the distinct
improvements in BV with the metal field plate
design, while ensuring comparable electrical
performance to devices without the metal field
plates. A slight Implant tuning could also further
improve the BV without significant degradation of
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other current-voltage parameters of the NMOS
devices. This concept of introducing a MFP can be
translated to most high voltage devices as a
feasible solution for BV improvement.
References
[1] M.-R. Lee and O.-K. Kwon, “High Performance
Extended Drain MOSFETs (EDMOSFETs) with
Metal Field Plate,” International Symposium On
Power Semiconductor Devices & ICs 1999, 249-
252, doi: 10.1109/ISPSD.1999.764110.
[2] J. S. Fu, H.-C. Chiu, P.-Y. Ke, T.-H. Chen and
W.-S. Feng, “High-Performance 90-nm Dual-
Gate nMOSFETs With Field-Plate Technology,”
IEEE Electron Device Letters 2011 Vol. 32,
Issue No. 3, 291-293, doi:
10.1109/LED.2010.2102738.
[3] X. Luo J. Wei, X. Shi, K. Zhou, R. Tian, B.
Zhang and Z. Li, “Novel Reduced ON-
Resistance LDMOS With an Enhanced
Breakdown Voltage,” IEEE Transactions on
Electron Devices 2014 Vol. 61, Issue No. 12,
4304-4308, doi: 10.1109/TED.2014.2364842.
[4] N. Fujishima, M. Saito, A. Kitamura, Y. Urano,
G. Tada and Y. Tsuruta, “A 700V Lateral Power
MOSFET with Narrow Gap Double Metal Field
Plates Realizing Low On-resistance and Long-
term Stability of Performance,” International
Symposium On Power Semiconductor Devices
& ICs 2011, 255-258, doi:
10.1109/ISPSD.2001.934603.
[5] Z. Lin and X. Chen, “A New Solution for
Superjunction Lateral Double Diffused
MOSFET by Using Deep Drain Diffusion and
Field Plates,” IEEE Electron Device Letters
2015 Vol. 36, Issue No. 6, 588-590, doi:
10.1109/LED.2015.2421972.
[6] B. J. Baliga, “Modern Power Devices,” Wiley-
Interscience: New York, ISBN: 978-0471819868
(1987).
Fig. 1 – a) Cross-sectional schematic of both (i) NMOS and (ii) Fig. 2 – a) BV vs RDSON curve; b) Breakdown Voltage (BV)
PMOS switching devices; b) SEM cross-sectional images of the values of different NMOS and PMOS device schemes
EDMOSFET switching device

Fig. 3 – BV characteristics of typical EDMOSFETs with/without Fig. 4 – IDLIN characteristics of typical EDMOSFETs
MFPs for a) NMOS, and b) PMOS devices with/without MFPs for a) NMOS, and b) PMOS devices

Fig. 5 – IDSAT characteristics of typical EDMOSFETs Fig. 6 – Snapback performance of the EDMOSFET switching
with/without MFPs for a) NMOS, and b) PMOS devices device at 25C. The operating region for the device is
highlighted in orange.

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