GaN-based lateral and vertical devices:
physical mechanisms limiting stability and reliability
Gaudenzio Meneghesso, Matteo Meneghini, Carlo De Santi, Enrico Zanoni
University of Padova, Department of Information Engineering, via Gradenigo 6/B., 35131 Padova, Italy
Abstract
GaN-based devices are creating a technological
revolution and are expected to replace silicon
transistors for the development of high-efficiency
power converters. For this reason, a significant
research effort is being spent towards the fabrication
of high-performance and high-reliability GaN
transistors. Despite this, the reliability of GaN
HEMTs is still limited by a number of factors, that
can significantly reduce device lifetime and lead to
early failures. This paper presents an overview of the
physical processes responsible for the failure of GaN
transistors for power electronics, with focus on: (i)
degradation under off-state conditions; (ii)
degradation in semi-on conditions; (iii) degradation
in the on-state (positive gate bias). The results
presented here help understanding the most common
degradation modes of GaN devices and can be used
to improve manufacturing technology.
Introduction
GaN-based devices represent an excellent
opportunity for the development of the next-
generation power converters. Lateral GaN-on-Si
devices with a blocking voltage of 600-650 V are
already commercially available, and vertical GaN-
on-GaN diodes and transistors are being studied to
reach breakdown voltages above 1 kV.
GaN HEMTs are expected to be operated at much
harder conditions compared to the silicon counterpart,
thanks to the unique characteristics of GaN as a
semiconductor. The temperatures (>200 °C) and
fields (>3 MV/cm) are significantly higher than in
silicon transistors, and this represents a potential
issue for reliability. For this reason, studying the
reliability-limiting mechanisms of GaN devices is a
necessary step to ensure a rapid market penetration.
This paper summarizes our most recent results in the
field, by discussing the most relevant degradation
mechanism detected under off-state, semi-on state
and on-state stress.
Degradation processes under off-state stress
When lateral GaN devices are submitted to off-state
stress, a high field builds up in the gate-drain access
region and across the buffer layer. Both lateral and
vertical field can favor a time-dependent degradation
of the devices, thus leading to early failures.
We discuss here two relevant and representative case
studies. In the first case, lateral GaN HEMTs were
submitted to stress at high constant voltage (600 V)
in the off-state [1], [2]. During stress time, the onset
of a time-dependent failure was observed. Both soft-
and hard-failures were observed, leading to an
978-1-5386-6508-4/19/$31.00 ©2019 IEEE 2019 Electron Devices Technology and Manufacturing Conference (EDTM)
increase in gate leakage (Figure 1, left). To
understand the physical origin of failures, we
identified the location of the failed region by
electroluminescence and cross-sectioned the devices
by TEM (Figure 1, right). The results clearly
indicated that failure occurs in the silicon nitride
between the field plate edge and the drain terminal,
which is a high field region [3]. A short-circuit path
is created between the 2DEG and the gate-head,
leading to a sudden increase in gate leakage. The
results indicated that there is a strong correlation
between device lifetime and potential/field
distribution; an accurate optimization of the electric
field is a necessary step for achieving high reliability
transistors. The conclusions of this work were used to
propose an improved approach for the development
of reliable devices, i.e. the use of an additional graded
SiN passivation under the gate head. The role of SiN
properties was explored also in [4].
Figure 1: (left) Constant voltage stress performed on a representative
device at gate voltage = –5 V, drain voltage = 600 V, and source and
substrate grounded; (top right) Emission microscopy evaluated during
stress with VGS=–5V and VDS= 600 V; (bottom right) TEM performed
on a cross section corresponding to the hot spot. © [2017] IEEE.
Reprinted, with permission, from [1]
When devices are submitted to off-state bias, a
second process may take place: in fact, the large
drain-substrate voltage difference may lead to a
significant depletion of the buffer, with consequent
increase in the vertical electric field. Recently, we
demonstrated the exposure to high drain-substrate
bias can lead to a time-dependent vertical breakdown
of GaN-on-Si HEMTs. We carried out a set of step-
stress experiments, by increasing the voltage applied
on the drain while keeping the substrate grounded.
With increasing stress voltage, we measured a
substantial increase in the noise superimposed to gate
leakage current, followed by a catastrophic failure of
the samples [5]. Further measurements carried out
under constant vertical bias indicated that: (i) during
a constant voltage stress, vertical leakage is initially
stable, then it becomes noisy, indicating the
generation of defects. (ii) For longer times, failure is
reached, leading to the shortening of vertical stack.
(iii) time-to-failure (TTF) is Weibull-distributed.
Degradation was interpreted as follows: when a high
vertical bias is applied to the devices, a small leakage
current flows through bulk conduction and
dislocation-assisted processes. The buffer is deeply
depleted, and behaves as a leaky insulator, showing a
time-dependent breakdown process. Dislocations
may locally accelerate breakdown, due to the higher
vertical leakage. This process can limit the time-to-
failure of the devices, but is not a major limiting
factor. We recently demonstrated [5] that 200 V
devices can have a 20 years lifetime at 560 V with
1 % failure rate. TTF can be further improved by
reducing the density of defects in the vertical stack,
and by optimizing the electric field profile.
Figure 2: (left) Drain current monitored during a constant voltage
stress (VD=800 V); (right) TTF dependence on the drain voltage
applied at ambient temperature of 30 °C and 150 °C. Each point
represents the Weibull scale factor with a confidence level of 99%. ©
[2017] IEEE. Reprinted, with permission, from [5]
Degradation processes under semi-on state stress
Another critical operation regime is reached when the
transistors are operated in semi-on stress conditions
[6]. This is not a permanent operation regime, but a
condition which is crossed when the device is
switched. For instance, in a boost converter, when the
device goes from off-to on-state, the drain current
starts increasing before the drain voltage has dropped
to nearly 0 V (linear regime). As a consequence, there
is a short time-frame (few tens of ns) during which
high current and high voltage are both present. This
may enhance hot electron effects, resulting in
degradation and trapping processes that are not
present under off-state conditions. Several
approaches can be used to study the performance and
the reliability of GaN transistors under hard
switching. Two interesting approaches are the use of
an inductive load, as proposed by Tanaka et al. in [7],
and the tuning of gate and drain square-waves in
order to ensure a non-negligible overlap between the
two [7].
With reference to this second case, on one hand it
2019 Electron Devices Technology and Manufacturing Conference (EDTM)
overestimates the trapping effects, while on the other
hand it permits an accurate description of the pulsed
and electroluminescence characteristics of the
samples. To evaluate the impact of hot-electrons on
device performance, dynamic-Ron was evaluated as
a function of the overlapping between gate and drain
waveforms, by moving from a positive drain-gate
delay (DGD, soft switching) to a negative drain-gate
delay (hard switching). The results, summarized in
Figure 3, indicate that hard switching can induce a
measurable increase in dynamic-Ron. The magnitude
of this increase depends on the drain voltage applied
and on the duration of the overlapping between the
drain and gate waveforms (Figure 3 (a)).
Electroluminescence was used as a tool to prove the
role of hot-electrons in the analyzed mechanism
(Figure 3 (b)), and the following results were
obtained: (i) there is a strong correlation between the
increase in dynamic-Ron and the EL signal measured
during hard switching; (ii) at high temperatures, the
effect of hot-electrons becomes less prevalent, due to
an increased scattering. Strategies for minimizing
hot-electrons effects include the minimization of the
electric field (at device level) and the optimization of
the switching characteristics (at system level).
Figure 3: (left) ON-resistance dynamic variation plotted as a
function of the drain quiescent bias point (VDSQ) for several DGD
values. The dynamic change of the ON-resistance has a non-
monotonic trend with the VDSQ, showing a maximum for VDSQ = 300
V. (right) Correlation between the increase in the EL signal and the
increase in the dynamic ON-resistance with a low DGD value applied.
© [2017] IEEE. Reprinted, with permission, from [8]
Degradation processes under on-state stress
In on-state conditions, GaN devices are exposed to
low drain voltage; however, normally-off transistors
must operate with a positive gate bias when they are
on, and this may result in additional degradation
processes. Recently, several research groups studied
the degradation of GaN power devices submitted to
positive gate stress, to assess the stability of the gate
stack [9]–[15]. The main findings can be summarized
as follows: (i) insulated gate GaN transistors may
suffer from dielectric-related time-dependent failures
[16][17]. In addition, time-to-failure is Weibull-
distributed [17][16]. (ii) transistors with p-GaN gate
may suffer from a field-driven breakdown of the
metal/p-GaN Schottky junction, that was observed
under pulsed TLP testing; the same devices may
suffer also from a time-dependent breakdown, when
submitted to long-term constant voltage stress [18].
Results suggest the creation of a percolation path in
the AlGaN barrier, as indicated by recent studies [11].
A significant improvement in lifetime was achieved
through optimization of the barrier parameters [11].
(iii) vertical GaN devices based on MOS structure
may suffer from trapping and failure processes [19],
[20]. Failures have been found to occur above 7 V for
a 15 nm Al2O3 gate insulator, indicating a good
quality of the dielectric and interface (Figure 4, left).
On the other hand, negative and positive threshold
voltage shift have been ascribed respectively to the
de-trapping of electrons from the gate insulator and
to the injection of electrons from the 2DEG to the
insulator (Figure 4, right).
Figure 4: (left) Step stress performed with VDstress=0 V and by
increasing the VGstress by 0.25 V each 120 s of stress. (right)
Schematic representation of the two mechanisms responsible for
positive VTH shift (1), and increase of the SS at low
IDS (2) © [2018] IEEE. Reprinted, with permission, from [20]
Discussion and conclusions
GaN-based devices are expected to find wide
application in the power conversion industry. The
optimization of such devices is an exciting challenge,
and the scientific community has been recently
working for understanding the main reliability-
limiting mechanisms. Here we have presented an
overview of our most recent data on the processes that
limit the lifetime of GaN transistors, with focus on
failure under off-state conditions, degradation during
semi-on operation and stress under positive gate bias.
The results collected so far indicate that the stability
of GaN-based devices can be improved by
complementary process and epitaxy optimization.
Acknowledgments
This research activity was partly funded by 1) project
“Novel vertical GaN-devices for next generation
power conversion”, NoveGaN (University of
Padova), through the STARS CoG Grants call; 2) by
the Italian Ministry of Foreign Affairs and
2019 Electron Devices Technology and Manufacturing Conference (EDTM)
International Cooperation, "Direzione Generale per
la Promozione del Sistema Paese", through the Italy-
Japan bilateral project "MAGYGAN"; 3) by the
project InRel-NPower (Innovative Reliable Nitride
based Power Devices and Applications). This project
has received funding from the European Union’s
Horizon 2020 research and innovation programme
under grant agreement No 720527.
References
[1] I. Rossetto et al., “Field-Related Failure of GaN-on-Si HEMTs :
Dependence on Device Geometry and Passivation,” IEEE Trans. Electron
Devices, vol. 64, no. 1, pp. 73–77, 2017.
[2] I. Rossetto et al., “2DEG Retraction and Potential Distribution of
GaN-on-Si HEMTs Investigated Through a Floating Gate Terminal,”
IEEE Trans. Electron Devices, vol. 65, no. 4, pp. 1303–1307, 2018.
[3] M. Meneghini et al., “Extensive Investigation of Time-Dependent
Breakdown of GaN-HEMTs Submitted to OFF -State Stress,” IEEE Trans.
Electron Devices, vol. 62, no. 8, pp. 2549–2554, 2015.
[4] W. M. Waller et al., “Impact of silicon nitride stoichiometry on the
effectiveness of AlGaN/GaN HEMT field plates,” IEEE Trans. Electron
Devices, vol. 64, no. 3, pp. 1197–1202, 2017.
[5] M. Borga et al., “Evidence of Time-Dependent Vertical Breakdown in
GaN-on-Si HEMTs,” IEEE Trans. Electron Devices, vol. 64, no. 9, pp.
3616–3621, 2017.
[6] M. Meneghini et al., “Reliability and failure analysis in power GaN-
HEMTs: An overview,” in IEEE International Reliability Physics
Symposium Proceedings, 2017.
[7] K. Tanaka et al., “Reliability of hybrid-drain-embedded gate injection
transistor,” IEEE Int. Reliab. Phys. Symp. Proc., p. 4B2.1-4B2.10, 2017.
[8] I. Rossetto et al., “Evidence of Hot-Electron Effects During Hard
Switching of AlGaN/GaN HEMTs,” IEEE Trans. Electron Devices, vol.
64, no. 9, p. 3734, 2017.
[9] M. Meneghini, O. Hilt, J. Wuerfl, and G. Meneghesso, “Technology
and Reliability of Normally-Off GaN HEMTs with p-Type Gate,”
Energies, vol. 10, no. 2, p. 153, Jan. 2017.
[10] I. Rossetto et al., “Time-Dependent Failure of GaN-on-Si Power
HEMTs With p-GaN Gate,” IEEE Trans. Electron Devices, vol. 63, no. 6,
pp. 2334–2339, 2016.
[11] S. Stoffels et al., “Failure mode for p-GaN gates under forward gate
stress with varying Mg concentration,” IEEE Int. Reliab. Phys. Symp.
Proc., p. 4B4.1-4B4.9, 2017.
[12] M. Ťapajna, O. Hilt, J. Würfl, and J. Kuzmík, “Investigation of gate-
diode degradation in normally-off p-GaN / AlGaN / GaN high-electron-
mobility transistors,” Appl. Phys. Lett., vol. 107, p. 193506, 2015.
[13] A. N. Tallarico et al., “Investigation of the p-GaN Gate Breakdown
in Forward-Biased GaN-Based Power HEMTs,” IEEE Electron Device
Lett., vol. 38, no. 1, pp. 99–102, 2017.
[14] M. Tapajna, O. Hilt, J. Würfl, and J. Kuzmík, “Gate Reliability
Investigation in Normally-Off p-Type-GaN Cap/AlGaN/GaN HEMTs
Under Forward Bias Stress,” IEEE Electron Device Lett., vol. 37, no. 4,
pp. 385–388, 2016.
[15] T. Wu, D. Marcon, M. B. Zahid, M. Van Hove, S. Decoutere, and G.
Groeseneken, “Comprehensive Investigation of On-State Stress on D-
Mode AlGaN / GaN MIS-HEMTs,” IEEE Int. Reliab. Phys. Symp., p.
3C.5.1, 2013.
[16] T. Wu et al., “The impact of the gate dielectric quality in developing
Au-free D-mode and E-mode recessed gate AlGaN / GaN transistors on a
200mm Si substrate,” Proc. 27th Int. Symp. Power Semicond. Devices
IC’, pp. 225–228, 2015.
[17] S. Warnock and J. A. del Alamo, “Progressive Breakdown in High-
Voltage GaN MIS-HEMTs,” Reliab. Phys. Symp. (IRPS), 2016 IEEE Int.,
pp. 4–9, 2016.
[18] I. Rossetto et al., “Field- and current-driven degradation of GaN-
based power HEMTs with p-GaN gate: Dependence on Mg-doping level,”
Microelectron. Reliab., vol. 76–77, pp. 298–303, 2017.
[19] M. Ruzzarin et al., “Instability of Dynamic- RON and Threshold
Voltage in GaN-on-GaN Vertical Field-Effect Transistors,” IEEE Trans.
Electron Devices, vol. 64, no. 8, 2017.
[20] M. Ruzzarin et al., “Degradation of vertical GaN FETs under gate
and drain stress,” in IEEE International Reliability Physics Symposium
Proceedings, 2018, p. 4B.1-1-4B.1-5.