Microelectronics Reliability 126 (2021) 114211

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Improved HV-H3TRB robustness of a 1700 V IGBT chip set in standard

power modules
J.-H. Peters a, *, M. Hanf a, S. Clausner a, C. Zorn b, N. Kaminski a
a
Institute for Electrical Drives, Power Electronics, and Devices, University of Bremen, 28359 Bremen, Germany
b
ForWind - Center for Wind Energy Research, University of Bremen, 28359 Bremen, Germany

A R T I C L E I N F O A B S T R A C T

Keywords: High Voltage-High Humidity High Temperature Reverse Bias (HV-H3TRB) is the standard to test power modules
HV-H3TRB for humidity driven degradation. This test has contributed significantly to detect and fix weak points in device
Power modules designs, especially of the junction termination. Thus, the latest junction termination designs offer unprecedented
Reliability
humidity robustness. This work reports on a comparative HV-H3TRB test on 1.7 kV IGBT modules with chips sets
Humidity
Moisture
of two consecutive generations tested at two different test voltages each. The progress in the chip design and
material composition provides more than an order of magnitude better performance in HV-H3TRB. Failure an­
alyses have indicated vastly reduced degrees of aluminium corrosion in the junction termination area, leading to
a slowed down failure mechanism.

1. Background 1.1. Accelerated testing

Power semiconductor devices are conquering more and more fields
of application. Besides handling high electrical and thermal loads, the
devices have to operate reliably, even under harsh environmental con­
ditions. This includes warm and humid climate, although the vast ma­
jority of devices is not hermetically sealed (see Fig. 1). Consequently,
high humidity raises the risk of performance degradation and failures in
application. Depending on the application, humidity might even show
up under the significant failure reasons [1].
The most humidity sensitive area of a power semiconductor is the
chip’s junction termination (JT) area, which can suffer from charge
accumulation, metal corrosion as well as decomposition of the insulator
structure when biased. In general, the JT optimises the electric field
distribution at the surface by spreading out the space charge region.
Damages introduced on the surface lead to an uneven field distribution
in the chip volume below, hence, causing very localised over-stress.
Consequently, humidity-induced failure mechanisms deteriorate the
blocking characteristics of power semiconductors, either by increased
leakage currents or decreased blocking capability, i.e. premature
avalanche, if not flash over.
In order to estimate the useful lifetime of their power devices,
manufacturers perform accelerated tests by exposing the devices to
much harsher conditions than the devices would encounter in the field.
Well-designed tests can find failures within e.g. 1000 h, which would
occur only after decades of field operation. The test of choice to find
humidity driven degradation in power semiconductor devices is the
High Voltage-High Humidity High Temperature Reverse Bias (HV-
H3TRB). In decades of application to power devices, the HV-H3TRB has
contributed significantly to detect and fix weak points in the device
design, especially of the JT [2–6]. In an HV-H3TRB, power semi­
conductor devices are biased with at least their usual DC-link or pref­
erably higher voltage, while stored in a climate chamber at typically
85 ◦ C and 85% relative humidity (“85/85”). The test duration for a
qualification test is usually 1000 h, while for scientific purposes an end-
of-life test is preferred.
The leakage current monitoring during the HV-H3TRB provides a
first impression about the state-of-health of a power device, but is not
precise enough for a detailed analysis. The blocking characteristics,
especially the avalanche behaviour and the reduction of the avalanche
voltage over time are more accurate to investigate and separate failure
modes and mechanisms. However, to obtain a precise blocking curve at
room temperature, the modules need to be dried to establish a micro-

* Corresponding author.
E-mail address: j.peters@uni-bremen.de (J.-H. Peters).

https://doi.org/10.1016/j.microrel.2021.114211
Received 7 June 2021; Accepted 17 June 2021
Available online 11 October 2021
0026-2714/© 2021 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
J.-H. Peters et al.
Fig. 1. Schematic of an IGBT module. Humidity intrudes by diffusion or creeps
along interfaces (blue arrows). With respect to moisture, the chips’ JT handling
the high electric fields are the most delicate spots. (For interpretation of the
references to colour in this figure legend, the reader is referred to the web
version of this article.)
climate inside comparable to the initial state [7,8]. Admittedly, this has
an impact on the progress of the degradation.
1.2. Design of experiment
Recent HV-H3TRB tests have revealed a general progress in moisture
performance of latest power modules compared to their predecessors
[2,3]. In order to confirm the effectiveness of the latest improvements
with respect to humidity robustness, 1.7 kV IGBT modules with different
chip technologies were tested in HV-H3TRB. Within the first test, a total
of 24 650 A PrimePACK™ 2 modules (FF650R17IE4), featuring an
improved JT design, were biased at 65% of the nominal voltage level
Vnom (Pi65, 16 pcs), and 80% Vnom (Pi80, 8 pcs), respectively. The bias
split was meant to investigate a voltage acceleration observed in HV-
H3TRB before [7,8]. For comparison, another 16 1.7 kV, 650 A Prime­
PACK™ 2 modules, equipped with the standard IGBT4 chip design, were
tested in a second test at the same two voltage levels (Ps65 8 pcs and
Ps80 8 pcs). The entire split chart is given in Table 1.
The stress profile shown in Fig. 2 represents the applied test pro­
cedure. The climatic conditions of 85/85 are slowly built up within 1 h
and kept constant for 24 h, before the bias is applied to the DUTs
(moderate ramp-up) and the effective test time starts to elapse. From
then on, the leakage current is continuously logged and monitored. To
avoid a massive destruction of the DUTs at failure, they are disconnected
from the high voltage within microseconds, in case the leakage level
exceeds 10 mA.
In order to investigate the ongoing degradation of the modules even
closer than the leakage monitoring allows, intermediate blocking curve
measurements (IM) were carried out after certain time intervals (50 h,
150 h, 300 h, …). To achieve reasonable blocking measurements com­
parable to the initial state and to reduce the risk of arcing due to
remaining moisture inside the modules, a drying procedure of 50 ◦ C and
10% rh was applied for 24 h (cf. Fig. 2) previous to the IMs. The fail
criterion applied to the blocking characteristic was exceeding 3 μA
below 1.7 kV. In this HV-H3TRB, only one switch of the half-bridge
configuration was connected to the test voltage each. Thus, each un­
connected switch served as a chamber reference to determine the in­
fluence of temperature and humidity without voltage applied to the
chips.
Table 1
Test splits and voltage conditions during the HV-H3TRB tests.
Test Split Package Chips Test voltage DUTs
1 Pi65 PrimePACK™ 2 Improved 65% Vnom/1105 V 16 pcs.
1 Pi80 PrimePACK™ 2 Improved 80% Vnom/1360 V 8 pcs.
2 Ps65 PrimePACK™ 2 Standard 65% Vnom/1105 V 8 pcs.
2 Ps80 PrimePACK™ 2 Standard 80% Vnom/1360 V 8 pcs.
2
Microelectronics Reliability 126 (2021) 114211
Fig. 2. Climate profile and procedure for HV-H3TRB.
2. HV-H3TRB results
2.1. Standard chip technology
Fig. 3 shows the leakage current monitoring of Ps65/80 devices
during the HV-H3TRB and reveals for the Ps80 devices either a sudden
breakdown (DUT3) with little oscillations before the failure event or an
increase of the leakage current over time (DUT2), which would most
likely lead to a shutdown of the respective test-channel due to even
further increasing leakage currents on continuation of the HV-H3TRB.
DUT1 exhibits an increasing amplitude of the oscillations over the tested
time with an increased leakage current. The noise of a few microampere
at the beginning of the test (up to roughly 700 h) is due to the capability
limit of the logging system, while the later oscillations are a result of
electro-chemical reactions responsible for the humidity driven degra­
dation [9]. In contrast, DUT4, typical for split Ps65, shows neither a
catastrophic failure nor an increasing leakage current after 1300 h in the
HV-H3TRB.
Fig. 4 shows the blocking curves of Ps80/DUT3 achieved after
designated testing times. The measured results indicate an initial
reduction in the blocking capability already becoming detectable at the
first IM after 47 h. For the time being, the blocking capability remains at
this value until it decreases below the nominal voltage of 1.7 kV after
708 h. Depending on the JT-design, generally two different modes of
blocking degradation are found: 1. increasing leakage at fixed voltage
and/or 2. decreasing avalanche inception voltage at fixed current
(premature avalanche) [7]. For all Ps65/80-DUTs the later behaviour
can be observed. DUT3 failed catastrophically after 772 h with a
remaining blocking capability of less than 300 V.
In case of the split Ps65, none of the devices failed catastrophically in
HV-H3TRB within the tested time of 1300 h, but the blocking curves
Fig. 3. Leakage monitoring of Ps65/80 DUTs in HV-H3TRB documenting one
sudden breakdown (DUT3) and increasing leakage current over time (DUT1
& DUT2).
J.-H. Peters et al. Microelectronics Reliability 126 (2021) 114211

Fig. 4. Blocking curves of DUT3, a Ps80 device, measured up or 3 μA with Fig. 6. Blocking curves of a Pi80 device, measured up to 3 μA with temperature
temperature impact on leakage compensated. Blocking capability reduces over impact on leakage compensated. Even after a testing time of more than 4000 h,
time to under the nominal voltage of 1.7 kV at the last measurement. the blocking voltage is only slightly reduced and remains well above the
nominal voltage of 1.7 kV.
show an initial reduction of the blocking capability. The devices of the
Ps80 split started to fail after only 800 h and after 1300 h 5 out of 8
devices had failed. Subsequent blocking curve measurements confirmed
catastrophic failures as all of these modules had a remaining blocking
capability of below 300 V. Additionally, the surviving modules of Ps80
have a reduced blocking capability below 1.7 kV.

2.2. Improved junction termination

In contrast, the modules of split Pi65 survived 5300 h effective test

time with 65% Vnom applied and the ones of split Pi80 survived 4100 h
with 80% Vnom. An example of the leakage current monitoring of these
two splits is shown in Fig. 5 and reveals neither a catastrophic failure
event nor an increase in the leakage level, but only measurement noise
of a few 10 μA. However, there was one unexplained early failure (in
Pi80 after about 15 h, removed from statistics). This excellent stability is
also confirmed by the intermediate blocking measurements, which show
a breakdown voltage only slightly decreasing over time (cf. Fig. 6). The
remaining blocking capability of only two modules (one Pi65 and Pi80
each) falls below the nominal voltage of 1.7 kV and this happens only
after more than 3000 h.
To compare the remaining blocking capability of both chip sets, the
breakdown voltages of the modules were extracted at a threshold of 2 μA
for each intermediate measurement. For modules which did not reach
that leakage level, the voltage value of the last data point was taken
instead. The median as well as upper and lower quartiles of these values Fig. 7. Comparison of the remaining blocking capability. Blocking voltages of
are plotted in Fig. 7. After a few hours already, both the Ps65 and Ps80 intermediate measurements at a threshold of 2 μA or last voltage datapoint of
splits show a drop in their remaining blocking capability, most probably all DUTs compared. Enlarged first 500 h tested time, voltage dependency of the
initial drop for Ps65/80. Z65/90 from [8].

Fig. 5. 85/85 leakage monitoring of Pi65 and Pi80. The higher leakage current
level of the Pi65 is due to two modules connected in parallel per channel, no
failure events of increasing leakage current observable.
due to ion movement on the chip surface [4]. In this experiment, even
the initial loss of blocking capability appears to be voltage-dependent.
As illustrated in Fig. 7, the remaining voltage level of split Ps80 is
lower compared to Ps65 in the first three IMs. With the intermediate
measurement 5 (Table 2), the Ps80 devices start to fail and the
remaining blocking capability is drastically decreasing. Then, all devices
fail within a short time window, so that one dominant failure mecha­
nism can be assumed. Compared to Ps80, the modules of Ps65 start to
drop with a delay and the blocking curves of two devices drop below the
nominal voltage at IM 6 and 7, respectively (see Table 2), but the tested
time was not sufficient to produce first catastrophic failures.
In [7], the equation for the acceleration factor in humidity testing
[10,11] was extended by a voltage acceleration factor, of which the y-
component has to be determined empirically:

3
J.-H. Peters et al. Microelectronics Reliability 126 (2021) 114211

Table 2
Summarized IM results achieved on the Ps65/80.
IM Cumulated Fail criteria Fail criteria Catastrophic fail
no. test-time/h Ps65 (V < Ps80 (V < criteria Ps80 (V <
Vnom) Vnom) 300 V)

0 0 0/8 0/8 0/8

1 47 0/8 0/8 0/8
2 143 0/8 0/8 0/8
3 285 0/8 0/8 0/8
4 544 0/8 0/8 0/8
5 708 0/8 1/8 0/8
6 1017 1/8 7/8 4/8
7 1297 2/8 8/8 5/8

( )x ( [ ] ) ( )y
RHa EA 1 1 Va
af (RH, T, V) = ⋅exp ⋅ − ⋅ (1)
RHu k Tu Ta Vu
To get an idea about the course of Ps65, two data sets of [8] of 1.2 kV
modules and test voltages of 65% Vnom (Z65) and 90% Vnom (Z90) are
added in Fig. 7. The voltage drops of Ps80 and Z90 around 1000 h are
nearly the same and the behaviour of Ps65 and Z65 might be similar.
Therefore, if the two points at about 90% of the normalised blocking
voltage, for Ps65 at 1297 h and Ps80 at 708 h, are taken, a factor of 1.83
for the voltage acceleration can be extracted. This leads to a y-exponent
of 2.91. This value is in reasonable agreement with the acceleration
factor of 2.1 and y-exponent of 2.2 in [8] for 65% Vnom and 90% Vnom
respectively. The difference between the values can be explained by the
rather inaccurate estimation of the acceleration factor from the device
drops and the different remaining blocking capability of 90% in this
paper and 75% in [8] taken for the extraction.
By contrast, the modules of the Pi65 and Pi80 splits show no initial
drop and carry on for more than 4000 h. The blocking voltage starts to
drop slightly from ca. 3000 h onwards, but the time until a significant
degradation is at least an order of magnitude longer than with Ps65/80.
Furthermore, no influence of the test voltage can be observed anymore,
at least not within the tested time.

3. Failure analyses

The good agreement between the Z65/90 and Ps65/80 data suggests
that aluminium corrosion, which was determined to be the predominant
failure mechanism in [8], is the main degradation mechanism for Ps65/
80 as well. Directly after the final blocking characterisation, three of the
five failed devices of the Ps80 split were subjected to failure analysis. In
subsequent steps after module decapsulation, the failed substrate as well
as the damaged chips on it were identified and disconnected. After­
wards, the silicone gel was removed by a non-chlorinated silicone rub­
ber remover (ARDROX 2312) accelerated by higher temperature and
storing the modules upside down in a stainless-steel basin on a motion
table. After the first microscopic inspection, the remaining polyimide
serving as the top hard passivation layer on the JTs was removed by
plasma etching to prevent further material decomposition, e.g. etching
of aluminium. The result is shown in Fig. 8.
Optical inspection revealed no visible aluminium corrosion spots on Fig. 8. Optical analysis of the JT after silicone gel and polyimide removal, top:
the JTs of the chamber references (Fig. 8a). On the contrary, without detail of Ps80 diode JT without bias (chamber reference), middle: detail of Ps80
applied voltage during HV-H3TRB the chips look almost pristine. diode JT with bias applied, bottom: Pi80 IGBT JT with bias applied. All pictures
In contrast to that, all JTs of Ps80 diode and IGBT chips show dis­ roughly to the same horizontal scale. The chip edge is to the top, active cells to
the bottom.
colorations and corroded spots (Fig. 8b). The burn mark at the outer part
of the JT indicates one of the failure spots of the module, which caused
the reduced blocking capability of DUT3. For all modules analysed, corrosion of Al field plates is one of the most common moisture-driven
aluminium corrosion could be confirmed as the main failure mechanism. degradation mechanisms in power modules [7,8,12] and design im­
Unfortunately, just omitting aluminium is not an option. It is by far provements have to take care of this part of the JT.
the most commonly used material for the chip metallisation, as it allows Thus, the design improvements for the Pi splits concern the JT layout
for creating an ohmic contact on both p- and n-doped Si. An Al metal­ and material composition. One Pi65 module with a reduced blocking
lisation provides good electrical, but above all excellent mechanical voltage under 1.7 kV after more than 3700 h of tested time were ana­
properties. Its amorphous structure promotes adhesion between semi­ lysed. Only one small spot on an IGBT chip showed signs of flashovers
conductor, dielectric insulator, and the soft-mould. Consequently, the and seems to be the cause for the reduced blocking capability. However,

4
J.-H. Peters et al.
the origin of this spot is unclear and it was not related to aluminium
corrosion. In fact, the JTs of the Pi65/80 modules contain less
aluminium, which results in the absence of aluminium corrosion even
after such a long-testing time, with none of the JT (extracted area in
Fig. 8c) show any discolouration or corrosion traces but look pristine.
In other words, the main failure mechanism for these modules seems
to be no longer aluminium corrosion. Therefore, the known lifetime
model with its estimation of acceleration factors based on aluminium
corrosion is no longer valid or at least lost its physical justification. Thus,
it still might serve as a purely mathematical fit or has to be replaced
altogether.
4. Conclusions
The ambient humidity is one important factor to estimate the useful
life or predict the remaining lifetime of power modules [13] and the HV-
H3TRB is the primary test for humidity driven degradation in such
power modules.
Recent test results revealed a general progress in the humidity
robustness of power modules. The tests and results discussed in this
work confirm the ongoing improvements, but go significantly beyond.
While standard 1.7 kV chips failed during a highly accelerated HV-
H3TRB test (80% Vnom) around 1000 h, the same standard modules with
an improved chip set lasted for more than 4000 h in that test.
The detailed analysis of the remaining blocking capability showed
that the improved chip set offers at least an order of magnitude better
performance in the HV-H3TRB test and that the dependence on the
applied voltage, observed previously and with the Ps65/80 split, is no
longer present. Thus, under usual mission profiles humidity related field
failures of power modules should no longer be an issue. In addition,
these improvements could be an explanation for the unexpectedly good
performance of SiC devices in HV-H3TRB tests, which should have been
inferior to silicon devices because of their smaller dimensions and high
electric fields, but were even superior [14,15].
However, extreme environments or extreme events causing e.g.
condensation inside power modules especially under the silicone gel
layer might still put the modules at risk [16] and the impact of such
operation condition has to be investigated further [17] and quantified
by advanced humidity test methods.
Declaration of competing interest
The authors declare that they have no known competing financial
Microelectronics Reliability 126 (2021) 114211
interests or personal relationships that could have appeared to influence
the work reported in this paper.
Acknowledgements
This work has been funded by the German Federal Ministry for
Economic Affairs and Energy (BMWi) under grant 0324336C.
Special thanks go to Infineon Technologies AG for providing the
modules and supporting the failure analyses.
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