Design and Analysis of Multi-Channel Junctionless

Nanowire Transistor
Asiful Hoque Mohammad Rabib Hossain Md. Mohsinur Rahman Adnan
Dept. of Electrical & Electronic Dept. of Electrical & Electronic Dept. of Electrical & Electronic
Engineering Engineering Engineering
Shahjalal University of Science and Shahjalal University of Science and Shahjalal University of Science and
Technology Technology Technology
Sylhet-3114, Bangladesh Sylhet-3114, Bangladesh Sylhet-3114, Bangladesh
bnhasif@gmail.com rabibhossain@gmail.com mmradnan-eee@sust.edu

Abstract— Absence of p-n junctions and associated electrical
drawbacks coupled with the ease of fabrication of multi-gate
(MG) architectures have rendered junctionless transistor (JLT)
a promising candidate for future very large scale integrated
(VLSI) circuits. Throughout this paper, we have presented a
comparative analysis on the performance of multi-channel
Junctionless transistor. Performance parameter named Drain
Current (ID), Threshold Voltage (Vth), Subthreshold Swing (SS),
on state and off state current ratio (Ion/Ioff) for the multichannel
structures of n-type Junctionless transistor are analyzed.
Variation of different device parameters such as oxide thickness,
channel length etc. make effect on device performance which
have been investigated. In order to observe Short Channel
Effects (SCEs), the above parameters were investigated. Impact
of Variation of insulation between multiple channels on the
performance of the device also has been explored.
Keywords— junctionless nanowire transistor, multiple
channel structure, short channel effects, interaction, DIBL,
Ion/Ioff ratio , threshold voltage Roll Off, silvaco TCAD
I. INTRODUCTION
The Junction less Nanowire Transistor (JLNT) operates in
the similar principle to a conventional MOSFET device in
spite of having no proper p-n junction in its structure [1]. The
device is proposed in the recent past [2]. The transistors which
are now existing are semiconductor junction based and PN
junctions most of the time. When the MOS devices enter into
the nanoscale region, these PN junctions require heavily high
doped density gradients. There arise some problems which is
the reason of invention of JLNT. For the laws of diffusion and
the nature of statistical distribution atoms in the
semiconductor device, ultra-shallow junctions’ formation
with high doping concentration has become an increasingly
troublesome task for the industry of semiconductor. Novel
techniques of doping and ultra-speedy annealing techniques
must be developed. To overcome these problems, the idea of
JLNT is magical.
Junctionless transistors (JLTs) have been proposed to
improve the electrical performance of conventional field
effect transistors (FET) devices [3,4]. In JLTs, the source-
channel-drain doping profile is similar. Therefore, the device
can be considered as a resistor with two terminals in which a
third terminal (gate) modifies the current flows through the
channel section. In addition to a simpler structure and
fabrication process, other advantages of JLTs such as high
ON/OFF current ratio, lower leakage current, lesser sub-
threshold slope, low frequency noise and variability were
reported in the literature [5-9]. The first junctionless proposed
was principally n-type highly doped gated resistor device [10].
Single n-Channel Junctionless Nanowire Transistors and n-
Type Poly-Si Junctionless Nanowire Transistor are also
amongst the ON channel n-type junctionless devices which
have been recently introduced [11,12]. The junctionless
transistors were principally turned off based on the depletion
of the channel by electric field induced by the gate which
mainly can be achieved with shrinking the channel size.
Multi-gate three-dimensional (3D) metal–oxide–
semiconductor field-effect transistors (MOSFETs) are
considered as having a most promising structure, which is
likely to push the limits of silicon integrated circuits beyond
the bound of classical planar technologies. [13,14] Compared
with the gate in traditional planar field-effect transistors, the
gate in a multi-gate FET surrounds the conductive channel in
different directions to obtain a good control of the conductive
channel. [15] Consequently, the advantages of the device
structure are obvious in reducing short channel effects and
leakage currents. [16] However, in extremely short-channel
devices (L= 10 nm or less), the fabrication of an ultra-sharp
doping concentration gradient p–n junction between
source/drain and channel requires an extremely complex
manufacturing process. Recently, the junction less nanowire
transistor (JNT) has been proposed to provide an alternative
to simplify the fabrication process. Above the gate threshold
voltage, the conductive path first emerges in the center of the
nanowire and then gradually expands to the whole nanowire.
This property provides an opportunity to study the
quantum transport characteristics of one-dimensional
(1D) structures in silicon material. It has been reported
that JNTs show clear current oscillations at lower
temperature below 70K and more marked conductance
oscillations than the inversion-mode devices due to
quantum confinement characteristics. [17] Due to the
requirements of high current controlling device and better
short channel effects multi-channel JLTs are needed over
single channel JLT. In this paper, we report comparative
characteristics in single and multiple n-channel JNTs. We
try to present the different behaviors of drain current in
single and multiple-n-channel JNTs as well as different
insulating material in between channel. Figure 1
illustrates the diagram of multichannel Junction less
transistor and Figure 2 illustrates the diagram of the
transistor without gate to have a clear view of the
multichannel structure. Comparative performance study
of this structure is elaborately described.
 II. DEVICE MODELING AND SIMULATION SETUP
To characterize the electrical characteristics of the device,
simulator TCAD Silvaco Atlas is used. [18] Different parameters
and variables were used for the simulation. By varying channel
length and oxide thickness, the simulation was carried out. But in
all cases, the doping concentration is kept fixed. For each
simulation, gate voltage was varied to find threshold voltage and
electrical characteristics keeping source and drain voltage
constant. For device modeling, CVT(Lombardi CVT model)
approach had been used in ATLAS simulator. CVT model is
defined by a Complete model including N, T, E// and 𝐸⊥
effects.
optical intervalley phonons. The third component, µsr, is the
surface roughness factor. The CVT model when activated will
also, by default, apply the parallel electric field mobility
model. In this model the low field mobility is supplied from
the CVT model.
An n-channel structure formed with a gate electrode of p-
type polysilicon. SiO2 was used as the gate oxide. Uniform
doping concentration of 1019cm-3 was selected for the
devices.
III. RESULTS AND DISCUSSIONS

A. Simulation Parameters

TABLE I
SIMULATION PARAMETERS

Channel Channel Oxide Channel

Length, Doping, Thick Thick
Lg(nm) cm-3 ness, ness,
Tox(nm) Tsi(nm)
Fig. 1 3D layout of multichannel junctionless transistor 10 1019 1,1.5 5
15 1019 1,1.5 5
20 1019 1,1.5 5

B. I-V Characetristic

Fig. 2 3D layout of multichannel junctionless transistor without gate

In all the structures the same approach (CVT) was
performed. To obtain accurate results for MOSFET
simulations, it is necessary to account for the mobility
degradation that occurs inside inversion layers. The
degradation normally occurs as a result of the
substantially higher surface scattering near the semiconductor
to insulator interface. This effect is handled within ATLAS by
specific inversion layer mobility models CVT. The CVT model
is designed as stand-alone models which incorporate all the
effects required for simulating the carrier mobility. The
inversion layer model from Lombardi [18]overrides any other Fig. 3 Id Vs Vg curve for Tox=1.5nm, Vds=1V
mobility models which may be specified on the Atlas
statement.[18] In the CVT model, the transverse field,
doping dependent and temperature dependent parts of the
mobility are given by three components that are combined In Figures 3 & 4, The electrical transport characteristic of
using Mathiessen’s rule. These components are µAC, µsr multichannel junction less transistor has been illustrated.
and µb and are combined using Mathiessen’s rule as follows:

-1
μ-1 -1 -1
T =μAC +μb +μsr (1)

The first component, µAC, is the surface mobility limited

by scattering with acoustic phonons. The second mobility
component, µb, is the mobility limited by scattering with
 Fig. 6 Vth Vs Lg curve for different Lg, Tox =1.5nm, Vds=1V & 1.5V

reducing the oxide thickness. The threshold voltage of a

MOSFET can be reduced by reducing the channel length.
There’s a popular effect called the short-channel effect,
Fig. 4 Id Vs Vg curve for different Tox, Lg=10nm, Vds=1V where the channel length is of the same magnitude of the
depletion region widths near the source and drain junctions.
C. Threshold Voltage For a long channel device, the depletion region near the gate
is much larger than the depletion regions near the source and
In this section, the simulation outputs are tabulated to get a the drain. Hence, the threshold voltage to be applied should
proper insight. be of enough magnitude to create an inversion region by the
migration of charge carriers. Since the oxide acts as an
TABLE II
insulator between the gate terminal and the inversion layer of
charge below the oxide, decrease of the oxide thickness
Threshold Voltage Variation with Channel Length and Oxide Thickness
increases the capacitance between the gate and the substrate.
Again, greater the capacitance, more will be the accumulation
Channel Oxide Threshold Voltage, Vth(V) of charge. Hence, more charge accumulation in the channel
Length,Lg Thicknes Vds= 1V Vds= 1.5V (due to lesser oxide thickness), with all other conditions
(nm) s, remaining constant, indicates lesser threshold voltage
Tox(nm) required to attain the same inversion.
10 1 1.44994 0.75
1.5 1.11 0.307 D. DIBL
15 1 2.11793 1.70055 TABLE III
1.5 1.926 1.448 DIBL Variation with Channel Length and Oxide Thickness
20 1 2.2389 1.9641 Multi Channel Oxide DIBL,
1.5 2.174 1.825 channel Length, Thickness, (mV/V)
Junction Lg(nm) Tox(nm)
In figure 5 & 6, the threshold voltage characteristic is less
visualized. To determine threshold voltage, the constant Transistor 10 1 1.400962
current method is applied. Varying channel length, keeping
1.5 0.855
work function, doping concentration, and other parameters
as constant, the threshold voltage increases. There are two 15 1 0.83474
main ways by means of which the threshold voltage can be 1.5 0.71172
reduced in a MOSFET; reduction of channel length and 20 1 0.54966
1.5 0.40712

Fig. 5 Vth Vs Lg curve for different Lg, Tox =1nm, Vds=1V & 1.5V Fig. 7 DIBL Vs Lg curve for Tox = 1nm & 1.5nm
In Figure 7, DIBL curve is shown. The change of threshold F. Subthreshold Swing
voltage over gate voltage variation is low. As there is
no junction in JLNT, the threshold voltage for different
drain voltage shows nearly stable threshold voltage. And TABLE V
Subthreshold Swing Variation with Channel Length and Oxide
the graph shows decrements over the increment of channel Thickness
length. Besides as DIBL concerning for lower channel length
device, when channel length decreases then drain and source Channel Oxide Subthreshold
voltages increases gradually. Because of source voltage Length, Thickness, Swing
lower than drain voltage, it causes field penetrations. It results Lg(nm) Tox(nm) (mV/dec)
in greater electron injection from the source. Vds= 1V Vds= 1.5V
E. Ion/Ioff ratio 10 1 .149 .157
1.5 .104 .137
TABLE IV 15 1 .0286 .039998
Ion/Ioff Ratio Variation with Channel Length and Oxide
Thickness 1.5 .0375 .0432
20 1 .0250 .02989
Channel Oxide Ion/Ioff 1.5 .034 .03177
Length, Thicknes Ratio
Lg s, Vds= 1V Vds= 1.5V
(nm) Tox(nm)
10 1 4.81e4 5.35e2
1.5 4.659e2 17.1661
15 1 2.03e14 2.24e12
1.5 7.06e8 6.33e8
20 1 5.89e22 1.00265e21
1.5 2.7337e18 4.832e16

Fig. 10 SS Vs Lg curve for Tox = 1nm, Vds = 1V and 1.5V

Fig. 8 Ion/Ioff Vs Lg curve for Tox = 1nm, Vds = 1V and 1.5V

Fig. 11 SS Vs Lg curve for Tox = 1.5nm, Vds = 1V and 1.5V

In figure 10& 11, it is observed that the subthreshold swing

Fig. 9 Ion/Ioff Vs Lg curve for Tox = 1.5nm, Vds = 1V and 1.5V
In figure 8 & 9, it is shown that Ion/Ioff ratio linearly increased
by increasing channel length. Because of increasing channel
length, the number of the carrier also increased in the channel
region. As a result, drain current increases and this linear
change happens with channel length variation.
curve decreases with increasing channel length. In this figure,
subthreshold swing shows better results except for the 10nm
channel length structure. Smaller lateral gate length makes the
gate electrode lose horizontal control on the potential of the
channel body. [19] Therefore, it has the worst subthreshold
characteristics compared to other devices. In the OFF state
(positive gate voltage), the leakage current is also higher with
smaller Lg mainly due to the incapability of the gates to
control the carriers inside the channel. As it can be seen, the
subthreshold swing (SS) decreased from 28.6 mV/decade in
the device with 15 nm Lg to 25 mV/decade, in the device with
20 nm Lg for 1V Vds.
G. Beta value Since all channels simultaneously conduct, there is huge
TABLE VI current flows from drain to source. So, the interaction
Beta value Variation with Channel Length and Oxide Thickness between channels is becoming a challenge for multi-channel
transistor design. It is more intensified when channel length
Channel Oxide Beta value is smaller due to heavy current present so electromagnetic
Length, Thickness, Vds= 1V Vds= 1.5V flux interferes and causes bumps and dips in the continuos
Lg(nm) Tox(nm) curve of output characteristics. So maximum current
achievement what it is desired is not fulfilled. To get remedy
10 1 7.91e-6 5.133e-6 from these situations, we investigate di-electric insulator
1.5 8.01785e-6 5.06714e-6 placement between channels. And from figure 13, 14 & 15
15 1 6.859e-6 5.0e-6 we can realize that the high di-electric compound Nitride
1.5 7.754e-6 5.0e-6 gives the best output than oxide and air. For better
20 1 2.046e-6 3.15987e-6 understanding all the above figures are combined in figure
1.5 5.697e-6 4.8854e-6 16. Before any placement of insulator between channels, it
should be taken care of that insulator can be easily deposited
H. Comparison between different insulation in the bulk with electrical and chemical properties taken into
accounts.
We have used two different insulating materials between the
channels of the device to explore the effect of interaction
among the conducting channels. In figure 12, The electrical
transport characteristic of the
transistor has been illustrated for three different insulation.

Fig. 14 output curve for oxide insulation for Lg=20nm, Tox=1nm

Fig. 12 Id vs Vg curve different insulation for Lg=20nm, Tox=1nm,

Vds=1v

Fig. 15 output curve nitride insulation for Lg=20nm, Tox=1nm

Fig. 13 output curve air insulation for Lg=20nm, Tox=1nm

 In figure 17, we have observed that the maximum drain
current of multichannel is almost 5 times of that of single
channel device due to the simultaneous conduction of the
multiple channel. Higher Ion/Ioff ratio, better DIBL, better
Subthreshold swing has been demonstrated by the
multichannel device.
In figure 18, Id vs Vd characteristic graph also shows that
the drain current of multichannel exceeds Id current of single
channel.

J. Comparison with multi-channel p-type device

Similar study has been carried out for multi p-type channel
device. Here, high current, improved subthreshold swing,
higher Ion/Ioff ratio have been observed for p-type multi
structure. We have seen that DIBL increased for p-type single
channel, but opposite effect has been shown for p-type
Fig. 16 output curve different insulation for Lg=20nm, Tox=1nm, multichannel. All the experiments are carried out for channel
Vgs=2v length variation for p-type multichannel which have been
demonstrated in figures 19 & 20. Since electron mobility is
I. Comparison between single and multi-channel device higher than holes in Si so maximum drain current
achieved in n-type channel. On the other hand, low on
state resistance has been observed in n-type channel.
Improved Ion/Ioff ratio and better DIBL have been
experimented in n-type channel. N-type mosfet is fast
switching device than P-type. But less off state current is
observed in p-type transistor due to lower mobility of
holes. To get the same characteristics of n-type
mosfet size needs to be bigger for p-type mosfet.

Fig. 17 Id vs Vg comparison for single and multichannel, Lg=10nm,

Tox=1.5nm, Vds=1V

Fig. 19.: Id vs Vg curve for Tox=1nm, Vds=1V

Fig. 18 Id vs Vd comparison of single and multi for Lg=10nm, Tox=1.5nm at

Vgs=0V
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ACKNOWLEDGMENT
The authors want to thank Dept. of Electrical and
Electronic Engineering, Shahjalal University of Science
& Technology, Sylhet-3114, Bangladesh for providing all
kind of laboratory and computational facilities to carry out
this work.
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