Performance study for quad gate vertically stacked
junctionless Nanosheet
1st Prasad M
Research Scholar, ECE Department
Sri Jayachamarajendra College of Engineering
Mysuru, India
prasadm88@gmail.com
Abstract—With technology scaling, innovative device design
are being explored to meet the demand for low power and
high speed circuit design. Proposed device is Quad gate vertical
stacked junctionless Nanosheet being most promising device
structure within nanoscale regime, with the use of oxide, work
function and channel engineering for single, double and triple
fins nanosheet have been proposed and successfully implemented.
In this paper, trigate junctionless (TGJLFET) overlap structure
device is modified with a new design approachs. First approach
is by adding fourth gate to TGJLFET to form a new device of
quad gate junctionless Nanosheet with overlap structure device.
Second approach is by extending the fins and adding source
and drain pads with underlap structure. Third approach is
adding the fin stacking and fourth approach is adding gate
stacking to three fins quad gate vertical stacking junctionless
Nanosheet, all the approaches are simulated using 3D visual
TCAD environment. The improvement in the performance of
Nanosheet device is denoted after comparing it with TGJLFET.
Investigated performance include leakage current, sub-threshold
swing, Drain induced barrier lowering (DIBL), threshold voltage,
trans-conductance, potential at core and surface fins of the
Nanosheet device. Further, DC and transient behaviour of 3D
inverter are simulated and studied using 3D visual TCAD device
simulator from Cogenda pvt Ltd.
Index Terms—Quad gate, overlap and underlap, gate stack,
junctionless, potential, DIBL, N type, P type and CMOS Inverter
I. I NTRODUCTION
Multi-gate FET with no junction exhibits near ideal
sub-threshold and low leakage current [1]. Further it shows
simpler in fabrication process, less variability and superior
electrical properties [2]. And also exhibits excellent short
channel behaviour, low leakage and high Ion/Ioff ratio [3].
Doping less bulk FinFET with gate stacking technique supress
the leakage current [4]. With use of gate stacking technique
with junctionless for trigate FinFT shows better performance
in terms of low leakage as scale down of channel thickness
[5]. Triple gate junctionless SOI FInFET exhibits better
performance than the double gate FinFET [6]. With reduction
of device scaling can enhance the performance by using gate
stack technique [7]. Optimization of trigate junctionless FET
have high Ion/Ioff ratio and switching speed in digital circuits
[8]. A silicon junctionless trench gate all around nanowire
have demonstrated experimentally shows outstanding Ion/Ioff
2nd U B Mahadevaswamy
Professor,ECE Department
Sri Jayachamarajendra College of Engineering
Mysuru, India
ubms-sjce@yahoo.co.in
ratio and sub-threshold slope [9]. Use of poly-Si thin film
and ultra-thin channel for n-type junctionless shows excellent
performance in SS and significant improvement in Ion current
[10]. With thin and narrow junctionless multi-gate FET have
better electrical properties [11]. By adding high-k gate stack
in junctionless FinFET shows better performance than without
gate stack [12].
Detailed discussion is provided on current status and
material properties consideration with high-k gate dielectric
[15]. The pie-gate junctionless FET with proper scaling
can achieve high Ion/Ioff ratio and low power for future
multi-functional 3D IC applications [16]. Stacked Nanosheet
for double channels with multi-gate thin film transistor shows
superior performance in electrical properties than stacked
planar device [17]. Gate all around with stacked Nanosheet
device is attractive and better solution as replacement of
FinFETs [18]. Dimensional device scaling alone gives power
benefit and scaling Nanosheet width provides fine tuning for
power and performance optimization [19]. Vertically stacked
junctionless Nanosheet for CMOS inverter shows reduction
in SNM due to Ion matching and also promising for system
on panel and 3D IC applications [20].
Further, Added fourth gate to trigate device to make it quad
gate device and it is modified with underlap conditions by
adding source and drain pads to make fin vertically stacked
Nanosheet. Finally gate stacked is implemented to make final
proposed model of both NMOS and PMOS 3fins quad gate
stacked vertically junctionless Nanosheet is implemented to
simulate the inverter circuit and study their DC and transient
behaviour.
II. D EVICE S TRUCTURE AND SIMULATION METHODOLOGY
The proposed and modified model of 3 fin vertically quad
gate stacked junctionless Nanosheet were simulated using
Visual TCAD platform.
Fig 1 shows the schematic and modelled diagram oftrigate
FinFET and 3 fin vertically quad gate stacked junctionless
Nanosheet. All the geometric parameters are shown in table
1. Channel regions and source/Drain pad with underlap regions

Fig. 1. (a) Schematic Diagram of Trigate FinFET (b) Schematic Diagram
of Quad gate vertically stacked junctionless Nanosheet (c) 3D View of Quad
gate vertically stacked junctionless Nanosheet
TABLE I
G EOMETRIC PARAMETERS FOR 3 FIN VERTICALLY QUAD GATE STACKED
JUNCTIONLESS NANOSHEET.
Device Geometric parameters Values (nm)
Lg Gate length
3Fin Quad Lspo Extended Fin length
gate TLk interfacial layer thickness
Stacked THK High-k thickness
Junctionless Lspo Source and Drain pad length
Nanosheet Tch Separation between Fins
(QGSJLNS) WFin Width of the Fin
TFin Thickness of the Fin
WNS NS spacing
NMOS Work Function for N-Type
PMOS Work Function for N-Type
were doped with acceptor of 1E19 cm-3. The dielectric
constants of interfacial layer (low-k) and high-k were fixed
at 3.9 and 22, respectively and the operation voltage VDD at
linear region and saturation region is equal to 0.1V and 1V.
Table 1 show geometric parameters for proposed model.
The drain current is obtained by considering the parameters
of carrier temperature, electric field and potential in the
nanoscale device. The current is computed from Lombardi
mobility model is an empirical model, which consists of
three components are bulk mobility, mobility due to scattering
and surface charge mobility. Three components describes the
carrier mobility in the inversion layers. The combined three
components using matthiessens rule.
µs− 1 = µb− 1 + µac− 1 + µsr− 1
Where, b is doping dependent bulk mobility, ac is mobil-
ity degradation due to acoustic phonon scattering and sr is
mobility degradation due to surface roughness.
III. R ESULT AND D ISCUSSION
The reference model of TGJLFET structure shown in
Figure 1 is simulated through a 3-D visual TCAD device
simulator. The above models are simulated and in order
to maintain the accuracy, the simulation results are well
calibrated to the benchmark with the experimental data given
in [8] as shown in Figure 2. The reference structure device
TGJLFET have design parameters of channel length, channel
width, channel thickness, gate oxide thickness, channel and
substrate doping concentration, and gate work function are
fixed throughout the simulations as: Lg = 30nm, W = 10
nm, tsi = 10 nm, tox = 2 nm, Nd = 1 1019 cm3, Nsub =
1 1015 cm3, and w.f. = 5.1 eV, respectively. The simulation
results are calibrated with reference model with gate voltage
variation from 0V to 1.2V at drain voltage of 0.1V and the
result indicates that both the simulation results are matched
and plotted it with drain current versus gate voltage as shown
in Fig 2.
30
15
1
1
20
5
10
10
40
5.2
4.27
Fig. 2. Calibration for Reference and Simualtion model at V=0.1V
Further the proposed device with adding the fourth gate to
TGJLFET to form a quad gate junctionless FET (QGJLFET)
having same design parameters of reference device structure.
The QGJLFET structure shown in Figure 3 is simulated
through a 3-D visual TCAD device simulator. The above
reference model are simulated and compared with quad gate
junctionless FinFET (QGJLFET) simulation results. The
gate voltage variation from 0V to 1.2V at linear region and
saturation region at 0.1V and 1V constant drain voltage. The
proposed model is increased in on current and reduced off
(1)
current with Ion/Ioff ratio is 2.876 times higher than the
reference model. The results is plotted as shown in Fig 3.
Further to improve the performance of the QGJLFET, the
fins are extended with underlap condition and adding the
source and drain pads. Then the device is simulated at linear
region at 0.1V and saturation region at 1V constant drain
voltage and gate voltage is ramp from 0V to 1.2 V. The
simulated result shows the increased in on current and reduced
off current better than the QGJLFET under overlap condition.
 TABLE II
P ERFORMANCE M ETRICS EVALUATED FOR ALL STRUCTURES

Fins Vth Vth DIBL SS Lin SS Sat

Lin (V) Sat (V) (mv/dec) (mv/dec) (mv/dec)
Proposed 0.484 0.484 13.4 61.748 61.851
1Fin 0.495 0.484 11.9 61.709 61.450
2Fin 0.475 0.468 8.2 61.768 61.285
3Fin 0.462 0.453 9.4 61.569 61.315
3Fin (GS) 0.559 0.552 7.6 60.768 60.573

with Ion/Ioff ratio of 2.31 and 1.98 times higher than the
double fin and single fin stack at linear region and Ion/Ioff
ratio 0.022 and 2.476 times higher than the double and single
fin stacked at saturation region.The results is plotted as shown
in Fig 5.

In table 2 shows the performance evaluation in terms

of threshold voltage linear and saturation region, Drain
Fig. 3. Simulation for Reference and Quad gate model at V=0.1V and Vd=1V induced barrier lowering (DIBL), Sub-threshold Swing (SS)
at linear and saturation region. All the results shows that
approximately equal to ideal values, but looking at fine tune
Further, added the double fin stack vertically and simulated.
values 3fin quad vertically gate stacked Nanosheet shows the
The result show the better on current and reduced off current
SS 60 mV/dec and negligible DIBL compared to others.
with Ion/Ioff ratio is 0.11 times higher than in linear region
and 2.40 times higher than in saturation region compared to
single fin Nanosheet structure.The results is plotted as shown
in Fig 4.

Fig. 5. Ion/Ioff Ratio for 1Fin, 2Fin and 3Fin Quad gate with and without
gate stacking Nanosheet at linear and saturation region at V=0.1V and Vd=1V

Finally, the triple fin quad gate vertically staked junctionless

Fig. 4. Simulation for Extended Fin Quad gate for 1Fin, 2Fin and 3Fin at
linear and saturation region at V=0.1V and Vd=1V
Further, added three fin vertically stacked nanosheet and
simulated. Then the device is simulated at linear region at
0.1V and saturation region at 1V constant drain voltage and
gate voltage is ramp from 0V to 1.2 V. The results show the
notable improvement in on current and reduced off current
nanosheet device is modified with by added gate stack with
material of HfO2 as high-k material with same oxide thickness
of 2nm, where SiO is 1nm plus HfO2 is 1nm. The equivalent
oxide thickness is 1.156nm respectively. Which is simulated
at linear region at 0.1V and saturation region at 1V constant
drain voltage and gate voltage is ramp from 0V to 1.2 V. The
simulated result shows the notable improvement in increased
on current and reduced off current with Ion/Ioff ratio is 3
times higher than in linear region and 1.637 times higher than
in saturation compared to triple fin quad gate vertically stacked
junctionless nanosheet. The results is plotted as shown in Fig
6.
Fig. 6. Simulation for 3Fin Quad gate with and without gate stacking
Nanosheet at linear and saturation region at V=0.1V and Vd=1V
The surface and core potential at the channel for single,
double and triple fin. The potential is uniform throughout the
channel over surface and core. Potential distribution in the
channel is relative to vacuum potential as shown in fig 7.
Fig. 7. Potnetial distribution over core and surface for 3Fin Quad gate stacking
Nanosheet
In order to test the feasibility of our model in circuit
applications, both N-type and P-type of a 3fin quad gate
vertically stacked Nanosheet, operating in a complementary
mode. The structure of CMOS inverter as shown in figure
8 and its DC characteristics with VDD is equal to 1V and
input ramp from 0V to 1V, as shown in figure 9 and transient
analysis with rise time 1e-09, fall time of 1e-09 and pulse
width of 4e-09 is simulated using 3D simulator Visual TCAD
platform ans as shown in figure 10.
Fig. 8. 3D model of CMOS Inverter
Fig. 9. DC characteristics of CMOS Inverter
IV. C ONCULSION
The quad gate device is implemented using fins stack-
ing with underlap condition by adding source and drain
pads for fins with gate stacking low-k and high-k materials
for existing TGJLFET research work.Based on the analysis,
modified models of quad gate junctionless with and without
gate stacking Nanosheet device have improved performance
compared to TGJLFET. The 3fin quad gate vertically stacked
junctionless shows superior performance to handle leakage
current due to better gate control and improvement in sub-
threshold swing, DIBL and Ion/Ioff ratio than the without
gate stacking Nanosheet. It has uniform electron density
and potential distributions within the active region of fins.

Fig. 10. Transient analysis CMOS Inverter
Fig. 11. Signal to Noise Ration of the CMOS Inverter
Increasing fins vertically gate stacked can be effectively used
in quad gate Nanosheet to optimize the device switching speed
in digital circuit applications. These models are more suitable
for a digital circuit is also explored in this paper and simulation
result ensures the accuracy of the model.
F UTURE S COPE
One of the astounding things about vertically stacked
Nanosheet design will extend Moores law so far as last longer
than the use of silicon in the channel. Nanosheet will appear
the best way possible to construct and carry well as far into
the future can now foresee.
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