Microelectronics Journal 107 (2021) 104942

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm

technology node
Vinay Vashishtha *, Lawrence T. Clark
Arizona State University, Tempe, AZ, 85287, USA

A R T I C L E I N F O A B S T R A C T

Keywords:
Fin field-effect-transistor (finFET)
Nanowire field-effect transistor (NWFET)
Nanosheet field-effect transistor (NSHFET)
5 nm
Static random access memory (SRAM)
TCAD
In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors
are compared for the 5 nm technology node. The performance of these transistors and the circuits comprising
them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE
simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used
on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of
this work is a 5 nm technology node follow-on to an existing 7 nm predictive process design kit (PDK) in common
academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold
current are compared for different gate lengths. Transistor performance is also compared for various raised
source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better elec-
trostatic performance as expected. However, the simulation results show that finFET devices will be adequate at
the 5 nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.

1. Introduction
FinFETs have successfully enabled continued CMOS scaling and
continuation of Moore’s law beyond the 10-nm technology node. FinFETs
provide increased drive current at a higher current density, while
reducing short channel effects such as drain induced barrier lowering
(DIBL), threshold voltage (Vt) roll-off, and subthreshold leakage, via
improved gate electrostatics provided by gates on three channel sides
[1–3]. The fully depleted fins mitigate random dopant fluctuation (RDF)
[4]. Foundry publications have indicated the continued finFET use at the
7 nm technology node (N7) [5,6]. However, their continued use at the 5
nm node (N5) is uncertain due to the degradation in their electrostatic
performance at shorter gate lengths (Lg) [7]. The use of horizontal
gate-all-around (GAA) field-effect transistors (FETs), such as nanowire
(NW) FET and nanosheet (NSH) FET, for continued scaling appears
increasingly promising due to their better electrostatics than finFETs [8,
9].
We developed a finFET-based predictive ASAP7 PDK for the 7 nm
node to address the unavailability of non-commercial predictive process
design kit (PDK) incorporating transistor compact models [10] together
with the necessary physical verification decks [11], interconnect models,
and standard cell libraries [12] to enable academic research into VLSI
circuit and physical design. The ASAP7 BSIM compact models were based
on assumptions consistent with scaling trends rather than TCAD results.
In this paper we present results of 3-D TCAD device simulations and
compact models aimed at an N5 predictive PDK (ASAP5). Transistor
geometric parameters Lg, raised source/drain (RSD) length (LRSD), and
low-k gate sidewall spacer width (WSPACER) are varied to quantify their
effect on transistor behavior. Compact models are derived from the TCAD
simulations.
The results presented here show that all of the transistor architectures
should be acceptable at the 5-nm technology node. SRAM bit line slew
rate and standard cell delay performances are compared. Since inter-
connect parasitics are significant, we use full layout parasitic extraction
using Calibre xACT3D for SRAM and gate delay comparisons.
TCAD simulated finFET, NWFET and NSHFET device parameters are
outlined in Section 2. Section 3 provides comparisons of the electrostatics
and current behavior of the different transistor structures. Extraction of
the FinFET and NWFET compact models for the ASAP5 devices is sum-
marized in Section 4. Ring oscillator (RO) and SRAM bit-line slew per-
formance comparisons are presented in Section 5. Section 6 concludes
and summarizes this paper.

* Corresponding author.
E-mail address: vinay.vashishtha@asu.edu (V. Vashishtha).

https://doi.org/10.1016/j.mejo.2020.104942
Received 16 September 2020; Accepted 10 November 2020
Available online 18 November 2020
0026-2692/© 2020 Elsevier Ltd. All rights reserved.
V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

2. FinFET and GAAFET design
After the release of ASAP7 BSIM-CMG compact models, we pursued 3-
D TCAD device simulations with finFET parameters congruous with our
initial ASAP7 compact models and geometries. These simulations served
as the calibration reference points for further 3-D TCAD simulations of
finFETs, NWFETs and NSHFETs, aimed at the ASAP5 predictive PDK.
Synopsys Sentaurus Structure Editor was used to design the transistor
structures and Sentaurus Device was used to simulate these structures
[13].
To include carrier mobility effects, the extended Canali high field
velocity saturation model [14] and the thin layer mobility model [15]
together with the inversion and accumulation layer mobility model are
employed [16]. The latter comprehends both the Philips unified mobility
model [17] and the enhanced Lombardi models [18]. Recombination
models used include the Shockley-Reed-Hall model [19,20], the Auger
model [21], and Hurkx band-to-band tunneling models [22]. Models are
also included to account for strain effects on band structure deformation
[23], carrier mobility, conduction band and valence band density of
states [24,25]. Other models used include the Slotboom band gap nar-
rowing model [26] and density gradient quantization model [27].
2.1. Gate length
Table 1 summarizes nominal parameters and doping concentrations
used to design the finFET and GAAFETs at the 16 nm metal gate length Lg
for our target N5, which is in line with another Lg estimate for N5 [8].
Fig. 1 shows the simulated 3-D views for the transistor structures. The
simulated NWFET and NSHFET structures are similar to the finFET to
facilitate like-for-like comparison. The NWFETs and NSHFETs contain
two vertically stacked horizontal NWs and NSHs, respectively. As each
such stack is analogous to a fin in a standard cell context, the units
quantifying transistor characteristics with respect to a singular stack are
typified as being those for “per fin”. The subfin, fin, NW, NSH, and the
raised source/drain (S/D) regions are all silicon. The 16 nm Lg target for
N5 may be conservative, as we believe our choice of 21 nm for the ASAP7
predictive PDK may be.
A variety of gate lengths have been published for 16 nm, 10 nm and 7
nm foundry processes, although these values are frequently not disclosed
or are treated as exemplary. Furthermore, gate length in a certain node
offering from one foundry does not match that from another foundry.
This inconsistency complicates ascribing a definitive gate length to a
Table 1
FinFET, NWFET, and NSHFET nominal design parameters.
finFET NWFET NSHFET
particular technology node based on the node naming convention alone.
For instance, TSMC describes using multiple metal gate lengths of 30 nm
and 34 nm for low threshold voltage (Vt) and standard Vt devices,
respectively, for their 16 nm offering [28]. Samsung, GlobalFoundries,
and the IBM Alliance cite a 20 nm Lg at the 10 nm foundry node [29]. This
work describes DIBL under 50 mV/V for these devices. Auth et al.
describe a 10 nm process (Intel’s 10 nm coincides much more closely
with a 7 nm foundry offerings based on the front-and-back-end layer
pitches) but do not disclose Lg or effective channel length (Leff) [30].
Their previously published data on the 14 nm generation (more in line
with a N10 foundry process) cited a 20 nm Lg [3], consistent with the
Alliance 10 nm generation Lg cited above. Alliance reported a 15 nm Lg at
N7 [5], but Samsung at N7 does not state a Lg [31], although it does state
that three logic Vt’s are offered via multiple work function gate stacks. At
the N7 node TSMC states “competitive DIBL of 40 mV/V at smaller
effective gate length down to 15 nm” Leff is generally larger than Lg due to
gate drain overlap for good performance.
It is reasonable to assume that foundries “put their best foot forward”
by publishing aggressive data and for one sub-20 nm finFET process that
we are aware of, the fin pitch and other key published data is smaller than
that in the PDK. Additionally, as evident above, multiple gate lengths can
be used. Moreover, the need to offer multiple Vt’s, achieved via multiple
work function layer combinations, requires sufficient gate length to
include these layers, as well as a high conductivity shunt metal [32]. The
gate layers are deposited over the fins or NWs within the spacers and thus
consume volume in the gate length as well as the between fin directions.
Yoshida et al. [32] show that there is no room for conductive tungsten
gate fill at 18 nm Lg for the lowest Vt option, and for any Vt option at 12
nm. The gate resistance becomes excessively high for Lg under 20 nm
without a new cobalt fill metal. The latter may allow Lg scaling to the 12
nm. The analysis presented in this paper approaches this Lg regime. A
different approach was used in N7 by one foundry [5]. The approach,
which they called “WF chamfering” recesses the WF material in the gate,
using the entire top of gate for barrier and conductive metal to ensure low
resistance along a narrower gate as demonstrated “for Lg < 17 nm”.
2.2. Contacted gate and fin pitch
A contacted gate pitch (CGP) of 40 nm is aggressive. We use it because
circuit layouts at the minimum pitch can be readily scaled-up to larger
pitches through automatic layout manipulation without impacting intra-
cell routing. For instance, if the CGP is reduced, vertical wires in a cell
may need to be eliminated. Conversely, increasing CGP merely increases
vertical wire spacing. The 24 nm Pfin, is scaled by 0.88
from that for N7
and is in accordance with the slow-down in its scaling at advanced nodes
[1,3,30].

Lg (nm) 16 16 16 2.3. Fin and nanowire dimensions

LRSD (nm) 12 12 12
WSPACER (nm) 5 5 5 The 32 nm fin height (Hfin) and the 6.5 nm fin width (Wfin) remain
CGP (nm) 40 40 40 unchanged from N7 since excessive fin bending at a 6 nm Wfin has been
WRSD or Pfin (nm) 24 24 24
Hfin or Hnsh (nm) 32 N/A 5
reported and a taller Hfin exacerbates the issue [33]. The fin is curved at
Wfin or Dnw or WNSH (nm) 6.5 8 10 the top for improved reliability and reduced gate leakage [1]. Some es-
Weff (nm) 70.50 50.26 51.41 timates show a 7 nm nanowire diameter (Dnw) at N5 [34,35]. However,
HRSD (nm) 44 44 44 we chose Dnw of 8 nm for the NWFET, since it provides a larger Idsat of
HSTI/Hsubfin (nm) 40 40 40
41.24 μA/fin as opposed to that of 38.33 μA/fin for the former at a
Hgate (nm) 60 60 60
EOT (nm) 0.78 0.78 0.78 comparable Ioff of 17.9 pA/fin for the nominal (16 nm Lg) device. For the
φNMOS (eV) 4.581 4.494 4.479 NSHFET, the NSH height (Hnsh) and width (Wnsh) of 5 nm and 10 nm (in
φPMOS (eV) 4.643 4.737 4.749 accordance with [8]), respectively, provide a similar effective channel
ρc-NMOS (Ω.cm2) 2.2
109 2.2
109 2.2
109 width (Weff) as the NWFET. The NSH corner rounding is half of Hnsh.
ρc-PMOS (Ω.cm2) 2.0
109 2.0
109 2.0
109
Nsub (cm3) 1
1017 1
1017 1
1017
Although Wfin, Dnw, WNSH for the simulated devices are unequal, which
Nsubfin (cm3) 5
1018 5
1018 5
1018 makes channel thicknesses for one device different than another, our
Nfin or Nnw or Nnsh (cm3) 1
1015 1
1015 1
1015 assumptions are based on estimates for N5. This provides a better com-
NS/D (cm3) 2
1020 2
1020 2
1020 parison with devices that are more in-line with those targeted at N5
S/D Doping Gradient (nm/dec) 1 1 1
rather than devices with equal channel thickness that are not represen-
Wfin, Dnw, and WNSH are in accordance with other estimates for N5 node. tative of an N5 node.

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V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

Fig. 1. Simulated (a) n-finFET, (b) n-NWFET (NW ¼ 2), and (c) n-NSHFET (NSH ¼ 2) 3-D views with 16 nm Lg. Cross section depicting doping concentration in the (d)
n-finFET, (e) n-NWFET (NW ¼ 2), and (f) n-NSHFET (NSH ¼ 2) along the fin length. The raised source/drain are not shown in (d)–(f).

2.4. Oxides and doping

The high-k gate oxide is a 1-nm thick HfO2 layer. A 0.6 nm thick
native SiO2 layer separates it from the Si channel. This results in a 0.78
nm equivalent oxide thickness (EOT), which is in accordance with 0.8 nm
EOT for N7 [36]. The gate trench sides are coated with a 1 nm thick HfO2
layer during its deposition at the trench bottom. The sidewall high-k gate
oxide layer abuts 5 nm wide Si3N4 gate sidewall spacers that are used for
S/D self-alignment. Thus, for the N5 transistors with 40 nm CGP and 16
nm Lg, the LRSD is 12 nm.
Fig. 1(d)–(f) show the doping concentrations for various regions
within the simulated n-FETs. To avoid sub-surface punch-through in the
finFET, the subfin region close to the fin is highly doped at 5
1018
cm3. The channel has an essentially intrinsic low doping concentration
(1
1015 cm3). As shown in Fig. 2(a), a steep sub-fin to fin retrograde Fig. 2. (a) Doping concentration profile along the fin depth in the n-finFET. (b)
doping profile is used, which has been shown to improve transistor ON- Doping concentration profile along the fin/NW/NSH length in n-finFET, n-
NWFET, and n-NSHFET. PMOS doping concentration profiles have been pre-
state current characteristics and resilience to variability [37]. The same
cluded for brevity. Lg is 16 nm and Leff is 14 nm.
sub-fin doping is used throughout for consistency. The peak S/D region
doping concentration is 2
1020 cm3, which diminishes with a 1
nm/dec gradient from S/D to the channel as shown in Fig. 2(b). The 2.5. Stress and contact resistivity
effective channel length (Leff) is demarcated by a 2
1019 cm3 peak
doping concentration in the channel [37]. Thus, the Leff is 14 nm for a 16 Uniaxial 1.6 GPa tensile and 2 GPa compressive stress are applied to
nm Lg and the 1 nm fin regions that underlay the metal gate edges on the NMOS and PMOS, respectively, to increase ON-state drive currents.
either side comprise the gate and S/D overlap. Contact resistivity (ρc) values of 2.2
109 Ω cm2 and 2.0
109 Ω cm2
are used for the n-FETs and p-FETs, respectively, which have been
demonstrated in a manufacturable process [38]. Even lower values have

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V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

been reported, which makes this choice conservative [39].

3. FinFET and GAAFET performance comparison

We characterize the transistor performance over a range of Lg, LRSD,

and WSPACER values with respect to regular Vt (RVT) transistors designed
using nominal design parameters enumerated in Table 1. A 0.7 V supply
voltage (VDD) is used for all TCAD simulations as per our N7 assumptions
[10]. The metal gate workfunction (φMG) is individually adjusted to
obtain approximately 17.7 pA/fin OFF-state (Vds ¼ VDD, Vgs ¼ 0 V)
leakage current (Ioff) for each simulated RVT transistor with nominal
design parameters. This Ioff specification results in the same Ioff per μm at
nominal N5 transistor geometries as compared to our N7 Ioff of 20 pA/fin
at a 27 nm Pfin for the RVT n-finFET compact model [10]. Instead of
optimizing the transistor performance at every discrete device geometry,
the φMG values thus ascertained for the nominal RVT transistors are kept
approximately the same for the entire set of ranges over which Lg, LRSD,
and WSPACER are swept. The φMG is varied by up to 2
103 eV to aid
simulation convergence. These changes affect Idsat by a maximum of
0.65%. TCAD results for the RVT devices are summarized in Table 2.

3.1. Gate length effects

The impact of Lg comprise Fig. 3, which compares Idsat, DIBL,

threshold voltage in the saturation (Vtsat) region, SS, Ioff, and gate-
induced drain leakage (GIDL) for finFET, NWFET, and NSHFET. Nomi-
nal LRSD and WSPACER values of 12 nm and 5 nm, respectively, are used for
each simulation. Linear Vds is 0.05 V and Vt is computed using constant
current at 50 nA Ids.
Fig. 3(a) shows that GAAFETs provide larger Idsat than finFETs across
all Lg. Previously, PMOS Idsat exceeding that of NMOS has been reported
[40], and we observe a similar finFET behavior. However, the n-GAA-
FETs are consistently stronger than their PMOS counterparts at all
simulated Lg. The NMOS-to-PMOS (N-to-P) Idsat ratio for the NWFETs at
16 nm Lg is approximately 1:0.89. For the GAAFETs and finFETs, a 1 nm
Lg change from the nominal 16 nm Lg changes the Idsat at most by 1.57%
and 4.03%, respectively, i.e., the GAAFETs are less susceptible to Lg
variations. NWFETs provide 1.34–1.41
and 1.14–1.22
greater Idsat
than the finFETs, and 1.13–1.15
and 1.07–1.09
better Idsat than the
NSHFETs over the 18–13 nm Lg range for NMOS and PMOS, respectively. Fig. 3. Simulated Lg variation effect on (a) Idsat, (b) DIBL, (c) Vtsat, (d) SS, (e) Ioff
and (f) GIDL, for the n-type and p-type finFET, NWFET, and NSHFET, at 12 nm
As mentioned in Section 2.3, the fin height and width are unscaled. Thus,
LRSD, and 5 nm WSPACER. The Leff is 2 nm less than Lg. The simulated NWFETs
to keep the Ioff per μm constant with the same electrostatics, the finFETs
and NSHFETs comprise two nanowires and nanosheets, respectively, per fin. All
sacrifice Idsat. The improved GAA electrostatics allow this with improved simulations are at 300 K.
drive current. Of course, adjusting finFET Ioff would allow greater Idsat.
As expected, and evident in Fig. 3 (b), finFETs exhibit larger DIBL
than the GAAFETs. FinFET DIBL is 2.46–3.21
and 3.2–3.8
more than
the NWFETs and NSHFETs, respectively. The largest GAAFET DIBL is less respectively. The same change for the n- and p-NWFET is 12.73% and
than the smallest finFET DIBL. The GAAFET Vt roll-off is also improved 11.76%, respectively.
over the finFETs (Fig. 3(c)). The Vtsat at 13 nm Lg decreases by 25.3% and The finFET SS is also greater than the GAAFET SS by 13–29% (see
24.31% compared to the nominal 16 nm Lg for the n- and p-finFET, Fig. 3(d)). Each GAAFET has an SS less than 66 mV/dec at 16 nm Lg. Ioff
increases by 62.68–199.68%, 18.39–78.24%, and 13.99–63.02% for the
n-finFETs, n-NWFET, and n-NSHFET, respectively, over the 18–13 nm Lg
Table 2
range. This more gradual GAAFET Ioff increase with Lg reduction as
RVT FinFET, NWFET, and NSHFET performance characteristics.
compared to the finFETs (Fig. 3(e)) corresponds to the improved Vt roll-
FinFET NWFET NSHFET off characteristics of the former. The steeper finFET Ioff increase, together
NMOS PMOS NMOS PMOS NMOS PMOS with Ioff equalization for all simulated transistors at the 16 nm Lg, results
Idsat (μA/fin) 29.83 30.50 41.24 36.55 36.10 33.86 in the finFETs having lower leakage than GAAFETs for larger than
Ioff (pA/fin) 17.75 17.76 17.87 17.51 17.73 17.84 nominal Lg.
Vt (V) 0.253 0.255 0.220 0.221 0.216 0.218 The GAAFETs exhibit lower GIDL (see Fig. 3(f)) than the finFETs due
DIBL (mV/V) 69.23 69.23 21.54 24.62 18.46 18.46
to the gate wrapping the channel bottom, thereby separating the gate-
SS (mV/dec) 75.33 75.73 64.21 65.02 63.21 63.764
GIDL (pA/fin) 0.73 1.68 0.31 0.51 0.53 1.02
drain overlap from the highly doped subfin, which affords less drain to
substrate interaction. In finFETs, GIDL reduces by a modest amount,
Results for transistors simulated at 16 nm Lg, 14 nm Leff, 12 nm LRSD, and 5 nm apparently modulated by the extent of the highly doped subfin region
WSPACER, 300 K. Metal gate workfunction has been adjusted to obtain approxi-
underneath the channel.
mately 17.7 pA/fin Ioff for each simulated RVT transistor with nominal
parameters.

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V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

3.2. Raised source/drain dimensional effects

We expect the aggressive 40 nm CGP primarily impacts the space for

source/drains. In order to assess the source and drain dimension impact
on the performance, the raised source/drain length (LRSD) is varied. As
expected, contact resistance reduction with a LRSD lengthening improves
Idsat as shown in Fig. 4(a). For a 16 nm LRSD, corresponding to a more
conservative 44 nm CGP, the Idsat increases compared to the nominal 12
nm LRSD by 5.21% and 2.85% for the n-NWFET and p-NWFET, respec-
tively. Although a relaxed CGP provides better Idsat it is not used as
explained in Section 2.2. For the n-finFET and p-finFET, Idsat increases by
3.29% and 2.92%, respectively.

3.3. WSPACER impact Fig. 5. Simulated WNSH variation effect on (a) Idsat and Ioff, (b) DIBL and SS, for
the n-type NSHFET, at 16 nm Lg, 14 nm Leff, 12 nm LRSD, and 5 nm WSPACER. The
Fig. 4(b) shows that the Idsat improvement due to S/D extension data labels above the Idsat (red) and Ioff (blue) curves are Idsat/WNSH (μA/nm)
and Ioff/WNSH (pA/nm), respectively. The simulated NSHFET comprises two
resistance decrease with WSPACER reduction is more pronounced on the
nanosheets per fin. All simulations are at 300 K.
GAAFETs than on the finFETs. This indicates greater extension resistance
contribution in the GAAFETs than in the finFETs. The more important
impact of WSPACER is on the S/D to gate capacitance. The WSPACER value 4. SRAM devices and compact models
chosen is a trade-off emphasizing the capacitance impact. Accounting for
the portion of the spacer not occupied by the S/D extensions, the We calibrated BSIM compact models to the NWFET and finFET 3-D
capacitance increases rapidly with WSPACER reductions. For example,  1 TCAD results at 16 nm Lg. The other nominal design parameters for
nm changes from the chosen nominal 5 nm increases/decreases the these simulated transistors are given in Table 1. The resulting RVT
capacitance by 21%/15%, respectively. The nominal WSPACER value models have the same Ioff per μm as the corresponding N7 transistor.
chosen was thus based on optimizing τ ¼ CV/I and not just Idsat. Fig. 6 shows that the RVT BSIM compact models for NWFETs and finFETs
correlate well to the 3-D TCAD simulation results. TCAD results for the
RVT devices are summarized in Table 2.
3.4. NSH width effects
Separate 3-D TCAD simulations were used to calibrate the SRAM
BSIM compact models for optimized SRAM transistors. The nominal RVT
NSHFETs allow multiple channel widths as opposed to the quantized
design parameters were preserved, with the exception the φMG, which is
widths permitted by finFETs and NWFETs, affording flexibility in opti-
varied to tune the transistor Vt. The SRAM device optimizes Idsat subject
mizing circuits. However, this flexibility impacts the multi-patterning
to a low Ioff (<5 pA/fin), i.e. a large Ion to Ioff ratio. Additionally, a low
mandrel layout making it potentially incompatible with the NW and
GIDL contribution to the total Ioff (GIDL < 40% Ioff) is required. This
finFET cell architectures. The Idsat and Ioff values, normalized to the NSH
width, are overlaid on the Idsat and Ioff curves in Fig. 5(a). They indicate
that both drive capability and leakage worsen as WNSH increases. The Pfin
or WRSD was changed commensurately with the WNSH for each simulation
so as to preserve the RSD angles. As shown in Fig. 5(b), SS and DIBL also
deteriorate with WNSH increase.
The NWFETs provide larger Idsat with only slightly worse electrostatic
characteristics than NSHFETs. Consequently, the layout compatibility of
horizontal NWFETs with finFET-based architectures drive the choice of
NWFETs for further comparisons. The subsequent sections compare
NWFETs with the finFETs since the latter represent feasible options at the
N5 node.

Fig. 4. Simulated LRSD variation effect on (a) Idsat for the n-type and p-type
finFET, NWFET, and NSHFET, at 5 nm WSPACER,16 nm Lg, and 14 nm Leff.
WSPACER variation effect on (b) Idsat, (d) Ioff, for the n-type and p-type finFET,
NWFET, and NSHFET, at 12 nm LRSD,16 nm Lg, and 14 nm Leff. The simulated
NWFETs and NSHFETs comprise two nanowires and nanosheets, respectively,
per fin. All simulations are at 300 K.
Fig. 6. Ids-Vgs characteristic of the (a) n-NWFET and p-NWFET, and (b) n-finFET
and p-finFET RVT compact models and the simulations to which they were
calibrated at 16 nm Lg,14 nm Leff, 12 nm LRSD, and 5 nm WSPACER. The simulated
NWFETs comprise two nanowires per fin and all simulations are at 300 K.

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V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

limits reducing Ioff and ensures a reasonable Idsat magnitude. Moreover,

to ensure SRAM write-ability, a PMOS current drive smaller than that for
the SRAM NMOS device is desirable.
Fig. 7(a) and (b) plot the TCAD Idsat and Ioff results vs. φMG for the
NWFETs and finFETs, respectively. The n-NWFET exhibit low Ioff without
being limited by GIDL throughout the φMG range. However, the Idsat
reduction is significant for φMG greater than 4.57 eV. Thus, either 4.55 eV
or 4.57 eV φMG are suitable choices for an SRAM device. At 4.64 eV φMG,
the p-NWFET has a low Ioff (1.77 pA/fin) and a high Idsat (25.02 μA) to Ioff
ratio, which makes it a good choice for the SRAM p-NWFET φMG. The p-
NWFET GIDL dominates the leakage for φMG lower than 4.64 eV. We
chose φMG for the SRAM n-NWFET to be 4.55 eV over 4.57 eV, as the
former provides a higher N-to-P Idsat ratio.
For the n-finFET, 4.63 eV is the only SRAM φMG candidate, since the
Ioff is too large for any smaller φMG and the GIDL is limiting for any larger
φMG. For the p-finFET SRAM device, any φMG values larger than 4.54 eV
result in p-finFET Idsat values that are greater than or equal to 0.87
of
the SRAM n-finFET Idsat. Thus, we chose 4.54 eV as the SRAM p-finFET
φMG to keep the PMOS drive substantially below that of the n-finFET
SRAM. Our prior 7 nm SRAMs using the ASAP7 baseline SRAM Vt tran-
sistors were more limited in write-ability than read static noise margin
(SNM). Write margin is a well-known tradeoff with read margin. Thus,
we hope to improve the former at minor expense to the latter. A notable
result of the device simulations, apparent from Fig. 7, is that GIDL is more
limiting in achieving low Ioff for the finFETs than the NWFETs in cases
where the total Ioff is small. The significantly better NWFET Idsat to Ioff
ratio is also apparent. The Ion/Ioff ratios are overlaid on the Idsat curves,
and the percentage of the Ioff comprised of GIDL is overlaid on the Ioff bars Fig. 7. Simulated φMG variation effect on Idsat, Ioff, Idsat/Ioff, and GIDL for (a)
in the figures. NWFETs and (b) n-finFETs for SRAM device determination, at 16 nm Lg, 12 nm
TCAD results for finFET and NWFET SRAM devices are summarized in LRSD, and 5 nm WSPACER. The data labels above the Idsat curves (red) and Ioff bars
Table 3. The SRAM BSIM compact models were calibrated to the TCAD (blue) are Idsat/Ioff (
106) and GIDL/Ioff (%), respectively. The simulated
results. Fig. 8 shows the calibrated SRAM compact models vs. TCAD re- NWFETs comprise two nanowires per fin. All simulations are at 300 K.
sults for NWFETs and finFETs, respectively.
Table 3
5. Circuit performance comparison SRAM FinFET and NWFET performance characteristics.
FinFET NWFET
The increasing importance of interconnect parasitics at advanced
nodes necessitates including them for circuit performance comparison. NMOS PMOS NMOS PMOS
We used Calibre MIPT and xACT3D for interconnect parasitic specifica- Idsat (μA/fin) 24.16 18.91 33.77 25.02
tion and extraction, respectively. Metal fills are assumed to be copper for Ioff (pA/fin) 4.63 3.94 2.71 1.77
N7 and cobalt for N5. The non-linear resistivity increase with intercon- Vt (V) 0.302 0.358 0.276 0.318
DIBL (mV/V) 69.23 69.23 21.54 24.62
nect width reduction [41,42] as well as the contribution from metal fill
SS (mV/dec) 75.29 75.69 64.213 65.018
diffusion barrier layer, its sidewall and bottom thicknesses, and trench GIDL (pA/fin) 1.09 3.32 0.35 0.64
slope angle effect, are all accounted for during the interconnect parasitic
Results for transistors simulated at 16 nm Lg, 14 nm Leff, 12 nm LRSD, and 5 nm
modelling and extraction.
WSPACER, 300 K.

5.1. SRAMs
[44] values for the 111, 112, and 122 SRAM cells simulated in 7 nm
(ASAP7) and in N5, by using the SRAM compact models fitted to the
A 122 (1 fin/NW pull-up, 2 fin/NW pull-down, and 2 fin/NW access
SRAM transistor TCAD results, are summarized in Table 5. Thus, the
transistor) SRAM bit cell is used for the BL discharge rate comparison. We
PMOS drive change in Section 4 reduced the read margins by 15 mV–17
designed three SRAM column group layouts based on this cell, each
mV. As expected, the 112 cell has by far the best read margin owing to the
containing four SRAM columns, with 32, 64, and 128 SRAM cells per
single fin access device. However, this trades-off to be easily the worst
column. Multiple columns provide the appropriate metal-to-metal ca-
write margin [43].
pacitances on the bit line (BL) routes. The SRAM BL read slew rate is used
These values are similar to published foundry data for finFETs. At
to evaluate the performance. For simplicity, we ignore the interconnect
N16, 111 cell published results show a read SNM of 120 mV at 0.6 V VDD
parasitic contributions from BL multiplexers and the sense amplifier.
[28]. The N7 and N5 111 cells here have the equivalent values of 141 mV
However, transistor loading is added to the BL termination points. The
and 120 mV, respectively. Publications of read SNM for the 111 cell in N7
time taken to develop a 100 mV signal on the BL is the figure of merit
show 100 mV at VDD ¼ 0.5 V for one foundry and 102 mV at VDD ¼ 0.6 V
following [43].
for another. The former is better than the N5 111 SRAM cell here, which
Table 4 summarizes the HSPICE simulated 100 mV BL signal devel-
has a read SNM of 96 mV at that voltage.
opment latencies with full interconnect parasitic resistance and capaci-
The write margins were DC simulated by driving the SRAM bit line
tance extraction. The circuit simulations use 0.65 V VDD. The finFET
(BL) with an ideal voltage source and measuring the BL voltage where the
SRAM latency is 40%–64% greater than that for their NWFET counter-
cell flips. A higher value of course indicates improved write-ability. Write
parts—a significant read speed penalty.
voltages for the 111, 112, and 122 cells simulated in our N7 and with the
SRAM read and write margins are similar to those of the ASAP7 SRAM
N5 SRAM compact models are given in Table 5. Write margin values for
values for the same operating voltages, as shown in Fig. 9. Read SNM

6
V. Vashishtha, L.T. Clark Microelectronics Journal 107 (2021) 104942

Fig. 9. Read signal to noise margin (SNM) simulation plots for (a) N7 and (b)
N5. Write margin simulation plots for (c) N7 and (d) N5. SRAM bitcells used are
111, 112, and 122. HSPICE circuits simulations are at 0.65 V nominal voltage,
25  C.

Table 5
Read SNM and Write Margin Simulation Results for 111, 112, and 122 SRAM
Cells.
Fig. 8. Ids-Vgs characteristic of the (a) n-NWFET and p-NWFET, and (b) n-finFET
Margin Type Node Cell Type
and p-finFET SRAM compact models and the simulations to which they were
calibrated at 16 nm Lg, 14 nm Leff, 12 nm LRSD, and 5 nm WSPACER. The simulated 111 112 122
NWFETs comprise two nanowires per fin and all simulations are at 300 K. Read SNM (mV) N7 150 169 143
N5 133 154 128
Write Margin (mV) N7 172 146 214
Table 4 N5 166 135 203
FinFET vs. NWFET SRAM BL Signal Development Latency.
HSPICE circuit simulations are at 0.65 V nominal voltage, 25  C.
Latency (ps)

Bitcells per Column 32 64
finFET 28.26 40.32
NWFET 20.18 26.88
HSPICE circuit simulations are at 0.65 V nominal voltage, 25  C. Values listed
here are the worst-case latencies.
the latter are still degraded compared to our N7, indicating that the
increased PMOS SRAM Vt amplitude chosen above may be insufficient.
Write assist schemes have become common on advanced processes, given
the difficulty of this tradeoff. Unfortunately, SRAM write margins are
generally unpublished. Moreover, with high sigma variability, the spe-
cific write circuits must be included for a detailed analysis, which is
beyond the scope of this paper.
5.2. Logic delay
7-stage NAND2
1 based ROs are used to evaluate the gate delay
improvement from N7 (Lg ¼ 21 nm) to N5 (Lg ¼ 16 nm) as well as
compare the finFET and NWFET based gates. The NAND2
1 standard
cell layouts for both ROs can accommodate 6.5 metal 2 (M2) interconnect
routing tracks, i.e. 6.5-T standard cells, which corresponds to 234 nm and
169 nm tall cells in ASAP7 and our anticipated N5, respectively.
Table 6 comprises the HSPICE simulation RO results. The stage delay
128 improvement from N7 to N5 with NWFETs is approximately 54% when
75.03 only the transistor contribution is considered, i.e., the no parasitic
45.57
extraction case. The improvements are diminished to approximately 25%
in the extracted case. The stage delay increases from the non-extracted to
the extracted case by approximately 2.24
for N7 and 3.68
for N5 with
NWFETs, emphasizing the importance of accounting for metal parasitics
in delay analysis. The stage delay increase from N7 to N5 with finFETs is
due to the smaller Idsat for the latter because of our assumption of con-
stant Ioff per μm with unscaled fins for a finFET N5, as discussed in
Section 3.
6. Conclusions
The choice of a target N5 Lg of 16 nm is based on practical consid-
erations as well as a desire to stay in line with the ASAP7 baseline Lg,
which may have been conservative—it is difficult to glean definitive
values from foundry publications. There is no doubt that scaling the
channel length is increasing challenging, particularly in view of the need
to provide multiple Vt’s and the rapidity with which multiple Vt setting
layers consume the gate volume. We also chose an aggressive CPP of 40
nm for this work. However, doing so allows automatic layout scaling to
larger CPP, e.g., 44 or 46 nm, since moving to a larger area precludes
vertical routes running out of space in any layout. The same layout

7
V. Vashishtha, L.T. Clark
Table 6
N7 vs. N5 7-Stage NAND2
1 Ring Oscillator Stage Delay.
Latency (ps)
Non-Extracted Extracted
Rise Time Fall Time Rise Time Fall Time
N7 5.75 4.52 12.88 10.14
N5 (NWFET) 2.61 2.09 9.62 7.67
N5 (FinFET) 7.17 6.66 15.40 13.96
HSPICE circuit simulations are at 0.65 V nominal voltage, 25  C. The stage delay
increase from N7 to N5 with finFETs is due to the smaller Idsat as a result of
constant Ioff per μm with unscaled fins for the finFET N5 (see Section 3).
architecture can support both the fin and GAA devices.
The finFET electrostatic characteristics, although poorer than GAA-
FETs, are still in line with those demonstrated in a foundry N7 process
that exhibits 89 mV/V DIBL and SS ¼ 72 mV/dec with an aggressive 15
nm Lg [5]. They are also better than an advanced planar N28 process that
had a 115 mV/V DIBL and a 90 mV/dec SS [45] which was also appar-
ently usable by designers. Consequently, finFETs are still viable for use at
N5 and potentially, even beyond. In fact, the simulations indicated that
any of the device types studied in this paper is feasible down to the 13 nm
Lg studied, while staying superior to the DIBL and SS performance of the
last generations of planar CMOS processes.
The TCAD simulation results indicate GAAFET suitability to replace
finFETs at N5 to enable high drive strength while maintaining or even
improving the leakage performance—provided they can be reliably
fabricated. Although NSHFETs afford greater latitude in circuit design
due to non-discrete channel widths, their drive strength and electrostatic
characteristics degrade with larger widths. The NSHFET results here
showed better SS and DIBL, as well as lower Ioff for gate lengths smaller
than 16 nm, as compared to NWFETs. However, these improvements are
marginal and the NSHFETs exhibited lower drive currents than NWFETs.
Reintroducing devices with width modulation flexibility may also
complicate the “fin” multi-patterning, particularly in standard cells.
The TCAD results showed that GIDL is a limiting factor for an SRAM
device, with a more pronounced impact on finFETs than on NWFETs, the
improved electrostatics of which simplify the optimization of leakage vs.
drive currents. The large difference between transistor-only and with
parasitic simulated performance shows the importance of including
parasitics in the analysis. SRAM circuit simulations with full parasitic
extraction show that NWFETs provide over 40% improvement in BL
development to sense latency as compared to finFETs, despite greater
leakage in the latter. The RO circuit simulations demonstrate that NWFET
use at N5 provides smaller delay than N7, as expected, but the non-linear
increase in interconnect resistivity diminishes the latency improvement.
A taller finFET would provide increased drive in the same area, consistent
with the scaling choices of foundry processes. However, the GAAFET
provides these improvements, so if manufacturable at N5, appears a
better choice.
Declaration of competing interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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