4088 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO.
8, AUGUST 2022
Optimization and Benchmarking FinFETs and
GAA Nanosheet Architectures at 3-nm
Technology Node: Impact of Unique Boosters
Krishna K. Bhuwalka , Senior Member, IEEE, Hao Wu, Wenbo Zhao, Gerhard Rzepa,
Oskar Baumgartner , Member, IEEE, Francis Benistant, Yijian Chen, and Changze Liu
Abstract — Using a full design-technology cooptimization
(DTCO) framework, we benchmark gate-all-around (GAA)
nanosheet (NS) FETs against FinFETs at 3-nm logic
technology relevant dimensions. First, to understand
the intrinsic gain from NS, both device architectures are
simulated using fixed technology ground rules [contact
poly pitch (CPP), metal pitch Mx , and cell height] and
process assumptions (PAs), including stress, doping,
junctions, and oxide thickness. Full geometry optimization
along the CPP direction (gate length LG , spacer thickness
TSP , and contact length LCNT ) is done to self-consistently
account for tradeoff between short-channel effects (SCE),
intrinsic and extrinsic resistances, and capacitances
(device and parasitic). This leads to independent optimum
design specifications for each Fin and NS architectures.
Impact of Fin tapering and NS width and stack number are
further investigated, showing additional design flexibility
of GAA NS devices at scaled dimensions.
Index Terms — 3-nm technology, design-technology
cooptimization (DTCO), FinFETs, gate-all-around (GAA),
nanosheet (NS), stack number, standard cell.
I. I NTRODUCTION
M ULTISTACK gate-all-around (GAA) nanosheet (NS)
transistors have been tipped to replace FinFETs as
architecture of choice for beyond 3-nm CMOS logic technol-
ogy nodes [1]–[8]. While short-channel effects (SCE) improve-
ment at scaled gate lengths is cited as main motivation for
migrating toward GAA technology, an important aspect of
these devices is that NS architectures can provide higher
effective width (WEFF ) per footprint at a given cell height
and stack height. Another advantage of GAA technology is
that almost 90% of process flow is like that of FinFETs,
Manuscript received 7 March 2022; revised 5 May 2022 and 23 May
2022; accepted 25 May 2022. Date of publication 8 June 2022; date of
current version 25 July 2022. The review of this article was arranged by
Editor R. Wang. (Corresponding author: Krishna K. Bhuwalka.)
Krishna K. Bhuwalka, Hao Wu, and Changze Liu are with the Belgium
Research Center, Huawei Technologies Research and Development,
3001 Leuven, Belgium (e-mail: Krishna.Bhuwalka@huawei.com).
Wenbo Zhao, Francis Benistant, and Yijian Chen are with HiSilicon
Technologies, Shenzhen 518129, China.
Gerhard Rzepa and Oskar Baumgartner are with Global TCAD Solu-
tions, 1010 Vienna, Austria.
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2022.3178665.
Digital Object Identifier 10.1109/TED.2022.3178665
0018-9383 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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thus allowing for relatively easy migration by modification
of few extra steps, i.e., SiGe/Si stack epi, inner spacers (ISPs)
formation, and sacrificial SiGe removal for replacement metal
gate (RMG) process [3]. Several attempts have been made
to benchmark the performance advantages of NS-FETs over
FinFETs under various device and technology assumptions
scenarios with SPICE level ring-oscillator simulations [5] as
well as device sensitivity analysis using Technology Com-
puter Aided Design (TCAD) [9]–[11], but a complete picture
accounting for self-consistent impact of SCE, device, and
standard cell-level resistances and capacitances is missing.
In this article, using a full design-technology cooptimization
(DTCO) framework [12], [13], including nonidealities such as
those mentioned in [17], we benchmark these two architectures
for a given process assumptions (PAs) case [L G , contact
resistivity, stress, source/drain and extension doping, junc-
tions, effective oxide thickness (EOT), and dielectric k-values]
(Fig. 1), as well as at each fully optimized along the channel
[contact poly pitch (CPP)] direction, thus considering gate
length (L G ) accounting for impact of SCE [subthreshold swing
SSAT and drain-induced barrier lowering (DIBL)], channel
resistance RCHANNEL and gate capacitance; spacer thickness
(TSP ) accounting for junction proximity (hence SSAT , DIBL),
external resistance REXT , and parasitic gate-epi capacitance;
and contact length L CNT accounting for middle-of-line (MOL)
and semiconductor-silicide contact resistance (for a given sili-
cide resistivity, contact resistance is a function of contact area).
Thus, we demonstrate that while optimum device performance
(ON-current ION at fixed OFF-current IOFF ) can be achieved at
smaller TSP (6 nm), improvement in MOL capacitance with
increasing TSP results in an optimum speed scenario at a larger
TSP (∼8 nm) for all the three architectures considered here,
that is, overall capacitance (CEFF ) plays a larger role than
short-channel impact alone. For FinFET, while improving fin
profile from tapering (89◦ with fin bottom width 6.7 nm and
fin top width 5 nm) to vertical (90◦ , uniform fin width of 5 nm)
significantly improves speed (SSAT improvement), optimum
L G already can be scaled. NS, due to further improvement
in SSAT , provides additional scaling in L G and improved
speed–power–performance scenario. Furthermore, NS width
and stack number (#) flexibility, which provides a wide range
of effective width WEFF per footprint, allows for further
room for NS design targeting high-performance or low-power
 BHUWALKA et al.: OPTIMIZATION AND BENCHMARKING FinFETs AND GAA NS ARCHITECTURES 4089

Fig. 1. Baseline PAs for simulations.

Fig. 2. 3-D (bird’s eye) view of device structures for two-Fin (vertical)
and a three-stack NS. Reference device is with CPP 45 nm, LG 15 nm,
applications. Detailed effective resistance and effective capac- TSP 6 nm, and LCNT 18 nm.
itance tradeoff for NS design is further done.

II. TCAD S TRUCTURE S ETUP

TCAD-based framework for DTCO as described in [13] is
used for this study. Baseline (nominal device) NS/FinFETs are
defined with assumptions, as listed in Fig. 1. Fin pitch (24 nm)
and vertical NS vertical pitch (15 nm) are used corresponding
to fin width of 5 nm (fin-to-fin space 19 nm) and NS thickness
of 5 nm (NS space 10 nm), respectively.
Fig. 2 shows the 3-D view for the nominal device
(CPP/L G /TSP /L CNT of 45 nm/15 nm/6 nm/18 nm). TCAD
device simulations are done using drift-diffusion/density gra-
dient (DD/DG) equations coupled with Poisson equations. The
DG models account for quantum correction potentials. The
mobility models used are Lombardi, Philips, and Ballistic
models. Device calibration [14] for mobility parameters is
done with PAs and compact models from [15]. It should also
be noted that for Si, both the impact of ballistic tunneling
as well as velocity overshoot is small for L G > 10 nm
[18]. Thereby, justifying use of semiclassical models in the
range of device geometry used here (L G 11–19 nm). Also,
ON -current ION (IDS at VDS = VGS = VDD = 0.75 V)
for design of experiment (DoE) splits is normalized to ION
for this dimension for FinFET with tapering profile. Ring-
oscillator simulations are done using the SPICE-based DTCO
flow [13], which shows excellent consistency with full-cell
DTCO flow. A fixed 6.5-track layout (cell height 208 nm
at metal pitch Mx 32 nm) is used. Speed or frequency-at-
iso-power (S@P) corresponding to VDD splits 0.5–1.0 V and
speed-at-iso-leakage (S@L) at n/p FET IOFF 1 nA (IDS at
VDS = 0.75 V and VGS = 0 V) are extracted where relevant.
All simulations are done for a temperature setting of 300 K.
Even though self-heating effects are different for both Fins
and NSs [3], including this effect is beyond the scope of this
work and is discussed elsewhere [19].
III. D EVICE O PTIMIZATION
In this section, we will discuss optimization for Fin and NS
devices. First, FinFET device-level optimization considering
the three essential components that define CPP for a fixed
(z-) vertical (HFIN 48 nm) and (y-) width (two-Fin#) is done.
It should be noted that two-Fin with HFIN 48 nm corresponds
Fig. 3. Representative cross sections for two NS DoE with short-LG
(left) and long LG (right). As LG increases, for fixed TSP , LCNT decreases
resulting in larger contact resistance for a fixed contact resistivity.
to effective width (WEFF ) of 202 nm [2 × (2HFIN + TFIN )],
where TFIN is the fin width (5 nm). This defines the base-
line with optimum dimensions for benchmarking with GAA
NS-FETs. Thus, at fixed CPP (45 nm), L G [including high-
k (HK) thickness], TSP , and L CNT are varied simultaneously
following the assumption that (Fig. 3):
CPP = L G + 2TSP + L CNT .
Both realistic fin profile Fin (taper) and ideal profile
Fin (vertical) is considered. All other process parameters are
constant as listed in Fig. 1 unless otherwise specified. This
is followed by a similar exercise for NS-FETs and then
full DTCO (for each DoE, layout, device structure, current–
voltage, and capacitance–voltage characteristics to extract
compact models and parasitic extraction (PEX) for each full
3-D standard cell architecture followed by SPICE simulations)
and subsequent analysis is done. For NS, in addition to CPP
dimension optimization, the impact of width NS and stack
number is also investigated. To enable the DTCO framework,
while both n/p FET device simulations are done, results for
only nFET are shown here to avoid repetition. While pFET
absolute electrical parameter values are different, general trend

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 4090 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 8, AUGUST 2022

Fig. 4. Normalized average ION (IOFF 1 nA) as a tradeoff between LG , Fig. 6. REXT and RCHANNEL for nFinFET (vertical) as a function of LG
TSP , and LCNT for nFinFETs at a fixed CPP of 45 nm and HFIN 48 nm. and TSP at fixed CPP of 45 nm and HFIN 48 nm.

Fig. 5. SSAT for Fin (taper) (left) and Fin (vertical) (right) as a function of Fig. 7. Normalized ION and SSAT for NS with stack number 3 and WNS
LG and TSP at fixed CPP of 45 nm and HFIN 48 nm. 30 nm as a function of LG and TSP at a fixed CPP of 45 nm.

and optimum design space is similar. In any case, full DTCO

study captures the impact of both n/p FETs.

A. FinFET Device Optimization

Fig. 4 shows the normalized ION at fixed IOFF for Fin (taper)
and Fin (vertical) for change in CPP direction parameters.
As can be seen, as L G scales for fixed TSP , ION shows an
optimum L G (ION first increases and then decreases). This is
a result of the tradeoff between SSAT (Fig. 5), which degrades
with L G scaling, while channel resistance RCHANNEL and Fig. 8. REXT and RCHANNEL for NS with stack number 3 and WNS 30 nm
as a function of LG and TSP at a fixed CPP of 45 nm.
REXT both improve (Fig. 6). RCHANNEL is the gate-dependent
component of total device resistance (RTOTAL = 0.05V/IDS )
and z-(stack #) direction parameters. A stack number of 3 and
and REXT (RTOTAL − RCHANNEL) is the external resistance (gate-
WNS of 30 nm is chosen as a starting condition as it results in
independent component of resistance including S/D resistance
nearly the same NS stack height (3 nm × 15 nm = 45 nm) and
and silicide resistance) as described in [16]. REXT improves
WEFF (3 × 2(WNS + TNS ) = 210 nm) as that of FinFETs. The
as L CNT increases as L G scales for fixed TSP . It should be
corresponding normalized ION and SSAT are shown in Fig. 7.
noted that RCHANNEL , though improves for most part, shows
As shown in Fig. 3, ISP and outer spacers (MSPs) are of
degradation beyond L G 12 nm at TSP < 7 nm. Since RCHANNEL
the same thickness (TSP ), that is, if the outer (main spacers)
is also extracted at fixed IOFF , short-channel impact is included.
thickness increases, ISPs thickness also increases. Apart from
Furthermore, while optimum ION for Fin (taper) is at L G 17 nm
NS resulting in maximum ION increase of ∼15% with respect
as expected, it scales to 14 nm for Fin (vertical). This is mainly
to tapered Fin and ∼9% with respect to vertical Fin, optimum
due to improved SSAT (Fig. 5). Furthermore, as a function of
L G at minimum TSP of 6 nm is at 13 nm. Thus, NS provides
increasing TSP , while optimum L G scales (SSAT improves as
L G scaling advantage of 4 and 1 nm with respect to tapered
TSP increases), ION degrades due to an increase in both REXT
and vertical Fins. Also, SSAT remains below 75 mV/dec for
(L CNT is smaller) and RCHANNEL (overlap resistance is higher
all DoEs providing greater ION advantage at smaller L G s. The
as effective gate length increases). It should be noted that
corresponding REXT and RCHANNEL data are shown in Fig. 8.
while ION degrades, effective capacitance (CEFF ) improves with
increasing TSP (epi-gate distance increases). This results in yet
another design aspect for speed–power optimization consider- IV. P ERFORMANCE –P OWER O PTIMIZATION
ations. This will be discussed further in the DTCO section. In this section, we discuss full standard cell optimization
results corresponding to device results from Section III. Fig. 9
B. NS-FET Device Optimization shows the gate-center cross section along the width (fin
Following similar study as for FinFET, optimum channel pitch) direction for Fin and NS reference devices. Fig. 10
(x-) direction study is done for NS-FETs for a fixed y −(WNS ) shows the cross section along the source center cut showing

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 BHUWALKA et al.: OPTIMIZATION AND BENCHMARKING FinFETs AND GAA NS ARCHITECTURES
Fig. 9. Full-cell cross section for two-Fin FinFET (left) and three-stack
NS (right) at gate-center cut showing Fin and NS profile along the width
dimensions. Fin pitch is 24 nm, while NS vertical pitch of 15 nm is used.
Fig. 10. Full-cell cross section for FinFET (left) and NS (right) at
source-epi center cut showing Fin and NS epi and MOL profile along
the width dimensions.
MOL components. The exact same MOL and back-end-of-line
(BEOL) parameters are used for all the devices.
The transistor compact model is extracted, excluding the
backend PEX components to avoid double counting at the
SPICE level. The PEX netlist model for the backend is
extracted on the full 3-D structure at the same time as the
transistor netlist. This ensures self-consistency between device
parameters and circuit parameters. Both netlists are used in
SPICE with the transistor compact model to conduct the
performance–power–area (PPA) analysis. The PEX netlist can
be switched ON and OFF to assess the impact of the backend
on the circuit performance. Since for each split, a full 3-D
structure is generated for PEX component extraction, a simple
inverter standard cell is used for all PPA works. On a 16-core
processor, this can be done in less than an hour.
Fig. 11 shows the SPICE simulation output for the DoEs.
As also shown in the figure, and for convenience of rep-
resentation, speed-at-iso-power and power-at-iso-speed are
extracted with respect to the reference device [Fin (taper) with
L G /TSP /L CNT of 15 nm/6 nm/18 nm], which is set to 100%.
As shown in the figure, speed (or frequency) at iso-leakage
(S@L) is extracted for each DoE at fixed nominal VDD (0.75)
where IOFF for both n- and p-FETs is fixed at 1 nA. Speed-at-
iso-power (S@P) for each DoE is extracted (interpolated from
VDD sweep) at fixed power for reference device at nominal
VDD (0.75 V). Similarly, power at iso-speed is extracted (inter-
polated) power at a fixed speed. At nominal VDD , effective
resistance REFF and effective capacitance CEFF are extracted
such that frequency (speed) ∼ 1/(REFF × CEFF ) [20].
A. FinFET Performance–Power Analysis
The extracted speed-at-iso-leakage for the DoEs is shown
in Fig. 12. Contrasting the optimum performance (Fig. 4)
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4091
Fig. 11. Power versus frequency curves for Fin (taper), Fin (vertical),
and GAA NS for VDD sweep 0.5–1.0 V (nominal VDD 0.75 V) for all the
DoEs (LG , TSP , and LCNT splits). Each curve is a result of full DTCO
simulation.
Fig. 12. Speed-at-iso-leakage (VDD 0.75 V and IOFF 1 nA) as a function
of LG and TSP for Fin (taper) (left) and Fin (vertical) (right). Optimum
performance is obtained at LG 15 nm for taper and LG 14 nm for vertical
due to better SCE control. Speed-at-iso-leakage 100% corresponds to
the reference Fin (taper) device.
Fig. 13. REFF and CEFF (VDD 0.75 V and IOFF 1 nA) as a function of LG
and TSP for Fin (vertical). While REFF increases as LG scales and TSP
increases, CEFF improves as LG scales and TSP increases.
where minimum spacer (6 nm) yielded best ION , including
capacitance impact, it becomes clear that while considering
overall impact of swing, resistance (channel and parasitic),
and capacitance (intrinsic and parasitic), a larger spacer leads
to more optimum performance. The tradeoff between REFF
and CEFF is shown in Fig. 13 for Fin (vertical) case. As L G
scales or TSP increases, REFF increases (lower RCHANNEL but
degraded SSAT and REXT ), while CEFF improves. It should
also be noted that CEFF shows much larger sensitivity to TSP
than L G . Tradeoff between the two sets’ optimum L G , TSP ,
and L CNT for each device. CEFF scaling with L G also helps
reduce L G (optimum) toward smaller values.
Thus, within the design space, full CPP direction parameter
optimization yields different optimum points for device-level
and standard cell-level optimization, thereby also highlighting
the usefulness and necessity of full DTCO level evaluation.
 4092
Fig. 14. Speed-at-iso-leakage data for NS with stack number 3 and WNS
30 nm. Gate length represents both inner and outer LG , while spacer
thickness represents both inner and outer ISPs. At optimum LG (13 nm)
and TSP (8 nm), a 10% improvement in performance is obtained with
respect to the reference GAA device (LG /TSP 15 nm/6 nm).
In fact, 15% higher speed-at-iso-leakage is obtained for Fin
(taper) (L G 15 nm and TSP ∼ 8.25 nm) and 12% higher for
Fin (vertical) cases (at L G 14 nm and TSP ∼ 8 nm) over each
reference device. It should also be noted that the optimum L G
gap between Fin (taper) and Fin (vertical) is reduced from
3 nm (17–14 nm) to 1 nm (15–14 nm), due to the impact of
dominating CEFF sensitivity.
B. GAA NS Performance–Power Analysis
Fig. 14 shows speed-at-iso-leakage tradeoff scenarios for
NS device L G and TSP scaling. As stated, inner-L G and outer-
L G share a common definition, i.e., both change at the same
time, and so do the outer (main) spacers as well as ISPs
(Fig. 3). As can be seen at full standard cell optimization,
GAA NSs at optimum L G of 13 nm provide an additional
L G scaling of 1 nm with respect to Fin (vertical) and 2 nm
with respect to Fin (taper). Performance improvement of 10%
is obtained with respect to the reference NS device (L G
15 nm and TSP 6 nm). Decreasing sensitivity for performance
improvement, i.e., Fin (taper) +15%, Fin (vertical) +12%,
and GAA NS +10%, is the consequence of improved swing
for the reference device for each case. This results in weaker
sensitivity due to an increase in TSP . Interestingly, optimum
spacer thickness for each case is found to be around 8 nm for
this set of PAs (junction, doping, and EOT). Any change in
these baseline conditions may result in a different design point.
C. Fin/NS Performance Benchmark
In this section, we summarize the results and bench-
mark Fin/NS devices for reference and each optimized case.
Fig. 15 shows the speed-at-iso-power and speed-at-iso-leakage
(0.75 V) for the various cases, while the corresponding REFF
and CEFF data are shown in Fig. 16. As can be seen, refer-
ence Fin (vertical) provides 6%/16% speed-at-iso-power and
speed-at-iso-leakage gain, while GAA NS improves both by
17%/35%. Fin (vertical) gain essentially comes because of
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 69, NO. 8, AUGUST 2022
Fig. 15. Speed-at-iso-power and speed-at-iso-leakage for Fin (taper),
Fin (vertical), and GAA NS for reference cases (LG and TSP ) (15 and
6 nm) and each optimized case (two-Fin and HFIN 48 nm and WNS 30 nm
and stack number 3).
Fig. 16. REFF and CEFF extracted at nominal VDD (0.75 V) for Fin (taper),
Fin (vertical), and GAA NS for reference cases (LG and TSP ) (15 and
6 nm) and each optimized case (two-Fin and HFIN 48 nm and WNS 30 nm
and stack number 3).
SSAT improvement (77–72 mV/dec), which results in a 13%
REFF gain at the same leakage (1 nA), while CEFF remains
similar (i.e., CEFF does not change with fin tapering). GAA
improvement is a result of both REFF (−22%) and CEFF
(−5%) gain. REFF gain is due to significant SSAT improvement
(77–67 mV/dec).
At the optimum case, Fin (taper) shows a 13% gain in
CEFF (TSP larger) at coincidently similar REFF . REFF is com-
pensated by improvement in SSAT but degradation in REXT as
contact length is reduced for the same L G . This results in an
overall 12%/15% gain in speed-at-power and speed-at-leakage
parameters.
For the Fin (vertical) case, a similar gain in CEFF is
obtained (13%), but REFF is degraded (5%). This is because
of weaker improvement in SSAT (72–69 mV/dec) but similar
REXT degradation.
Finally, for GAA NS, while SSAT is saturated (∼67 mV/dec),
there is more severe loss in REFF (degrade 8%), though CEFF
improves. This results in a weaker overall gain in speed-at-
iso-power/speed-at-iso-leakage of 15%/9% with respect to its
reference device. Despite this, overall GAA NS can provide
up to 18% gain over Fin (vertical) and 29% over Fin (taper) if
each device is independently optimized, a result of 14% REFF
gain and 7% CEFF gain.
D. GAA NS Geometry Optimization
Since GAA NS provides planar-like flexible choice of NS
width (WNS ), which coupled with stack number increase,
 BHUWALKA et al.: OPTIMIZATION AND BENCHMARKING FinFETs AND GAA NS ARCHITECTURES
Fig. 17. NS n/p WEFF as a function of WNS and stack number. At similar
stack height, NS provides break-even WEFF for WNS 30 nm.
Fig. 18. Cross section for 3-D standard cell structure for GAA NS with
stack number 2 and WNS 15 nm (left) and stack number 4 and WNS 30 nm
(right).
it provides for a wide range of effective width WEFF per
footprint. This is shown in Fig. 17. For an optimum NS
device from Fig. 14 (L G 13 and TSP 8 nm), WNS and stack
number study are done to understand performance–power
tradeoff scenarios. For all the results shown here, n/p WNS
is symmetric.
Thus, WNS is varied from 15 nm to a maximum of 35 nm,
while stack number is varied from stack number 2 (a stack
height of 30 nm) to stack number 6 (a stack height of 90 nm) at
a fixed NS pitch of 15 nm. Fig. 18 shows the gate-center cross
section for representative NS devices with stack number 2 and
WNS 15 nm and stack number 4 and WNS 30 nm. It should
be noted that as WNS is scaled, the center-to-center distance
between n/p NS is kept constant at 96 nm as indicated in the
figure. This implies that n/p spacing between the NSs increases
(decreases) as NS width decreases (increases). Also, total gate
metal length is kept constant (208 nm), which means that gate-
epi overlap length changes as WNS changes. With stack number
increase, gate height increases accordingly, while all other
MOL vertical components are kept constant. It should also
be noted that while the source/drain epi volume is a function
of both NS width and stack number (not shown, but can be
visualized from Fig. 10), stress for nFET (tensile 0.7 GPa) and
pFETs (compressive 1.6 GPa) remains constant.
The corresponding speed-at-iso-leakage and speed-at-iso-
power performance metrics for the devices are shown in
Figs. 19 and 20, respectively. For stacks #5 and #6, data
points WNS 30 and 35 nm are not shown as for these widths;
for large stack number, n/p epi is shorted or with very little
process margin.
As can be seen, from speed-at-iso-leakage perspective,
while for smaller WNS (15–25 nm), the optimum stack is
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4093
Fig. 19. Speed-at-iso-leakage for GAA NS with WNS and stack number
as variable parameters (LG 13 nm and TSP 8 nm).
Fig. 20. Speed-at-iso-power for GAA NS with WNS and stack number
as variable parameters (LG 13 nm and TSP 8 nm).
Fig. 21. REFF versus CEFF for GAA NS with WNS and stack number
as variable parameters (LG 13 nm and TSP 8 nm). Speed-driven (wide
NS and high stack number), power-efficient (narrow WNS and low stack
number), and optimum (relatively low REFF and CEFF ) regions are
indicated with respect to reference Fin (taper).
at #5, it drops to #4 as WNS becomes larger (30–35 nm).
This can be explained from the corresponding REFF − CEFF
tradeoff scenarios, as shown in Fig. 21. Optimum performance
regions correspond to relatively low REFF and low CEFF with
respect to Fin (taper). This in turn corresponds to devices
with intermediate stack number and WNS (stack numbers 3
and 4, WNS 25–30 nm); high-performance devices that have
low REFF are those with high stack numbers 5 and 6 and large
WNS 30–35 nm.
Also, because of increase in CEFF , they perform worse in
terms of power efficiency. Finally, power-efficient devices are
indicated in the top-left corner of the plot with typically low
CEFF but high REFF (worse performance). These are the device
with low stack (#2) and low WNS (<25 nm).
Overall, increasing WNS from 30 to 35 nm can yield further
performance gain of 8% (144%–152%) and an increase of
 4094
stack number from 3 to 4 can give another 5% gain (157%)
in the extreme case. Further increase in stack number (stack
height) results in degraded performance. This is consistent
with data reported in [17] for FinFET/NS cases. It should
also be noted that from a power perspective, an optimum stack
number 2 (larger WNS ) and stack number 3 (intermediate WNS )
are desired.
V. C ONCLUSION
In this article, using a full DTCO framework, we have
done extensive and systematic design space optimization and
study of FinFETs and GAA NS-FETs at industry-relevant
3-nm dimensions. Simultaneous impact of SCE (SSAT , DIBL),
intrinsic (RCHANNEL ), and extrinsic (REXT ) resistances and
device and parasitic capacitances are included to understand
performance–power tradeoff scenarios while fully optimizing
CPP dimension parameters (L G , TSP , and L CNT ), at the same
time keeping base PAs same. Impact of migrating from a
process realistic taper fin profile to highly process challenging
vertical profile can already result in substantial performance
(speed-at-iso-leakage) improvement (+16%).
Furthermore, at similar WEFF /footprint GAA and stack-
height NSs can still provide better performance than vertical
FinFETs (+19%) by further improving SSAT as well as REFF
even at the same reference CPP dimensions. At fully opti-
mized cases, all three devices show improvement with further
increase in spacer thickness (6–8 nm), predominantly by CEFF
reduction and SSAT improvement. Obviously, as SSAT improve-
ment is maximum for Fin (taper), it shows maximum speed-
at-iso-leakage gain (+15%) followed by Fin (vertical) +10%
and GAA NS (+9%). Overall, GAA NS provides 18% (126%–
144%) gain over Fin (vertical) devices. Further utilizing the
flexibility in stack number and WNS , we show that NSs can
provide additional room to optimize the performance–power
tradeoff scenarios. From the speed-at-iso-leakage perspective,
up to 157% gain is possible by stack number and WNS
increases from 3 to 4 and 30 to 35 nm with respect to Fin
(taper). This translates to an impressive 29% speed-at-iso-
leakage gain with respect to Fin (vertical), thereby providing
a continued path for CMOS scaling.
ACKNOWLEDGMENT
The authors would like to thank colleagues at IMEC Devin
Verreck and Geoffrey Pourtois for providing logistics support.
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