Proceedings of the 19th
IEEE International Conference on Nanotechnology
Macau SAR, China, July 22-26, 2019
Effects of interface trap charges on the electrical characteristics of back-gated 2D
Negative Capacitance FET
Chunsheng Jiang1, 2, *, Le Zhong1, 2, and Lei Xie1, 2
1
Microsystem & Terahertz Research Center, China Academy of Engineering Physics, Chengdu 610200, China
2
Institute of Electronic Engineering, China Academy of Engineering Physics, Mianyang 621999, China
E-mail: jiangchunsheng@mtrc.ac.cn
Abstract—In this work, a fully analytical compact drain
current model of back-gated two-dimensional (2D) negative
capacitance (NC) FET including interface trap charges has
been developed by solving Poisson's, drift-diffusion and 1-D
Landau-Khalatnikov equations, and it is validated against
the experimental data. In addition, the impact of interface
trap charges on the electrical characteristics of the back-
gated 2D NC-FET is investigated systematically based on
the model. It is found that the subtresdhold swing (SS) and
on-off current ration ( I𝐨𝐧 /𝐈𝐨𝐟𝐟 ) are seriously degraded
because of the presence of interface traps at 2D
channel/oxide interface and 2D NC-FET with a big 𝐭 𝐟 is
more immune to the degradation induced by the interface
traps.
Keywords—2D Negative Capacitance FET; ferroelectric
gate dielectric; analytical model; interface trap charges; low
power applications
I. INTRODUCTION
Power dissipation has been one of biggest constraints
for nanoscale metal-oxide-semiconductor field-effect-
transistors (MOSFETs) in sub-10 nm regime [1]. Most
efficient technique to reduce both dynamic and static
power dissipation is to lower the power supply voltage
( Vdd ) of modern transistors. Minimum power supply
voltage (Vdd ) is limited by the subthreshold swing (SS) of
Vdd ≥SS⋅ log10 (Ion /Ioff ). Herein, Ion and Ioff are the on-
state and off-state currents, respectively. Unfortunately,
the so-called Boltzmann limit puts a fundamental
limitation on the minimum of SS in traditional MOSFETs
( SS≥ 2.3kB T/q ) [2]. Particularly, the minimum SS of
conventional MOSFETs can’t be below 60 mV/dec at
room temperature (RT), even for cutting-edge FinFET
technology.
Lately, the negative capacitance transistor (NC-FET)
with two-dimensional (2D) semiconductors[e.g., transition
metal dichalcogenides (TMDs): MoS2 and WSe2] has been
proposed as one of most promising candidates in sub-10
nm regime due to its lower power and excellent noise
characteristics [3-5]. A SS below 60 mV/dec at RT has
been achieved in a range of gate voltage, although the
operating mechanism of these 2D NC-FETs is ambiguous.
In these 2D NC-FETs, an oxide buffer layer (e.g. SiO2,
Al2O3, HfO2) between the ferroelectric and the
semiconductor is generally needed for a high-quality
interface. However, there is still an interface trap density
ranging from ~1 × 1011 to 2 × 1013 cm−2 eV−1 at 2D
semiconductor/oxide interface, which will degrade
subthreshold behavior of 2D FETs and 2D NC-FETs [6-8].
A physics-based compact model including interface trap
978-1-7281-2892-4/19/$31.00 ©2019 IEEE
charges is indispensable for investigation of the working
mechanism and optimization of 2D NC-FETs.
In this work, a fully analytical drain current model of
back-gated 2D NC-FET including interface trap charges
has been proposed and this model is calibrated to the
experimental data. In addition, the impact of interface trap
charges on the static electrical characteristics of back-gated
2D NC-FET is studied systematically based on the model.
II. MODEL DERIVATION
The cross-sectional schematic of a back-gated 2D NC-
FET and its coordinates are shown in Fig. 1(a). Fig. 1(b) is
the small-signal equivalent capacitance network of the
device. Cit represents the interface trap capacitance. L is the
gate length; t ox is the thickness of buffer oxide layer; t f
is the thickness of FE layer. A 2D NC-FET can be treated
as a baseline 2D FET in series with a ferroelectric capacitor.
Therefore, with the help of the 1D steady-state Landau-
Khalatnikov [9] and Kirchhoff Voltage Law (KVL), one
can obtain
Vgs =Vmos +Vf =Vmos +2t f αQ av +4t f βQ3av +6t f γQ5av (1)
Qg Q ch +Q P1 +Q P2
Q av ≡ = (2)
WL WL
Q P1 =CP WVmos (3)
Q P2 =CP W(Vmos -Vds ) (4)
where α , β , γ are material-dependent Laudau
coefficients. Vgs is the gate voltage; Vmos is the
electrostatic potential of the interficial metal layer (IML)
between the ferroelectrical layer(FE) and buffer oxide
layer. 𝑄𝑐ℎ is the intrinsic charges of gate electrode.
Q P1 and Q P2 are the parasitic gate charges induced by
the parasitic gate-source (CP ) and gate-drain capacitances
( CP ), respectively. Thus, 𝑄𝑎𝑣 is the average charge
density of gate electrode. W is the gate width. The
electrical characteristics of the baseline 2D FET (i.e.,
Ids (𝑉𝑚𝑜𝑠 ) and Q ch (𝑉𝑚𝑜𝑠 )) can be found in our previous
paper[10]. Notethat, the term 1/𝜆2 in the expressions of
Ids (𝑉𝑚𝑜𝑠 ) and Q ch (𝑉𝑚𝑜𝑠 ) in Ref. [10] must be replaced
by (1 +
𝑞 2 𝐷𝑖𝑡
) /𝜆2 in this work to consider the impact of
𝐶𝑜𝑥
interface trap density ( Dit ). Herein, λ is the “scaling
length” of the device.
As shown in Fig. 2, the interface traps are assumed to
be amphoteric[11-13]. That is, when a 2D NC-FET works
in the depleted region ( 𝜙𝑠 <0 and Vmos < 𝑉𝐹𝐵0 ), the
interface traps are positively charged while they are
negatively charged when the device operates in the
accumulation region( 𝜙𝑠 >0 and Vmos > 𝑉𝐹𝐵0 ). VFB0 is
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the flat-band voltage, which is mainly determined by the
workfunction difference between the gate material and the
2D channel. Also, the fixed oxide charge also has a big
impact on VFB0 . Ef , Ei are Fermi energy level and mid-
gap energy level, respectively.
III. RESULTS AND DISCUSSIONS
Fig. 3(a) shows the transfer characteristics of a
fabricated 2D MoS2 NC-FET (Dev. #1) for both the
simulation and experimental data. The detailed fabrication
process can be found in our previous paper[3]. Fig. 3(b)
indicates the SS calculated from the transfer characteristics
of the same device when Vds =0.1 V for both the
simulation and experimental measurement. The negligible
hysteresis (∼12 mV) of this device is caused by the
damping effect of FE layer[14], which is beyond the scope
of this paper. The SS is extracted for both forward sweep
(SSFor ) and reverse sweep (SSRev ). Because there exists a
negligibly small interface trap density at the Al2O3/MoS2
interface, the device demonstrates the minimum
SSRev =52.3 mV/dec, SSFor =57.6 mV/dec, which are
smaller than the Boltzmann limit of 60 mV/dec at room
temperature. The deviation between analytical model and
experimental results in Fig. 3(b) could be caused by the
simplicity of the analytical model, which ignores the
damping effect of FE layer, series resistance of
source/drain contacts, and field-dependent mobility.
Fig. 3(c) denotes the transfer characteristics of another
fabricated 2D MoS2 NC-FET(Dev. #2) for both the
simulation and experimental data. The two devices have
distinct thickness of MoS2 and T2D =8.6 nm for the first
device (Dev. #1) while T2D =5.3 nm for the second device
(Dev. #2). Landau coefficients are obtained from the
experimental polarization-electric field ( P-E ) curve
utilizing the fitting method [10]. Fig. 3(d) presents the SS
calculated from the transfer characteristics of the Dev. #2
when Vds =0.1 V for both the simulation and experimental
measurement. Conversely, there’s a bigger interface trap
density of ~3×1012 cm-2 eV-1 for Dev. #2, which leads to
the degradation of SS. That is, both SSRev and SSFor of
the Dev. #2 are bigger than the thermodynamic limit of 60
mV/dec at RT. The simulated results agree well with the
experimental data, confirming the correctness of the
developed analytical model.
Fig. 4(a) shows the transfer characteristics for different
values of Dit of an n-type 2D MoS2 NC-FET with
tf =20 nm. Fig. 4(b) is the extracted SS varying with Ids
for various Dit of the same device. It’s easily seen that the
off-state current degrades significantly when Dit
increases. The underlying physics of this phenomenon can
be explained as follows. The interface traps are positively
charged when the device works in the subthreshold regime,
which causes the negative shift of threshold voltage. Note
that the device exhibits sub-thermionic (SS<60 mV/dec)
characteristics at room temperature when Dit =0 cm-2eV-1.
However, this sub-thermionic characteristic will be
shielded by the increment of Dit . It’s likely that the
existence of a certain amount of Dit leads to the only
unidirectional steep SS in many experimental works [8,
15]. Figs. 4(c) and 4(d) present the transfer characteristics
and the extracted SS varying with Ids for various Dit of
an n-type 2D MoS2 NC-FET with tf =50 nm.
164
Fig. 5(a) illustrates the minimum SS and on/off
current ratio (Ion /Ioff ) varying with Dit for both tf =20 nm
and tf =50 nm extracted from Figs. 4 (a)-(d). Ion is
defined as the drain current when Vgs =0.5 V. Ioff is
defined as the drain current when Vgs =0 V. It’s obvious
that the Ion /Ioff increases when tf increases for a given
Dit . Fig. 5 (b) shows the SS shift (∆SS) changing with Dit
for the baseline 2D FET, 2D NC-FET with tf =20 nm and
tf =50 nm, respectively. ∆SS is the increment of SS
caused by Dit , which is defined as
∆SS=SS(Dit )-SS(Dit =0) (5)
The 2D MoS2 NC-FET with tf =50 nm shows the
sub-thermionic characteristic with Dit in excess of
3×1012 cm-2eV-1 and has lower slope of ∆SS-Dit lines
compared with the baseline 2D FET. Thus, 2D MoS2 NC-
FET with a big tf is more immune to the degradation
induced by Dit . The underlying reason can be explained
by the definition of SS. The expression of SS colud be
derived from the small-signal equivalent network of the
back-gated 2-D NC-FETs as shown in Fig. 1(b). SS can be
given by,
2.3kB T C C C
SS= ⋅ (1+ it+ 2D) ⋅(1- device ) (6)
q Cox |CFE |
2
where Cit =q Dit . Cdevice is the areal capacitance of the
entire baseline 2D MoS2 FET and it can be expressed as
(C2D +Cit )⋅Cox
Cdevice =2Cp + (7)
C2D +Cit +Cox
and
dQav 1
CFE = = (8)
dVf 2αtf +12βtf Q2av +30γtf Q4av
When the device works in the subthreshold regime, the
channel is fully-depleted. Thus, C2D is assumed to be
0. ∆SS can be approximately calculated as,
2.3kB T Cit (2CP +Cox )
∆SS=SS(Dit )-SS(Dit =0) ≈ ⋅ ⋅ [1 − ]
q Cox |CFE|
(9)
It’s easily observed that ∆SS is approximately
proportional to Dit (and Cit ), which agrees well with Fig.
5(b).
IV. CONCLUSIONS
A fully analytical drain current model of back-gated 2D
NC-FETs including interface trap charges has been
developed and this model matches well with the
experimental data. The impact of interface traps on the
static electrical characteristics of back-gated 2D NC-FETs
is investigated systematically based on the model. It is
concluded that the NC effect can be screened by the
interface trap charges. Therefore, the impact of interface
traps needs to be considered in real device designs.
 ACKNOWLEDGMENT Vds Source

This work was supported by the Development Fund for L Drain

Source Drain
Incubation Programs of China Academy of Engineering T2D 2D semiconductor
Cp Cit C2D Cp
tox Oxide layer
Physics (CAEP) under Grant No. PY2019040. fs
Interfacial metal gate
tf FE layer Cox
Vmos
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165
 -5
(a) 10-6 (b)
10 120 Dit=0 cm-2eV-1
10-7 Dit=31012 cm-2eV-1

SS(mV/dec)
10-8 Dit=0 cm-2eV-1
100 Dit=61012 cm-2eV-1
Ids (A/mm)

10-9 Dit=31012 cm-2eV-1

Dit=91012 cm-2eV-1
10-10 Dit=61012 cm-2eV-1
80
10-11 Dit=91012 cm-2eV-1
10-12 Vds=0.1 V
10-13 tf=20 nm 60
10-14 Cp=3.54 fF/mm Vds=0.1 V, tf=20 nm, Cp=3.54 fF/mm
10-15 40
-1.0 -0.5 0.0 0.5 10-12 10-11 10-10 10-9 10-8 10-7
Vgs (V) Ids (A/mm)
-5
(c) 10 (d)
10-6 120 Dit=0 cm-2eV-1
10-7 Dit=0 cm eV -2 -1 Dit=31012 cm-2eV-1
10-8
SS(mV/dec)

Dit=31012 cm-2eV-1 Dit=61012 cm-2eV-1

Ids (A/mm)

10-9 100 Dit=91012 cm-2eV-1

Dit=61012 cm-2eV-1
10-10 Vds=0.1 V
Dit=91012 cm-2eV-1
10-11 80 tf=50 nm
10-12 Vds=0.1 V
Cp=3.54 fF/mm
10-13 tf=50 nm
10-14 Cp=3.54 fF/mm 60
10-15
-1.0 -0.5 0.0 0.5 10-12 10-11 10-10 10-9 10-8 10-7 10-6
Vgs(V) Ids(A/mm)

Figure 4. (a) The simulated transfer characteristics for different values of

Dit when t f =20 nm. (b) Extracted SS varying with Ids for various Dit
when t f =20 nm from Fig. 4(a). (c) The simulated transfer
characteristics for different values of Dit whe t f =50 nm. (d) Extracted
SS varying with Ids for various Dit when t f =50 nm from Fig. 4(c).
(a)1011 95 (b)
Vds=0.1 V 35 2D FET
90 2D NC-FET@tf=20 nm
1010 Cp=3.54 fF/mm
On/off current ratio,Ion/Ioff

30
SS shift (mV/dec)

85 2D NC-FET@tf=50 nm
SSmin(mV/dec)

109 80 25
20 Vds=0.1 V
10 8 Solid lines: tf=20 nm 75
Cp=3.54 fF/mm
Dash lines: tf=50 nm 70 15
107 65 10
106 60 5
Boltzmann limitation
55 0
105
0 2 4 6 8 10 12 0 2 4 6 8 10 12
Dit(1012 cm-2eV-1) Dit (1012 cm-2eV-1)

Figure 5. (a) The minimum SS and on/off current ratio varying with Dit
for both tf =20 nm and tf =50 nm. Ion is defined as the drain current
when Vgs =0.5 V. Ioff is defined as the drain current when Vgs =0 V. (b)
SS shift (∆SS) varying with Dit for the intrinsic 2D FET, 2D NC-FET
with tf =20 nm and tf =50 nm.

166