IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO.
5, MAY 2006
Highly Manufacturable Advanced Gate-Stack
Technology for Sub-45-nm Self-Aligned
Gate-First CMOSFETs
Seung-Chul Song, Member, IEEE, Zhibo Zhang, Craig Huffman, Jang H. (Johnny) Sim, Sang Ho Bae,
Paul D. Kirsch, Prashant Majhi, Rino Choi, Member, IEEE, Naim Moumen, and Byoung Hun Lee
Invited Paper
Abstract—Issues surrounding the integration of Hf-based
high-κ dielectrics with metal gates in a conventional CMOS
flow are discussed. The careful choice of a gate-stack process as
well as optimization of other CMOS process steps enable robust
metal/high-κ CMOSFETs with wide process latitude. HfO2 of a
2-nm physical thickness shows a very minimal transient charge
trapping resulting from kinetically suppressed crystallization.
Thickness of metal electrode is also a critical factor to optimize
physical-stress effects and minimize dopant diffusion. A high-
temperature anneal after source/drain implantation in a conven-
tional CMOSFET process is found to reduce the interface state
density and improve the electron mobility. Even though MOSFET
process using single midgap metal gate addresses fundamental
issues related to implementing metal/high-κ stack, integrating
two different metals on the same wafer (i.e., dual metal gate)
poses several additional challenges, such as metal gate separation
between n- and pMOS and gate-stack dry etch. We demonstrate
that a dual metal gate CMOSFET yields high-performance devices
even with a conventional gate-first approach if an appropriate
metal separation between band-edge metal for nMOS and pMOS
is incorporated. Optimization of dry-etch process enables gentle
and complete removal of two different metal gate stacks on ultra-
thin high-κ layer.
Index Terms—Boron diffusion, charge trapping, CMOSFET,
dual metal gate, electron mobility, equivalent oxide thickness
(EOT), gate first, hafnium, HfO2 , Hf-silicate, high-κ, metal gate,
NH3 , TiN.
I. INTRODUCTION
V ARIOUS hafnium-based high-κ materials are being
considered as candidates for use in high-κ gate stacks at
nodes of 45 nm and below [1]–[4]. The materials and process
have been extensively studied, and they have been considered
for use in semiconductor production, especially for low power
Manuscript received July 6, 2005; revised January 23, 2006. The review of
this paper was arranged by Editor H. Shang.
S.-C. Song, J. H. Sim, S. H. Bae, and R. Choi are with SEMATECH, Austin,
TX 78741 USA (e-mail: s.c.song@sematech.org).
Z. Zhang and C. Huffman are Texas Instruments Incorporated assignees at
SEMATECH, Austin, TX 78741 USA.
P. D. Kirsch, N. Moumen, and B. H. Lee are IBM assignees at SEMATECH,
Austin, TX 78741 USA.
P. Majhi is an Intel Corporation assignee at SEMATECH, Austin, TX 78741
USA.
Digital Object Identifier 10.1109/TED.2006.872700
0018-9383/$20.00 © 2006 IEEE
979
application [5], [6]. Given this history and maturity, integrating
them into the production flow of smaller scale devices has been
widely demonstrated [1]–[6], even though many integration
issues remain to be resolved, especially with metal gate
technology.
Metal gate has been considered as a technology option
for the 45 nm node [7], [8]. Several different approaches to
integrating a metal/high-κ stack into a CMOSFET flow have
been proposed [9]–[11]. A replacement gate approach that
implements a metal/high-κ gate stack using a dummy gate
after high temperature source/drain (S/D) anneal has received
considerable attention [9], but the difficulties of integration and
potential yield problem were general concern on this approach
[9]. Fully silicided (FUSI) gate technology is also extensively
studied recently mainly because it is relatively easy to integrate
[10], but it is still considered a transitional solution to full
metal gate technology since it cannot be free from the reactions
between the poly gate and high-κ, such as dopant penetrations
and equivalent oxide thickness (EOT) increase [11].
This paper will review various technical challenges in a gate-
first approach to fabricate metal/high-κ stack before the S/D
anneal step as in the conventional CMOSFET flow [12]. This
approach requires several innovative processes to make this
sequence compatible with conventional CMOSFET technology,
such as dual work-function metal gate formation, gate pat-
terning, and metal removal with a minimal damage on high-κ
dielectrics. Even though initial challenges are significant in
this approach, the final integration flow will be manufacturing
friendly compared to other approaches previously introduced.
To investigate the technical challenges involved in the gate-
first CMOS approach, a TiN gate with Hf-based high-κ di-
electrics is used because these materials are more mature than
other candidate materials even though the work function of
TiN is close to midgap [13]. Then, issues in dual metal gate
CMOS processes with a gate-first approach will be discussed
briefly.
II. EXPERIMENTAL
Ozonated water was used to clean the surface before
depositing the gate dielectric. This surface treatment tends
980
TABLE I
PROCESS FLOW OF FORMING HIGH-κ/METAL GATE STACK
to grow a 0.5–1 nm chemical oxide under the deposited
high-κ dielectric. After surface treatment, either Hf-silicate
(HfSiO) or Hf-dioxide (HfO2 ) was deposited. The HfO2 was
deposited by atomic layer deposition (ALD) using the pre-
cursors Hf[N(CH3 )C2 H5 ]4 with O3 as the oxygen source. In
depositing the Hf-silicate, the precursors Hf[N(CH3 )C2 H5 ]4
and Si[N(CH3 )C2 H5 ]4 were used with O3 as the oxygen source.
Si precursor flow was modulated to incorporate various percent-
ages of Si in the HfSiO. The resulting HfSiO had 20%–60%
SiO2 as confirmed by Rutherford backscattering (RBS)
analysis. NH3 anneal was performed after high-κ deposition at
700 ◦ C for 60 s.
A TiN layer was prepared by ALD using TiCl4 and NH3 ,
which was subsequently capped by 100 nm amorphous Si. The
TiN ranged from 2–10 nm. A composite amorphous-Si/TiN
stack, rather than a single TiN gate, was used to improve
thermal stability and simplify integration, especially during the
gate-stack dry etch [14]. The thick poly gate and minimal metal
gate are easier to integrate and manufacture. The poly Si/TiN
stack was etched in an inductive coupled plasma (ICP) chamber
using HBr chemistry.
The gate-stack dry etch stopped on the high-κ layer, followed
by ashing to remove the remaining resist and etch residue.
After the gate-stack dry etch, a physical bombardment using
Ar sputter preceded a wet-chemical removal of HfO2 . Then,
passivation with a nitride sidewall was used to prevent addi-
tional oxidation of the high-κ at the gate edge. BF2 with a
4 × 1015 -cm−2 dose at 20 keV was implanted as the P+ S/D.
For nMOSFET, As with a 5 × 1015 -cm−2 dose at 20 KeV was
implanted at the N+ S/D. A conventional CMOS flow was
used with a 1000–1100 ◦ C rapid thermal anneal (RTA) for
1–10s (1s means spike RTA) after the S/D implant. After the
whole process, a forming gas anneal was performed at 480 ◦ C
for 30 min.
Table I summarizes the process flow described above. Fig. 1
shows the transmission electron microscopy (TEM) cross sec-
tion of the gate-first MOSFET with the TiN/high-κ. As can be
seen, the physical gate length is less than 50 nm. The 10-nm
TiN gate is shown underneath the thick polygate. The TiN gate,
in exploded view, has a columnar grain structure, and the thin
nitride passivation layer is apparent below the oxide spacer and
sidewall of poly Si/TiN gate.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 1. TEM cross section of gate-first MOSFET with TiN/high-κ gate stack.
The physical gate length is less than 50 nm. The 10-nm TiN gate is shown
underneath the thick polygate.
III. RESULTS AND DISCUSSION
The proportion of Hf and Si in the HfSiO is an important
consideration. Some of published reports on optimum com-
position conflict each other [15]–[17]. Koike et al. [15], for
example, found that a high-Hf content is desirable to increase
the κ value. This conflicts with Koyama’s finding that high Si
content is desirable to reduce Fermi-level pinning [16]. To add
to the controversy, Watanabe et al. also found that higher Si
content increases stability and reliability [17].
In reality, however, the composition and thickness of the
HfSiO should be optimized in terms of mobility, scalability,
dopant diffusion, charge trapping, and reliability. It is necessary
to think of both composition and thickness simultaneously to
optimize final device performance. As the percentage of Si in
HfSiO increases, EOT increases with a corresponding reduction
in the value of the effective dielectric constant (keff ), as shown
in Fig. 2. A 10% variation in Si content yields a variation in
EOT of approximately 0.15–0.2 nm or more than 10% of the
total EOT. This is because EOT is a function of both physical
thickness and the composition of the material. It is therefore
important to obtain uniformity in both physical thickness and
chemical composition.
Fig. 3(a) demonstrates the effect of Si content on threshold
voltage (Vt ). The Vt was extracted by maximum Gm method
at linear region. In both nMOS and pMOS, the scaling is
linear for Vt with increases in Si percentage. The rise of Vt
with respect to higher Si content is well correlated with the
increase in EOT. One conclusion is that there is no signature
of Fermi-level pinning which is the case in a poly/high-κ
stack [16]. Fermi-level pinning is therefore not a concern in
the metal/high-κ stack with which this study was concerned.
SONG et al.: ADVANCED GATE-STACK TECHNOLOGY FOR SUB-45-nm SELF-ALIGNED GATE-FIRST CMOSFETs
Fig. 2. Effect of Si percentage in Hf-silicate on EOT and effective dielectric
constant (Keff ). As the percentage of Si in HfSiO increases, EOT increases
with a corresponding reduction in the value of the effective dielectric constant
(keff ). HfSiO films with fixed physical thickness of 4.0 nm were used.
Fig. 3. (a) Effect of Si percentage in Hf silicate on threshold voltage (Vt ).
Both nMOS and pMOS show linear increasing Vt with increases in Si percent-
age. (b) Effect of Si percentage in Hf silicate on threshold voltage (Vt ) variation.
pMOS Vt value distribution becomes wider with higher Si content.
Fig. 3(b), however, shows significant differences in Vt spread
between nMOS and pMOS devices. In nMOS, the distribution
of Vt is very tight regardless of Si content. In pMOS, though,
the Vt value distribution becomes wider with higher Si content.
There is a negative shift in Vt , indicating a positive charge in
the high-κ under pMOS conditions. The reason for the increase
in Vt spread reflects differences in boron diffusion into the
HfSiO film. Boron diffuses from the boron-doped polygate
through the TiN metal gate. Boron produces a positive charge
981
Fig. 4. Effect of Si percentage in Hf silicate on electron mobility. Increases in
Si content improve mobility because transient charge trapping is suppressed.
in the HfSiO, resulting in the Vt shift to the negative [18]. The
diffusion process is random, and this randomness yields the
wider Vt distribution. As more Si is available in the bulk of
the HfSiO layer, more stable Si–N bonds are formed. Nitrogen
is commonly added to high-κ film to enhance physical and
electrical properties [15], [19]. Its profile is a function of the
amount and location of Si in the HfSiO, affecting which atom
boron will bond together. With more stable Si–N bonds in the
HfSiO bulk, more boron is stopped within the HfSiO layer.
This relation between the amount of Si and boron diffusion is
confirmed by secondary ion mass spectroscopy (SIMS) analysis
[20]. With more boron in the bulk of HfSiO layer, a greater
positive charge is produced, resulting in a greater negative shift
in the Vt value. When less Si–N bond is available in the HfSiO
bulk, boron tends to pile up at the bottom intefacial layer, where
boron is mostly neutral.
In the gate-first pMOS approach, the pMOS polygate must
be implanted by boron to self-align with the S/D. It is therefore
impossible to eliminate boron from the gate, but reducing the
percentage of Si in the HfSiO minimizes the electrical effect of
boron on pMOS Vt . With a lower proportion of Si in the HfSiO,
boron is less likely to form the chemical bonds (e.g., Hf–N–Si)
that generate a positive electrical charge. Reducing the amount
of Si thus reduces the electrical effect of the boron diffusion,
although it does not eliminate the diffusion itself, which is
inevitable because of the columnar grain structure of the TiN
metal gate. The diffusion through the grain boundary of the
metal gate, however, can be somewhat controlled by controlling
the morphology of the metal gate itself. An amorphous metal
gate is preferred to minimize the diffusion of boron through
the grain boundary as in amorphous silicon gate [21]. Reducing
the thermal budget after the S/D implantation also retards
diffusion. Obtaining optimum performance, then, may depend
on an integrated approach to minimizing the effect of boron
diffusion. When it is necessary to use high Si percentage in the
HfSiO, it is more critical to retard the actual diffusion of boron.
Electron mobility is an important factor in nMOS perfor-
mance. Fig. 4 shows the effect of Si content in HfSiO on
electron mobility in the high-κ. Mobility was extracted using
982
Fig. 5. Thickness and composition effects on transient charge trapping.
Charge trapping can be reduced by absolute reductions in the volume (or
thickness) of the high-κ by suppressing crystallization and by reducing the
percentage of Si.
split C−V and dc Id −Vg curve measured at Vd = 50 mV
[22]. Fig. 4 clearly demonstrates that increases in Si content
improve mobility mainly because transient charge trapping
is suppressed. The Hf-based high-κ tends to trap charges
when an electrical bias is applied on the gate [23], which
is known to degrade electron mobility [24], [25]. The ori-
gin of transient charge trapping in Hf-based high-κ is not
fully understood, but seems to be related to an oxygen va-
cancy in the HfO2 portion [26], [27], which can act as a
shallow trap. Increasing the Si percentage in HfSiO reduced
the HfO2 portion and consequently reduced the transient
charge trapping. This, in turn, enhances electron mobility,
which is closer to intrinsic value. However, this conflicts with
earlier requirements for high-performance applications because
it also increases EOT. Because a thinner EOT is desired for
high-performance applications, there is a conflicting interaction
between the two goals (i.e., high Si content decreases EOT, but
increases charge trapping).
HfSiO composition and physical thickness are both impor-
tant factors in determining charge trapping and EOT. Thinner
HfSiO results in less charge trapping simply because there is
a less volume of material to trap charges. But reducing the
percentage of Si and suppressing the crystallization of HfO2
also reduce the charge trapping. Thus, as is shown in Fig. 5,
charge trapping can be reduced by absolute reductions in the
volume of the high-κ, by suppressing crystallization and by
reducing the percentage of Si. The reduction in charge trapping
as a result of decreasing EOT is more significant as the ratio of
Si in HfSiO is reduced. At about 3 nm, charge trapping becomes
negligible regardless of Si content in HfSiO. In HfO2 , charge
trapping is most sensitive to physical thickness and, at about
2 nm, charge trapping almost disappears. For all percentages of
Si, charge trapping is reduced simply as a result of the decrease
in the total volume. Even so, scaling down the thickness is more
effective when the percentage of Si is reduced. Another factor
contributing charge trapping is the amount of crystallization
in HfO2 . Crystallization creates grain boundaries in the film,
which could in turn provide more traps. Distorted chemical
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 6. Effect of physical thickness of HfO2 on EOT and Keff . As HfO2
thickness decreases, the bottom interfacial layer, which varies much less, be-
comes a greater proportion of the combined thickness. As the bottom interfacial
layer, which has a relatively lower κ value, becomes a greater portion of the
combined thickness, the overall κ value decreases.
bonding at the grain boundary could create additional trapping
sites [28]. Reducing physical thickness appears to be effective
in suppressing the crystallization of HfO2 .
Fig. 6 shows the effect of HfO2 physical thickness on EOT
and keff . In the figure, physical thickness is expressed as a
combination of the high-κ and bottom interfacial layers, which
is used with EOT to calculate the keff value. Under the exper-
imental conditions for this study, the use of O3 as an oxygen
source has the effect of increasing oxide thickness in the bottom
interfacial layer. Thicker high-κ tends to grow more bottom
oxide due to longer exposure to the O3 during the HfO2 deposi-
tion process. Increasing the bottom interfacial layer thickness
has the effect of decreasing the overall κ value, but in fact
the overall keff value decreases as the high-κ becomes thinner.
The reason is that as high-κ thickness decreases, the bottom
interfacial layer, which varies much less with respect to high-κ
thickness change, becomes a greater proportion of the com-
bined thickness. As the bottom interfacial layer, which has
a relatively lower κ value, becomes a greater portion of the
combined thickness, the overall κ value decreases. Ultimately,
EOT sensitivity to physical thickness is not as great as to
pure SiO2 , and the control of the composition of the high-κ
material may be more important than the control of its phys-
ical thickness. As shown in Fig. 6, a variation of 1 nm in
physical thickness results in a difference ∼ 0.1 nm in EOT.
In fact, physical thickness control is less than ±0.5 nm
(3 sigma), which allows relatively large process latitude.
In Fig. 7, a TEM plane view is used to explore the morphol-
ogy of 2 and 4 nm HfO2 films and the crystallization in the
two materials. The 4 nm material shows a clear grain boundary
and high crystallization, while the 2-nm film shows virtually
none. The result is almost no charge trapping in the 2-nm film
and subsequent improvements in dc mobility. Several detailed
studies on thin-film crystallization demonstrate the kinetics of
phase transformation with respect to the physical thickness of
the thin film [29], [30]. Crystallization in 2 nm HfO2 is kineti-
cally suppressed due to two-dimensional phase transformation
[30], which takes much longer to crystallize. Below a certain
SONG et al.: ADVANCED GATE-STACK TECHNOLOGY FOR SUB-45-nm SELF-ALIGNED GATE-FIRST CMOSFETs
Fig. 7. TEM plane view of (a) 4 nm and (b) 2 nm HfO2 . Crystallization in
2 nm HfO2 is kinetically suppressed due to 2-D phase transformation, which
takes much longer to crystallize.
critical thickness (∼ 2 nm HfO2 in our case), the crystallization
becomes extremely slow and may be prevented in a normal
CMOS process flow.
The improvement in dc mobility in the 2 nm HfO2 films,
however, cannot be due solely to suppressing crystallization.
Part of the improvement appears to be due to the amorphous
character of the film and reduced remote coulomb scattering.
Different κ values across the crystalline grains and a rougher
surface at the interfacial boundary result in overall nonunifor-
mity throughout the channel length causing carrier scattering
[31], [32]. The absence of such nonuniformity owing to the
amorphous nature of the film allows the 2 nm HfO2 to improve
the pulsed mobility as well as the dc one, as compared to
thicker HfO2 .
κhigh-κ
Tphysical = · EOT
κSiO2
κhigh-κ
ln Jg = −A · · EOT + B.
κSiO2
Equation (1) expresses the relationship between the phys-
ical thickness and EOT with regard to κ values of high-κ
and pure SiO2 , and (2) shows how the gate leakage current
density (Jg ) is expressed by EOT. Constants A and B in
983
(2) are fitting parameters related to barrier height and traps
in the dielectric. As shown in Figs. 5 and 7, thinner high-κ
is desirable to reduce the transient charge trapping and suppress
crystallization and must be scaled down for high-performance
applications. But as the physical thickness is reduced, Jg
increases, which is contrary to what is desired. Jg increases
exponentially as EOT scales and more rapidly as the κ value
of high-κ film becomes higher, as described in (2). That is,
as the high-κ gets thinner, the leakage current reduction from
SiO2 becomes less. Therefore, while high-κ scaling is good,
aggressive high-κ scaling can undermine the benefit of low gate
leakage of the high-κ device. In other words, thickness must
be scaled down within the gate leakage current specification
of the application.
Choosing between scaling and composition control may de-
pend on the application’s specification. For high performance,
Hf content must be increased, thereby increasing the κ value
and reducing EOT. The result is more charge trapping in the
HfSiO with high Hf content. At the same time, physical thick-
ness should also be reduced to reduce charge trapping. In low-
power applications, physical thickness should be sufficient to
reduce the gate leakage. Since charge trapping increases with
thicker film, the Si content of such films should be increased to
minimize the charge trapping.
As noted earlier, nitrogen is incorporated into the film to
modify its electrical characteristics. The specific reasons for its
inclusion are to suppress crystallization, prevent boron pene-
tration, and reduce EOT by increasing the κ value [33]–[36].
Nitrogen, however, tends to degrade the quality of the inter-
face and degrade mobility [37], [38]. Therefore, accomplish-
ing these three purposes may require a sacrifice in mobility.
Since scaling thickness can reduce crystallization, nitrogen
concentration need not be as high as it might otherwise be.
Similarly, the maximum EOT reduction is achieved with about
5% nitrogen, while the introduction of nitrogen decreases the
transient charge trapping only to a point, after which there is an
anomalous and reverse effect. A 5%–7% nitrogen concentra-
tion seems most desirable. An effective method to incorporate
nitrogen is still a subject for further study.
As ALD TiN thickness increases, grain size and physical
stress on the underlying high-κ likewise increase. Our study
indicates that the film becomes more compressive as it becomes
thicker. The effect of physical stress on SiO2 quality is well
documented [39]; showing that chemical bonding is distorted
and even broken due to physical stress. A charge-pumping
measurement is used to evaluate the interface state; these mea-
surements indicate that increased stresses are associated with
greater ALD TiN thickness, which results in a higher interface
state and increased charge trapping. Fig. 8 shows the effect
of TiN metal thickness on mobility as a function of channel
(1) length. Because of the larger interface state and charge trap-
ping, thicker TiN degrades mobility in long-channel devices.
(2) Mobility is improved in thick TiN devices as the channel length
shrinks. The physical stress on the high-κ from the metal gate
diminishes as the size of the device diminishes, because less
grain is available to impose stress on the high-κ. Reducing
the metal gate thickness is therefore desirable to minimize the
adverse physical-stress effects on the underlying high-κ.
984
Fig. 8. Effect of TiN metal thickness on mobility. Thicker TiN degrades
mobility in long-channel devices because of the larger interface state and charge
trapping caused by physical stress on underlying high-κ.
Fig. 9. Effects of ALD TiN thickness on (a) Vt shift and (b) Vt distribution
within the wafer. As TiN thickness gets thinner, nitrogen becomes depleted,
reducing work function manifested by decreasing nMOS Vt and increasing
pMOS Vt . Due to enhanced boron diffusion, pMOS with thinner TiN results
in wider Vt distribution.
Finally, work function and dopant diffusion should also be
taken into account to determine the final metal gate thickness.
Fig. 9(a) and (b) shows the effect of ALD TiN thickness on
Vt shift and distribution. As the TiN becomes thinner, the
nMOS Vt decreases as well. pMOS Vt , however, increases with
thinner TiN, indicating that the work function decreases as TiN
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 10. Gate-edge profile comparing (a) O2 ashing and (b) NH3 ashing taken
after gate-stack dry etch. Due to the absence of oxygen in ashing process,
NH3 ashing results in less Si recess and bottom oxide “bird’s beak” at the
gate edge.
thickness reduces. It is found that the nitrogen content in TiN
diminishes as the TiN becomes thinner from RBS study. The
higher electronegativity of nitrogen is believed to increase the
work function of thicker TiN [40].
The thickness of TiN has additional effect on pMOS Vt . As
the TiN becomes thinner, pMOS Vt rises more than nMOS Vt
is reduced, demonstrating an effect other than work function
on the pMOS Vt resulting from TiN thickness. For pMOS,
boron diffuses into the high-κ and produces a positive charge,
resulting in a negative Vt shift. As the TiN becomes thinner, the
effect is increased due to the shorter distance and smaller
grain (i.e., more grain boundaries). As a result, Vt distribution
becomes wider and more random across the wafer due to boron
penetration. Therefore, even though the effects of physical
stress are somewhat relaxed as TiN becomes thinner, the effect
of the increased boron diffusion must necessarily be taken into
consideration in pMOS.
Since electron mobility is higher and Vt is lower, thin TiN
should be used in nMOS, but a thicker TiN should be used
in pMOS or another metal should be chosen that would allow
the advantages of a thin metal gate without the boron-diffusion
effects seen here. In short, the metal gate should be optimized
separately for each application: nMOS and pMOS. This can
be achieved by dual metal gate CMOS process, which will be
discussed later in this section.
As the size of devices decreases, gate-edge profile becomes
increasingly important. Fig. 10(a) and (b) shows how NH3 ,
instead of O2 , in the ashing process can improve the gate-edge
profile. According to Bersuker et al. [41] and Yeap et al. [42],
it is necessary to remove the high-κ in the S/D area to eliminate
SONG et al.: ADVANCED GATE-STACK TECHNOLOGY FOR SUB-45-nm SELF-ALIGNED GATE-FIRST CMOSFETs
Fig. 11. nMOSFET Vt rolloff curve with channel length comparing poly gate
and TiN metal gate. Vt rolloff was much more pronounced with a TiN metal
gate than with a poly gate device, since the TiN metal gate may block more halo
implantation than the poly gate.
or reduce process-induced charging and fringing field-induced
barrier lowering (FIBL) effects. HfO2 requires physical bom-
bardment before wet etch and is difficult to remove following
the postdeposition anneal (PDA), while HfSiO is removed quite
easily by an HF-based wet chemical solution. The wet-chemical
removal process, however, tends to “undercut” the high-κ un-
derneath the metal gate due to isotropic nature of wet-etching
process. When a nitride liner layer later fills the undercut, gate
leakage current rises, especially in short-channel devices due
to larger defects in the silicon nitride layer deposited at the
gate edge. Ashing process using NH3 gas eliminates this under-
cutting and the “bird’s beak” effect at the gate edge. When an
O2 ashing is used, oxygen diffuses rapidly through the high-κ
layer. The growth of bottom oxide underneath high-κ at the
S/D region consumes the Si layer and causes a Si recess in the
active area when the high-κ/bottom interfacial layer is removed.
Oxygen atoms can also diffuse laterally into the gate edge,
which increases the bottom oxide under the high-κ at the gate
edge, causing the “bird’s beak” appearance. This has the effect
of increasing EOT, especially for short-channel devices. The
use of a nonoxygen-based ashing process, in this case NH3 ,
resolves the problem.
Fig. 11 compares Vt rolloff characteristics with respect
to channel length (Lg ) between poly- and TiN metal gate
nMOSFET. It was found that Vt rolloff was much more
pronounced with a TiN metal gate than with a poly gate
device. The reason is that the TiN metal gate may block
more halo implantation than the poly gate, degrading short-
channel effects. It is necessary to have sufficient halo implan-
tation to offset the short-channel effect. An SIMS analysis
confirmed this explanation of the differences between TiN
metal and poly gate devices. Almost 40% of the implantation
dose is lost during implantation through the 5-nm (calculated
thickness through which halo implantation travels at the gate
edge) TiN layer as compared to a poly Si layer of the same
thickness. Moreover, implantation through the metal gate also
appears to push the metal atoms into the high-κ at the gate
edge, severely compromising dielectric integrity. Using an
985
Fig. 12. Comparison of interface state density measured by charge-pumping
method with respect to different spike anneal temperature. High-temperature
RTA anneals out the defects and enhances the characteristics of the interface
without significantly degrading other factors that had been of concern.
offset spacer or notched gate structure could minimize the
halo implantation through the metal gate layer. From the n
and pMOSFET device of Lg ∼ 50 nm with optimized halo
implantation, the subthreshold swing values are ∼ 110 and
∼ 115 mV/dec, respectively.
RTA should be performed after the S/D implantation, which
occurs after gate-stack formation in a conventional gate-first
CMOS flow. The high temperature applied to the high-κ/metal
gate stack becomes an issue because of crystallization [43]
or potential interactions among the materials [44], especially
metal gate and high-κ interface. These issues have led to the
assumption that RTA could be a showstopper for metal/high-κ
integration in a gate-first approach [45]. It also was thought
that the RTA issues might make metal/high-κ integration more
appropriate for a gate-last approach to manufacturing [46].
The gate-first approach, however, is significantly easier from
a manufacturing viewpoint; consequently, an attempt was made
to adopt it despite the perceived difficulties. Originally, it was
thought that in addition to the crystallization issues, the high
temperatures of RTA would yield variations in grain size and
orientation that would be unacceptable because of the resultant
degraded mobility [47]. High temperature RTA, however, has
recently been shown to offer significant advantages. It can
reduce point defects in HfO2 [48], resulting in strain-induced
self-organization [49] and improved mobility [50].
In this paper, we found that a higher spike anneal tempera-
ture resulted in less interface state density and better electron
mobility. As the spike anneal temperature was increased, the
interface state decreased significantly, and that decrease also
improved the mobility. Moreover, these benefits were achieved
without any degradation of dc mobility or increased tendency
to crystallize. When the metal gate, such as TiN, is thermally
stable with high-κ, no increase in EOT or shift in work function
was observed. Fig. 12 demonstrates the effect on interface
state density when different temperatures were applied during
the RTA with a “spike” temperature. High-temperature RTA
actually anneals out the defects and enhances the characteristics
of the interface without significantly degrading other factors
986
Fig. 13. Ion −Ioff of optimized TiN/Hf-silicate CMOSFET. At Ioff =
100 nA/µm, Ion = 1000 µA/µm and 480 µA/µm have been achieved for
n and pMOS, respectively, using Vdd = 1.1 V condition.
Fig. 14. Dual metal gate integration scheme using MEM method. Although
there are other possibilities, this MEM approach is considered the most flexible
integration schemes.
that had been of concern. The indication, then, is that when the
interface is poor, a high-temperature RTA is one approach to
improve the device characteristics. On the other hand, when the
quality of the interface is already good, the advantages of the
high-temperature anneal are not as obvious.
Fig. 13 indicates the improvements in performance that are
possible with the various optimizing procedures discussed here.
At Ioff = 100 nA/µm, Ion = 1000 µA/µm, and 480 µA/µm
have been achieved for n and pMOS, respectively, using Vdd =
1.1 V condition. The 3 nm HfSiO was used with 20% Si
content; the EOT was 1.2 nm. The overall effective dielectric
constant is ∼ 12, taking ∼ 0.6 nm of bottom interfacial layer
into account. The bottom interfacial layer has relatively higher
dielectric constant compared to pure SiO2 due to oxygen defi-
ciency in the layer [51].
Fig. 14 illustrates the integration scheme of the dual metal
into a CMOSFET. The present study used a metal-etch-metal
(MEM) manufacturing approach. The first step is the prepara-
tion of two different metals to be used for nMOS and pMOS.
This involved a metal-separation process and gate-stack dry
etch through different metal stacks within one wafer, as de-
scribed below. The high-κ and first-metal layers are deposited
on the Si substrate followed by the deposition of hardmask
and then photo resist. Once the hardmask layer is selectively
removed, the photo-resist layer is removed and the first metal
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006
Fig. 15. Electron and hole mobility from dual metal gate CMOSFETs with
TaSiN and Ru for n and pMOS, respectively. High values for electron and hole
mobility were obtained in both cases.
is etched selectively before removing the remaining hardmask.
During the hardmask removal, the first metal is exposed as
well as the high-κ. A second metal is added, followed by the
poly gate deposition. Etching through the gate, as shown, yields
contact with the double metal stack (left) and the single metal
(right). A device with a double metal stack (first-metal touching
on high-κ) could be an nMOSFET and the single-metal portion
(second metal on high-κ) could be a pMOSFET, or vise versa.
Although there are other possibilities, this is considered the
most flexible integration schemes. Two critical challenges still
remain: the high-κ must withstand the first-metal wet etch
and hardmask removal, and the gate etch must deal with two
different gate stacks on the same wafer. The processes of wet
etch and hardmask removal must be unique to HfO2 and HfSiO.
The hardmask material should be selected carefully so that its
removal does not affect the underlying high-κ.
Fig. 15 shows the electron and hole mobility from dual
metal gate CMOSFETs. The two metals chosen were TaSiN
for nMOS and Ru for pMOS. Tetra ethyl oxysilane (TEOS)
oxide was used as the hardmask. Since a TEOS hardmask is
not compatible with HfSiO, HfO2 was used for this experiment.
The appropriate selection of a hardmask material would allow
HfSiO in the dual metal gate integration as well. High values
for electron and hole mobility were obtained in both cases.
Selection of different metals may yield even more favorable
results in terms of work function and EOT.
IV. CONCLUSION
Incorporating high-κ and metal gate into a conventional
CMOS flow requires the gate-stack process as well as other
CMOS-process steps to be optimized. Optimizing composi-
tion and thickness of high-κ is important, as transient charge
trapping depends critically on both physical parameters of the
high-κ. From our study, HfO2 with a physical thickness of 2 nm
has almost no charge trapping with complete coverage of the
wafer. Finding the optimum metal thickness is also important in
preventing performance degradation induced by physical stress
SONG et al.: ADVANCED GATE-STACK TECHNOLOGY FOR SUB-45-nm SELF-ALIGNED GATE-FIRST CMOSFETs
of the metal film and suppressing dopant diffusion from the
poly gate. The composition and thickness of the metal gate
also have a great influence on Vt and device performance.
A high-temperature anneal after S/D implantation does not
seem to be a limiting factor in integrating a metal/high-κ stack
into a conventional CMOS flow. Recent findings show that a
high-temperature anneal enables structural relaxation of the
high-κ, improving the interface quality. A dual metal gate inte-
gration scheme has been demonstrated using a metal-separation
process. A careful choice of the hardmask material enables the
integration of both HfO2 and HfSiO high-κ into a flexible MEM
dual metal gate CMOS scheme.
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“Effects of structural properties of Hf-based gate stack on transistor per- [51] G. Bersuker, J. Barnett, N. Moumen, B. Foran, C. D. Young, P. Lysaght,
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[35] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and Seung-Chul Song (M’04) received the B.S. degree
L. Colombo, “Application of HfSiON as a gate dielectric material,” Appl. in materials science and engineering from the Uni-
Phys. Lett., vol. 80, no. 17, pp. 3183–3185, Apr. 2002. versity of Incheon, Incheon, Korea, in 1996, the M.S.
[36] M. A. Quevedo-Lopez, M. El-Bouanani, M. J. Kim, B. E. Gnade, degree in materials science and engineering, and the
R. M. Wallace, M. R. Visokay, A. LiFatou, J. J. Chambers, and Ph.D. degree in electrical and computer engineering
L. Colombo, “Effect of N incorporation on boron penetration from p+ from the University of Texas, Austin, in 1998 and
polycrystalline-Si through HfSixOy films,” Appl. Phys. Lett., vol. 82, 1999, respectively.
no. 26, pp. 4669–4671, Jun. 2003. He was with Motorola Semiconductor Product
[37] C. Choi, C. S. Kang, C. Y. Kang, R. Choi, H. J. Cho, Y. H. Kim, S. J. Rhee, Sector and Samsung Electronics during 2000–2002
M. Akbar, and J. C. Lee, “The effects of nitrogen and silicon profile on and 2002–2004, respectively, participating in 0.15-,
high-κ MOSFET performance and bias temperature instability,” in VLSI 0.13-, and 0.1-µm CMOS process integration and
Symp. Tech. Dig., 2004, pp. 214–215. device research. He is currently a Project Manager in the FEP Division,
[38] H.-J. Cho, C. Y. Kang, C. S. Kang, R. Choi, Y. H. Kim, M. S. Akbar, SEMATECH, Austin, TX, focusing on planar and nonplanar CMOS inte-
C. H. Choi, S. J. Rhee, and J. C. Lee, “The effects of nitrogen in HfO2 for gration and device research associated with dual metal gate and high-κ di-
improved MOSFET performance,” in Proc. Int. Semicond. Device Res. electric stack. He has authored or coauthored more than 50 conference and
Symp., 2003, pp. 68–69. journal papers.
[39] T.-C. Yang and K. C. Saraswat, “Effect of physical stress on the degra- Dr. Song received the Best Paper Award in the 1998 ESSDERC.
dation of thin SiO2 films under electrical stress,” IEEE Trans. Electron
Devices, vol. 47, no. 4, pp. 746–755, Apr. 2000.
[40] Y. Gotoh, H. Tsuji, and J. Ishikawa, “Measurement of work function
of transition metal nitride and carbide thin films,” J. Vac. Sci. Tech-
nol. B, Microelectron. Process. Phenom., vol. 21, no. 4, pp. 1607–1611,
Jul. 2003.
[41] G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B. H. Lee, J. Barnett,
S. Gopalan, G. Brown, Y. Kim, C. D. Young, J. Peterson, H.-J. Li,
Zhibo Zhang received the B.S. degree in engi-
P. M. Zeitzoff, G. A. J. H. Sim, P. Lysaght, M. Gardner, R. W. Murto,
neering physics from Tsinghua University, Beijing,
and H. R. Huff, “Integration issues of high-κ gate stack: Process- China, in 1990, the M.S. degree in electrical en-
induced charging,” in Proc. 42nd IEEE Int. Reliab. Phys. Symp., 2004,
gineering from the Chinese Academy of Sciences,
pp. 479–484.
Beijing, China, in 1993, and the Ph.D. degree in
[42] G. C.-F. Yeap, S. Krishnan, and M.-R. Lin, “Fringing-induced barrier
solid state physics from the Massachusetts Institute
lowering (FIBL) in sub-100 nm MOSFETs with high-κ gate dielectrics,” of Technology, Cambridge, in 1998.
Electron. Lett., vol. 34, no. 11, pp. 1150–1152, May 1998.
He was a Member of Technical Staff at Lu-
[43] H. Kim, P. C. McIntyre, and K. C. Saraswat, “Effects of crystalliza-
cent Technologies Bell Labs from 1998 to 2000,
tion on the electrical properties of ultrathin HfO2 dielectrics grown by
working on semiconductor process integration for
atomic layer deposition,” Appl. Phys. Lett., vol. 82, no. 1, pp. 106–108, system-on-a-chip applications. From 2000 to 2004,
Jan. 2003.
he was an Assistant Professor in electrical engineering at North Carolina
[44] K. P. Bastos, C. Driemeier, R. P. Pezzi, G. V. Soares, L. Miotti,
State University and conducted research on nanofabrication and nanoscale
J. Morais, I. J. R. Baumvol, and R. M. Wallace, “Thermal stability of
devices. He joined Texas Instruments Incorporated (TI), Austin, TX, in
Hf-based high-κ dielectric films on silicon for advanced CMOS devices,” 2004 and was an Assignee at SEMATECH’s FEP Division, Austin, TX,
Mater. Sci. Eng., B, Solid-State Mater. Adv. Technol., vol. B112, no. 2–3,
working on metal gate and high-κ dielectrics integration. He is currently
pp. 134–138, 2004.
with TI SiTD, responsible for transistor process integration for advanced
[45] M.-F. Wang, Y.-C. Kao, T.-Y. Huang, H.-C. Lin, and C.-Y. Chang,
CMOS technology.
“Thermal stability of PVD TiN gate and its impacts on characteristics
of CMOS transistors,” in Proc. 6th Int. Symp. Plasma- Process-Induced
Damage, 2001, pp. 36–39.
[46] J. Pan, C. Woo, C.-Y. Yang, U. Bhandary, S. Guggilla, N. Krishna,
H. Chung, A. Hui, B. Yu, Q. Xiang, and M.-R. Lin, “Replacement metal
gate NMOSFETs with ALD TaN/EP-Cu, PVD Ta, and PVD TaN elec-
trode,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 304–305, May 2003.
[47] R. Wallace, Article in High Dielectric Constant Material. New York:
Springer-Verlag, 2005. Craig Huffman received the B.S. degree in engi-
[48] G. D. Wilk and D. A. Muller, “Correlation of annealing effects on local neering physics from Southwestern Oklahoma State
electronic structure and macroscopic electrical properties for HfO2 de- University, Weatherford, in 1983.
posited by atomic layer deposition,” Appl. Phys. Lett., vol. 83, no. 19, He is a Texas Instruments Incorporated (TI),
pp. 3984–3986, Nov. 2003. Austin, TX, Assignee to SEMATECH, Austin, TX,
[49] G. Lucovsky, J. P. Maria, and J. C. Phillips, “Interfacial strain-induced working in the FEP Division. Currently, he supports
self-organization in semiconductor dielectric gate stacks. II. Strain-relief all metal gate etch activities for the advanced gate
at internal dielectric interfaces between SiO2 and alternative gate di- electrode evaluation team and the dual metal gate
electrics,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., integration team. Through this project, he has devel-
vol. 22, no. 4, pp. 2097–2104, Jul. 2004. oped etch processes to support the 100+ materials
[50] A. Callegari, P. Jamison, E. Cartier, S. Zafar, E. Gusev, V. Narayanan, evaluated by the FEP teams. Prior to his assignment
C. D. Emic, D. Lacey, M. Feely, R. Jammy, M. Gribelyuk, J. Shepard, to SEMATECH, he worked on BEOL etches for 90-nm node. During his
W. Anderson, A. Curioni, and C. Pignedoli, “Interface engineering for 20+-year career with TI, he has addressed a full spectrum of etch issues,
enhanced electron mobilities in W/HfO2 gate stacks,” in IEDM Tech. ranging from tool improvement projects to process development and transfer
Dig., 2004, pp. 825–828. to manufacturing as well as fab startups.
SONG et al.: ADVANCED GATE-STACK TECHNOLOGY FOR SUB-45-nm SELF-ALIGNED GATE-FIRST CMOSFETs
Jang H. (Johnny) Sim received the B.S., M.S., and
Ph.D. degree in electrical and computer engineering
from the University of Texas, Austin, in 2001, 2003,
and 2005, respectively.
He has been with SEMATECH, Austin, TX, as
an Intern. His M.S. research work was on the de-
vice characterization of HfSiON dielectric and fully
silicided NiSi metal gate. His Ph.D. work was on
electrical characterization and reliability of high-κ
and metal gate stack. He is currently working on
CMOS logic device design for 45 nm with the IBM
Systems and Technology Group, East Fishkill, NY. He is an author or coauthor
of more than 50 research publications.
Sang Ho Bae received the B.S. degree from the
University of Incheon, Incheon, Korea and the M.S.
degree from Yonsei University, Seoul, Korea, both in
material engineering.
After graduation, he worked for AMAT Korea,
and then started the Ph.D. degree program in elec-
trical and computer engineering at the University
of Texas, Austin in Spring 2002. Since September
2004, he has been with SEMATECH, Austin, TX,
working on advanced CMOS process (high-κ and
metal gate stack) development. He is currently a
SEMATECH Intern.
Paul D. Kirsch received the B.S. degree from the
University of Wisconsin-Madison, in 1995 and the
Ph.D. degree from the University of Texas, Austin,
in 2001, both in chemical engineering.
He has been with the IBM Systems and Tech-
nology Group, East Fishkill, NY, since 2001. He
is currently on assignment to SEMATECH, Austin,
TX, as Project Manager of the advanced gate di-
electric project. His work has focused on gate stack
development. He has authored or coauthored more
than 20 journal and conference papers in various
semiconductor research areas including high-κ dielectric surface and interface
chemistry, atomic layer deposition, and high-κ dielectric/metal gate devices.
He is the holder of several process development patents with IBM.
Prashant Majhi received the B.Tech. degree from
the Indian Institute of Technology, Madras, India, in
1996 and the Ph.D. degree in science and engineering
of materials from Arizona State University, Tempe,
in 2000.
He joined the Process Development Group at
Philips Semiconductors in The Netherlands in 2000
and had been the Project Leader in module devel-
opment for several CMOS and mixed signal process
technologies. In October 2004, he joined Intel Cor-
poration. He is currently at SEMATECH, Austin,
TX, as an Intel Assignee, managing the Planar CMOS Scaling and Advanced
Gate Electrodes Group. He has authored or coauthored more than 100 pa-
pers in journals and conferences and is the holder of several IC process
development patents.
989
Rino Choi (M’04) received the B.S. and M.S. de-
grees from the Department of Inorganic Materi-
als Engineering, Seoul National University, Seoul,
Korea, in 1992 and 1994, respectively, and the Ph.D.
degree in materials science and engineering from the
University of Texas, Austin, in 2004.
He was with Daewoo Motors Company from 1994
to 1999, where he worked as a Development and
Test Engineer. Since 1999, he has been studying var-
ious high-κ dielectrics and has published more than
50 journal and conference papers. After graduation,
he has continued his research on the electrical characterization and reliability
of advanced gate stacks at SEMATECH, Austin, TX.
Naim Moumen received the master’s degree in
colloidal chemistry and condensed matter from the
“Ecole Normal Suprieur,” Paris, France, in 1992
and the Ph.D. degree in physical chemistry from
the Pierre and Marie Curie University, Paris, France,
in 1996.
He joined IBM, East Fishkill, NY, as a Process
Engineer after a postdoctoral position at Clarkson
University. He worked on surface preparation and
defect reduction in CMOS fabrication, wet etching
of SiGe, and surface preparation for Si and SiGe
deposition. Since 2002, he has been assigned by IBM as Project Manager of
the advanced pre gate clean project at SEMATECH, Austin, TX, focusing on
specific need for high-κ deposition, dielectrics scaling, and metal electrode wet
etching.
Byoung Hun Lee received the B.S. and M.S. degrees
in physics from the Korea Advanced Institute of Sci-
ence and Technology, Daejeon, Korea, in 1989 and
1992, respectively, and the Ph.D. degree in electrical
and computer engineering from the University of
Texas, Austin, in 2000.
He worked at Samsung Semiconductor during
1992–1997 and has been with IBM, East Fishkill,
NY, since 2001. He has authored or coauthored more
than 200 journal and conference papers in various
semiconductor research areas including gate oxide
reliability, silicon-on-insulator (SOI) device and process, strained silicon de-
vices, and high-κ and metal gate process and devices. He is currently on assign-
ment to SEMATECH, Austin, TX, as Manager of advanced gate stack program,
managing clean project, high-κ dielectric project, metal electrode project, dual
metal gate CMOS integration project, and electrical characterization project.