3896
11, NOVEMBER 2014
High-Performance Vertical Gate-All-Around Silicon
Nanowire FET With High-κ/Metal Gate
Yujia Zhai, Leo Mathew, Rajesh Rao, Marylene Palard, Sonali Chopra,
John G. Ekerdt, Leonard F. Register, and Sanjay K. Banerjee
Abstract— We present a vertical gate-all-around Si nanowire
(SiNW) metal–oxide–semiconductor field-effect transistor with
high-κ dielectric and TiN metal gate. The process flow is fully
compatible with CMOS technologies. SiNWs are fabricated by
deep Si reactive ion etching, gate-stack is formed by atomic layer
deposition, and metal salicide is utilized as drain contact. The fab-
ricated p-type gate-all-around SiNW metal–oxide–semiconductor
field-effect transistors that have a gate length of 320 nm exhibit
excellent characteristics with ION /IOFF > 104 , subthreshold
slope of 87 mV/decade, and 25 mV/V of drain-induced barrier
lowering. Low-temperature characteristics are also presented.
The demonstrated devices have potential applications in novel
low-power logic circuits and as selection transistors for 4F 2
cross-point memory cells.
Index Terms— CMOS technology, deep Si etching, gate-all-
around, high-κ/metal gate, nanowire, salicide.
I. I NTRODUCTION
T HE ongoing downscaling of electronic devices has
become more challenging since dimensions are
approaching the physical limits of performance [1]. Short-
channel effects, e.g., subthreshold swing (SS) degradation
and drain-induced barrier lowering (DIBL), are caused by
the encroachment of electric field lines from the drain into
the channel region, thereby competing with the gate for the
channel depletion charge. DIBL effectively reduces the barrier
between source and channel [2], and consequently, reduces
the threshold voltage (Vth ). Theoretical studies indicate that
the scaling requirement is more relaxed for the gate-all-around
structure than for the planar or double-gate structures since
Manuscript received May 5, 2014; revised July 23, 2014 and
August 7, 2014; accepted August 26, 2014. Date of publication September 18,
2014; date of current version October 20, 2014. This work was supported in
part by the King Abdullah University of Science and Technology, Thuwal,
Saudi Arabia, in part by the National Science Foundation, Nanosystems
Engineering Research Center, through the Nanomanufacturing Systems for
Mobile Computing and Mobile Energy Technologies, and in part by the
National Nanotechnology Infrastructure Network Programs. The review of
this brief was arranged by Editor W. Tsai.
Y. Zhai, M. Palard, L. F. Register, and S. K. Banerjee are with the
Microelectronics Research Center, University of Texas at Austin, Austin,
TX 78758 USA (e-mail: yujia.zhai@utexas.edu; marylene@mer.utexas.edu;
banerjee@ece.utexas.edu).
L. Mathew and R. Rao are with Applied Novel Device Inc.,
Austin, TX 78758 USA (e-mail: leomathew@appliednoveldevices.com;
rajesh.rao@appliednoveldevices.com).
S. Chopra and J. G. Ekerdt are with the Department of Chemical
Engineering, University of Texas at Austin, Austin, TX 78712 USA (e-mail:
snchopra@utexas.edu; ekerdt@utexas.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2353658
0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO.
smaller natural length λ can be reached, and the wrapped
gate design provides optimal electrostatic control [3]–[7].
Therefore, vertical-channel nanowire gate-all-around metal–
oxide–semiconductor field-effect transistors (MOSFETs),
which are fabricated about a cylindrical pillar of Si, benefit
from both reduced short-channel effects and improved SS, as
well as potentially higher packing densities. Extensive simu-
lation and modeling studies have been done on 1-D nanowire
FETs [8]. Simulation shows that the low DIBL and SS
can be maintained if scaling laws are followed [9], [10],
e.g., simulation based on Boltzmann transport equation
indicates that silicon body diameter should be smaller than
roughly 2/3 of the channel length to maintain an SS below
80 mV/decade [11]. Modeling of mobilities in silicon
nanowire (SiNW) and simulation of nanowire FET with
high-κ dielectrics have also been reported [12], [13].
Vapor–liquid–solid nanowire growth is one well-known
approach to synthesizing SiNWs. In this technique, a metal
particle (typically Au) is used as catalyst for 1-D single-
crystal SiNW growth [14]. This approach is able to yield bulk
quantities of SINWs, and they can be in situ doped during
growth. While the length and diameter of the synthesized
nanowires have some variability, FETs fabricated with VLS
SiNWs have been reported with high mobilities [15], [16].
SiNWs can also be fabricated by superlattice nanowire pattern
transfer (SNAP). SNAP utilizes a thin-film superlattice, e.g.,
GaAs/Alx Ga(1−x) As to translate the nanowire pattern from
a template with nearly atomic level control over the width
and spacing [17]. Another popular technique to fabricate
SiNW for FETs is based on Si/SiGe thin-film superlattice.
Lithography defines the nanowire width, and following
anisotropic and isotropic etching forms the 3-D stacked
nanowires [18]. FETs with sub-10-nm nanowire diameter and
high-κ/metal gate-stack have been reported with high gain
transfer characteristics and low DIBL [19]. With a modified
process, -FET with independent gates operation has been
realized for potential power consumption reduction [20].
An alternative approach to fabricating SiNW arrays for
FETs is by deep silicon etching masked by dots pattern.
This scheme has the following merits. First, the fabrication
process is more straightforward and less complicated com-
pared with SNAP or 3-D stacked techniques, as superlattice
is not required. In addition, it is potentially more economical
if high throughput lithography is utilized. For example, we
have used nanoimprint lithography to fabricate large arrays
of highly ordered SiNW array [21]. Second, in our studies,
ZHAI et al.: HIGH-PERFORMANCE VERTICAL GATE-ALL-AROUND SiNW FET 3897

we found that etched SiNWs have a more uniform length and

diameter distribution compared with VLS growth. Third, if
NW is etched in epitaxial layers, in situ source/drain/channel
doping can be achieved before the etch. Finally, the vertical
configuration may enable novel 3-D integration concepts, such
as 3-D memory plus CMOS logic, as described briefly later.
Although a few vertical NW FETs using thermal SiO2
dielectric and amorphous silicon gate electrode have be
reported [22], [23], downscaling of the effective oxide thick-
ness (EOT) requires high-κ dielectrics to reduce gate leakage
current. Metal gates are also favored not only for eliminating
the polydepletion effect but also for screening surface optical
phonons that lead to intrinsic mobility degradation in the
high-κ stacks [24]–[27].
We present a fabrication scheme of a p-type gate-all around
SiNW MOSFETs utilizing atomic layer deposition (ALD)
of high-κ dielectric and titanium nitride metal gate. While
these research devices are not at the limits of scaling,
smaller devices would be possible by scaling the process. The
fabricated devices exhibit excellent performance with steep
SS and low DIBL. SiNWs were patterned by electron-beam
(e-beam) lithography and formed by deep Si reactive ion
etching (DSE) with metal salicide mask. Source and drain
doping are achieved before the nanowires are etched, and metal
salicides reduce the contact resistance.

II. P ROCESS D EVELOPMENT

To achieve the desired the p-n-p doping profile for pMOS,
we used epitaxial silicon wafers and predoped the wafer before
the nanowires were etched. The wafer had a highly doped
p-type substrate and a p-type epilayer (7–11-μm thick), where
the substrate served as the common source for the nanowire
MOSFETs. The n-type channels were doped by phosphorus
implantation with a dosage of 1 × 1013 cm−2 at 100 keV.
After 1-h 1000 °C activation annealing, the junction depth was
diffused to 470 nm below the wafer surface. The drains were
doped by boron implantation with a dosage of 5 × 1015 cm−2
at 20 keV, followed by a 10-s thermal activation at 1000 °C.
The simulation results predict a drain doping peak concentra-
tion of 1021 cm−3 and a junction depth of 150 nm, and peak
concentration in the n-type channels of ∼1017 cm−3 and a
channel length of ∼320 nm.
The sample was patterned by e-beam lithography after
doping. First, a 100-nm diameter hole array was patterned
using ZEP e-beam resist. Next, 20 nm of titanium followed
by 20 nm of nickel was deposited on the sample with e-beam
assisted evaporation, and a subsequent liftoff process formed
a metal dot array on the silicon surface. Metal/silicon salicide
was formed after a 600 °C 10-s rapid thermal anneal in N2 .
Thirty cycles of DSE realized the nanowire array with a height
of ∼720 nm. The aspect ratio of the nanowire is ∼1:8.
The fabrication process flow of SiNW MOSFETs is shown
in Fig. 1. First, 20 nm of Al2 O3 was deposited by ALD on the
nanowires as gate dielectric at 250 °C, followed by the plasma-
enhanced ALD 50-nm TiN for gate metal in NH3 atmosphere.
Then, a 50-nm SiO2 capping layer was deposited by plasma-
enhanced chemical vapor deposition (PECVD) to protect the
gate metal [Fig. 1(a) and (b)].
Fig. 1. Fabrication process flow of nanowire MOSFETs. (a) Fabricate SiNW.
(b) ALD Al2 O3 , ALD TiN, and PECVD SiO2 . (c) Photolithography pattern
gate and resist thinning. (d) SiO2 etching by BOE. (e) Remove resist. (f) TiN
etching by SC-1. (g) Remove SiO2 . (h) PECVD SiO2 for 250 nm. (i) Resist
spin on and thinning. (j) Anisotropic SiO2 etching. (k) Remove resist, deposit,
and pattern drain metal. (l) Photolithography and SiO2 etching to access gate
metal.
After the three-step deposition, photolithography defined
gate contact pads and unexposed photoresist completely buried
the nanowires. To vertically pattern the gate metal, a control-
lable O2 plasma etch-back process was performed to thin the
resist. Therefore, the resist only covered the bottom portion of
nanowires, as shown in Fig. 1(c). The exposed SiO2 capping
layer was removed by a 15-s buffered oxide etch (BOE)
[Fig. 1(d)], and the resist was stripped off [Fig. 1(e)]. After-
ward, SC-1 (NH4 OH:H2 O2 :H2 O = 1:1:5 at room temperature)
solution was employed to etch the upper portion of TiN to form
the wrapped-gate pattern [Fig. 1(f)], followed by SiO2 wet
etching [Fig. 1(g)]. Fig. 2 shows scanning electron microscopy
(SEM) images of a device with nine nanowires in successive
process steps: nanowires as-etched [Fig. 2(a)], resist etch back
[Fig. 2(b)], and TiN etch for gate pattern formation [Fig. 2(c)].
The gate covers the lower portion of the nanowires, and
the channel length is ∼320 nm. Gate overlap is primarily
determined by the O2 plasma thinning process. Although the
subsequent SC-1 wet etch is isotropic and may undercut the
gate metal, the impact can be minimized if the subsequent
TiN wet etch is well controlled.
To isolate the gate metal layer from the drain metal layer,
a 250-nm PECVD SiO2 film was deposited as the intermetal

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3898
Fig. 2. Tilted SEM image of the nine nanowires in successive fabrication
stages. (a) Nanowire as-etched, and the scale bar is 200 nm. (b) Resist etch
back. (c) TiN etch and gate pattern formation. (d) PECVD SiO2 deposition
and etch back.
Fig. 3. (a) Tilted SEM image of a single nanowire with surrounding TiN gate.
(b) Cross-sectional SEM image of a nanowire MOSFET. The cross section
that is created by FIB cuts through the nanowire core.
dielectric [Fig. 1(h)]. Similar to the gate vertical patterning,
resist was spun-on and thinned with a 130-s O2 plasma etch
back [Fig. 1(i)]. The PECVD SiO2 cap was removed by an
anisotropic CHF3 and O2 plasma etch [Fig. 1(j)] to uncover
the nanowires for drain metallization. As shown in Fig. 2(d),
a 5-min etch consumed approximately 350 nm of SiO2 and
the Al2 O3 gate dielectric on top of the nanowire was also
broken through. About ∼100-nm SiNW is exposed to the drain
metallization.
The drain contact pad was patterned by the second pho-
tolithography. A 150-nm nickel film was deposited by e-beam
assisted evaporation so that the metallization was formed with
the salicide on the nanowires [Fig. 1(k)]. To access the buried
TiN gate metal, contact windows through the PECVD SiO2
were opened by the third photolithography and 2-min BOE
[Fig. 1(l)].
A focused ion beam (FIB) was utilized to create a cross
section through a particular nanowire to obtain the cross-
sectional view of the fabricated nanowire MOSFET. A tilted
SEM image of a single nanowire with surrounding TiN gate
is shown in Fig. 3(a), and a cross-sectional SEM image of the
final device is shown in Fig. 3(b).
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014
Fig. 4. Measured transfer characteristics of silicon nanowire MOSFET.
Fig. 5. Measured output characteristics of SiNW MOSFET with 25 nanowires
in parallel.
III. D EVICE C HARACTERIZATION
The fabricated vertical SiNW MOSFETs were characterized
at room temperature using the substrate as the source. The
transfer characteristics (Id –Vg ) indicate that the SiNW behaves
as a pMOSFET (Fig. 4). This device has 25 nanowires in
parallel, with a channel length of approximately 320 nm.
Each nanowire has a diameter of 90 nm and a gate dielectric
of 20-nm Al2 O3 , i.e., ∼10-nm EOT. The gate voltage is swept
from 1 to −2 V with a step of −0.02 V, while VDS is kept at
−0.2 and −1.0 V. The Id –Vg curves show good dc character-
istics. The ON-state current achieved at VDS = −1 V and
VGS = −2 V is 11.8 μA, compared with an OFF-state
current below 10−10 A when VDS = −1 V and VGS = 1 V.
Considering that this device has 25 nanowires in parallel, each
nanowire contributes a current of ∼ 0.47 μA. The ION /IOFF
ratio extracted is 104 –105(VGS = VDS = −1 V for ION , and
VGS = 0 and VDS = −1 for IOFF ). The measured curve also
shows a very small threshold voltage (Vth ) rolloff with VDS :
the DIBL measured at IDS = 100 nA is 25 mV/V. The SS
of the device is 87 and 96 mV/decade at VDS = −0.2 and
−1.0 V (saturation region), respectively.
The measured output characteristics (Id –Vd ) are plotted in
Fig. 5. VDS is swept from 0 to −2 V, and VGS ramps from
0 to −1.5 V with a step of −0.5 V. This device exhibits
well-behaved long-channel p-MOSFET characteristics, with
good saturation of drain current with increasing VDS . The
transconductance (gm ) of the tested device is also extracted
ZHAI et al.: HIGH-PERFORMANCE VERTICAL GATE-ALL-AROUND SiNW FET
Fig. 6. Transconductance of SiNW MOSFET measured at VDS = −0.2 V.
Fig. 7. Low-temperature transfer characteristics compared with room-
temperature results and output characteristics (inset).
and plotted in Fig. 6 at VDS = −0.2 V. The maximum gm is
achieved at VGS = −0.56 V. The carrier mobility μ can be
approximately estimated by
gm L
μ=
W Cox VDS
where L is the channel length and W is the channel width.
Cox is the gate oxide capacitance. The extracted hole mobility
is 2.2 cm2 /V · s, which we believe is lower than the true value
because we cannot correct for source/drain series resistance in
our test structure. We believe we have high contact resistance
at the top of the nanowire to drain electrode, as the nanowire
top was exposed to a sequence of etching processes. It should
be improved by further optimization of the process flow.
The low-temperature performance of the fabricated devices
was also characterized at 77 K. The sample was cooled
down by liquid nitrogen (LN2 ), and the transfer character-
istic was measured. Fig. 7 shows the comparison of the
low-temperature and room-temperature transfer characteristics
with VDS = −0.2 V. Compared with the room-temperature
performance, steeper subthreshold slope, lower drive current,
and larger threshold voltage magnitude |Vth | are observed
at 77 K. The extracted SS at 77 K is 65 mV/decade, compared
with 87 mV/decade that was extracted at room tempera-
ture. The ON-state drive current at VGS = −2 V reduces
from 2.58 μA at room temperature to 0.73 μA at 77 K,
and the OFF-state current has a reduction of two magnitude
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3899
Fig. 8. Illustration of 3-D architecture that has an NVM plane above the
logic plane.
(from 10−11 to 10−13 A). The threshold voltage magnitude
|Vth | increases ∼0.24 V at 77 K.
We briefly describe some potential applications. These gate-
all-around nanowire MOSFETs can be utilized as selection
transistors for 4F 2 cross-point memory cells, where F is the
minimum lithographic dimension. The memory cells lie above
the selection transistors at the intersections of word lines and
bit lines. Another novel way of using these transistors could
be in vertical Flash nonvolatile memory (NVM) cells.
A novel 3-D architecture can also be envisioned with an
NVM plane using such SiNWs above a CMOS logic plane
for low-power computing. One could imagine storing the logic
values in registers or static random access cache memories in
the logic level in the NVM memory cells above, and shutting
off the logic blocks if they are not performing computing to
conserve power. Subsequently, as needed, the logic values can
be restored from the NVM plane to the logic plane. What
often makes such ideas impractical is the necessity to have
very high alignment accuracy between fully random access
memory cells, with the underlying logic devices. We propose
an innovative variation of this theme, by envisioning an ultra-
dense array of memory cells, which would have a much tighter
pitch than the underlying logic nodes that have to be stored.
(1)
Metal-filled via holes would project above the logic plane,
providing access to nodes that would be necessary for instantly
restoring the logic states in the underlying subcircuit. These
logic nodes could have a somewhat random and sparse spatial
arrangement, depending on the subcircuit. If the memory cell
density above is much higher than the density of the required
logic nodes, one could guarantee that at least one memory
cell would be in contact with each logic node. The second
innovation is to recognize that if one simply needs to store the
logic state locally in a nonvolatile fashion in the immediate
vicinity of the logic node, it is not necessary to have truly
random access to each of these memory nodes. Fig. 8 shows
the design of such a 3-D architecture with NVM Flash cells
made in vertical SiNW MOSFETs. For such a scheme, all the
NVM memory cells would be connected in parallel, with a
global word line and a global bit line (the universal source
contact in Fig. 8).
IV. C ONCLUSION
We have presented the process integration and device
characterization of a gate-all-around SiNW-based p-type
MOSFET. Nanowires are patterned by e-beam lithography
3900
and DSE. Metal salicide is utilized as etch mask during
nanowire formation, and it also reduces the drain contact
resistance of the MOSFET. ALD Al2 O3 and TiN are utilized
as the high-κ gate dielectric and gate metal. The device
exhibits a low SS of 87 mV/decade, a high ION /IOFF ratio
of >105 and a small DIBL of 25 mV/V. Low-temperature
performance also was characterized at 77 K. We also proposed
a 3-D architecture that enables the applications of these NW
MOSFETs as selection transistors for 4F 2 cross-point memory
cells.
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Authors’ photographs and biographies not available at the time of publication.