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Research Institute of Superconductor Electronics (RISE), Nanjing University, Nanjing 210046, China
Received August 4, 2018; accepted September 4, 2018; published online December 17, 2018
In order to obtain high-quality superconducting qubits, we employed a cold-development technique, using temperatures down to
−20°C, to fabricate Al/AlOx/Al Josephson junctions. Cold development greatly reduced the sensitivity of the electron-beam
resist to the developer, eliminated molecules of the electron-beam resist at trench edges, and improved the repeatability and
reliability of the nanopatterning process. The fabricated samples have well-defined geometries and increased dose margins, with
lateral sizes of 100 nm×100 nm on both silicon and sapphire substrates. Together with the bridge-free fabrication method we
used in these experiments, we believe that the cold-development technique can play an important role in quantum information
technology that employs superconducting qubits.
Josephson junction, cold development, electron-beam lithography, insulating substrates
Citation: W. Chen, J. Z. Pan, Z. Y. Xu, Y. Y. Lv, X. J. Zhou, X. C. Tu, J. Li, G. Z. Sun, and H. B. Wang, Fabrication of Al/AlOx/Al Josephson junctions on
silicon and sapphire substrates using a cold-development technique, Sci. China-Phys. Mech. Astron. 62, 067011 (2019), https://doi.org/10.1007/
s11433-018-9298-3
1 Introduction herence time is the key, because only when it is long enough
can a system have sufficient time to process quantum in-
Josephson junctions have attracted considerable attention, formation. The coherence time has a very close relationship
both because of their intriguing properties and their potential to the substrate materials and the fabrication process. In
applications as superconducting electronic devices. Such general, high-resistivity silicon and sapphire substrates are
devices include Josephson parametric amplifiers (JPAs) [1], promising candidates due to their small dielectric loss tan-
superconducting quantum interference devices (SQUIDs) gents (tanδ). In particular, junctions on sapphire substrates
[2], rapid single-flux-quantum (RSFQ) devices [3], single- can achieve relatively longer coherence times than those on
electron transistors (SETs) [4], superconducting quantum silicon substrates [13]. The Dolan bridge technique [14] is
bits (qubits) [5,6], and so on. Due to their long coherence the major fabrication process generally employed. However,
times and simple fabrication processes, Al/AlOx/Al Jo- a bridge-free technique has recently been proposed [15] that
sephson junctions are frequently used in superconducting appears strongly competitive, due to the absence of bridge
circuits and quantum computation systems [7-12]. The co- collapse. Electron-beam lithography (EBL) is usually used as
the nanopatterning technique, and methylmethacrylate
(MMA) and poly (methylmethacrylate) (PMMA) are nor-
*Corresponding authors (XueCou Tu, email: tuxuecou@nju.edu.cn; HuaBing Wang,
email: hbwang@nju.edu.cn) mally used as the bilayer electron-beam resists.
© Science China Press and Springer-Verlag GmbH Germany, part of Springer Nature 2018 phys.scichina.com link.springer.com
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-2
forward scattering, which lowers the nanopatterning quality normalized the measured areas (Wav×Lav) with respect to the
[28]. In our experiment, we therefore spun a conducting layer nominal value (100 nm×100 nm). Figure 4(b) shows the
of a water-soluble polymer (ALLRESIST Electra 92) onto dependence of the normalized junction area on the exposure
the sapphire substrates at 2000 r/min for 1 min (to a thick- dose and development temperature. The junction areas de-
ness of ~60 nm) and baked it at 90°C for 2 min. Before pend linearly on the exposure dose and are fitted with solid
development, we removed the conducting layer by immer- lines at the different temperatures. At 22°C, all data are
sing the sample in deionized water for 60 s at room tem- larger than the nominal area (the dotted horizontal line),
perature. indicating that we were not able to obtain the nominal
Using the same process as shown in Figure 1, we fabri- junction area (100 nm×100 nm) at room temperature. How-
cated 800 Al/AlOx/Al Josephson junctions with nominal ever, by developing the resists at lower temperatures, we
areas of 100 nm×100 nm. To evaluate the junction properties successfully obtained the nominal junction area with ex-
2
as qubits, the most direct method is obviously to measure the posure doses of 1353, 2081, and 3767 μC/cm at 6, −10, and
coherence time. However, due to the large number of arrayed −20°C, respectively. Additionally, the slopes of the fitted
junctions in the experiment, it is impossible to measure them lines show that lower development temperatures result in
individually and make a comprehensive comparison. Instead, lower deviations of the areas from the nominal value. In
we optimized the fabrication process and qualified the other words, there is great merit in using low-temperature
junctions by analyzing other important parameters, such as development to control the junction geometry. We found that
the junction geometry, consistency, and reliability. To this development at −20°C was sufficient to minimize the area
end, we mainly evaluated the lateral sizes and surface deviation, and it is easy to operate at this temperature in most
morphologies of the Al/AlOx/Al Josephson junctions to de- laboratories.
termine the optimum lithographic conditions. The junction area is sensitive to the experimental condi-
We observed the geometries of the Al/AlOx/Al Josephson tions. Thus, it is certainly helpful if the tolerance for the
junctions with a scanning electron microscope (SEM). For exposure-dose range is sufficiently large. In order to de-
each development temperature, we fabricated 100 junctions termine this relationship, we define an acceptable dose
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under different exposure doses from 300 to 5250 μC/cm . window to be one for which the deviations of the real
Figure 4(a) shows SEM images of four typical Al/AlOx/Al junction areas range from 90% to 110% of the nominal value.
Josephson junctions on silicon substrates with the same ex- Figure 4(c) shows the dose windows at different develop-
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posure dose (3500 μC/cm ) but different development tem- ment temperatures. We find that the dose window at −20°C
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peratures. The horizontal and vertical lines in the middle area can be up to 3302-4206 μC/cm for silicon substrates, which
2
are the marks left by measuring the junction sizes. Clearly, is considerably larger than that at 6°C (1116-1637 μC/cm ).
the junction sizes and morphologies depend strongly on both Lower development temperatures can therefore enlarge the
the development temperature and the exposure dose. As the dose window and consequently reduce the requirement on
development temperature and exposure dose decrease, the exposure doses.
areas of the Al/AlOx/Al Josephson junctions decrease as As mentioned above, Al/AlOx/Al Josephson junctions on
well. As usual, the junctions developed at room temperature sapphire substrates have longer coherence times than those
had large size deviations from the nominal value. On the on silicon substrates. However, the insulating properties of
contrary, the cold-developed samples exhibited considerably sapphire substrates prevent the EBL technique from produ-
reduced deviations. In the lower-temperature development cing good patterning, so it is difficult to fabricate the nominal
process, the diffusion coefficient D of the PMMA molecules pattern without a conducting layer. To solve this problem, we
decreases as [29]: sprayed an additional water-soluble conducting polymer
E ad / RT onto the resist to release charges before patterning with EBL.
D = Ae ,
Other than this, we followed the same process as we used for
where, A, ΔEad, R, and T are the diffusion constant, a positive the silicon substrates.
parameter with the dimensions of energy, the ideal gas Shown in Figure 5 are the results for samples on sapphire
constant, and the absolute temperature, respectively. The substrates. We obtained samples with the nominal junction
2
quantity ΔEad depends on the minimum kinetic energy re- area for exposure doses of 1353, 2081, and 3767 μC/cm at 6,
quired for PMMA molecules to push past some of their −10, and −20°C, respectively. We did not use any conducting
nearest neighbors and move into the next cage. Accordingly, layer for imaging, so the SEM images in Figure 5(a) look
the loss of PMMA molecules at trench edges is less than at somewhat blurred. However, the junction geometry is still
room temperature, as we have noted previously [17,18]. well-defined, indicating that the fabrication conditions used
In order to quantify the control of junction geometry in our for the silicon substrates can be adopted for samples on
process, we measured the junction sizes four times and then sapphire substrates as well. Note that the slopes of the fitted
obtained the averaged width (Wav) and length (Lav). We lines in Figure 5(b) are larger than those in Figure 4(b) for the
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-5
Figure 4 (Color online) (a) SEM images of four typical Al/AlOx/Al Josephson junctions on silicon substrates. The four figures correspond to the same
2
exposure dose (3500 μC/cm ) but to the different development temperatures of 22, 6, −10, and −20°C, respectively. (b) Dependence of the normalized
junction area on the development temperature. The dotted horizontal line represents the nominal area of 100 nm×100 nm. (c) The acceptable dose windows at
different development temperatures for the junctions on silicon substrates.
Figure 5 (Color online) (a) SEM images of four typical Al/AlOx/Al Josephson junctions on sapphire substrates. The four figures correspond to the same
2
exposure dose of 3500 μC/cm but to the different development temperatures of 22, 6, −10, and −20°C, respectively. (b) Dependence of the normalized
junction area on the development temperature. The dotted horizontal line represents the nominal area of 100 nm×100 nm. (c) The acceptable dose windows at
different development temperatures for the junctions on sapphire substrates.
same development temperatures, meaning that the accep- mising way to fabricate Al/AlOx/Al Josephson junctions for
table dose window is relatively narrower for the sapphire superconducting qubits for quantum information technology.
substrates.
This work was supported by the National Natural Science Foundation of
China (Grant Nos. 61727805, 61771234, 61501220, 61611130069, and
4 Summary 61521001), the National Key Research and Devlopment Programme of
China (Grant No. 2016YFA0301802), Jiangsu Provincial Natural Science
The cold-development technique has obvious advantages Fund (Grant Nos. BK20150561, and BK20160635), the Fundamental Re-
search Funds for the Central Universities, and Nanjing University In-
compared to the standard technique. It can dramatically en-
novation and Creative Program for PhD Candidate (Grant No. CXCY17-
hance geometry control and reliability, as it considerably 15). We thank Haifeng Yu for his valuable discussion.
reduces the junction-area deviations from the nominal value.
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