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SCIENCE CHINA

Physics, Mechanics & Astronomy


•Article• June 2019 Vol. 62 No. 6: 067011
https://doi.org/10.1007/s11433-018-9298-3

Fabrication of Al/AlOx/Al Josephson junctions on silicon and


sapphire substrates using a cold-development technique
*
Wei Chen, JiaZheng Pan, ZuYu Xu, YangYang Lv, XianJing Zhou, XueCou Tu , Jun Li,
*
GuoZhu Sun, and HuaBing Wang

Research Institute of Superconductor Electronics (RISE), Nanjing University, Nanjing 210046, China

Received August 4, 2018; accepted September 4, 2018; published online December 17, 2018

In order to obtain high-quality superconducting qubits, we employed a cold-development technique, using temperatures down to
−20°C, to fabricate Al/AlOx/Al Josephson junctions. Cold development greatly reduced the sensitivity of the electron-beam
resist to the developer, eliminated molecules of the electron-beam resist at trench edges, and improved the repeatability and
reliability of the nanopatterning process. The fabricated samples have well-defined geometries and increased dose margins, with
lateral sizes of 100 nm×100 nm on both silicon and sapphire substrates. Together with the bridge-free fabrication method we
used in these experiments, we believe that the cold-development technique can play an important role in quantum information
technology that employs superconducting qubits.
Josephson junction, cold development, electron-beam lithography, insulating substrates

PACS number(s): 85.25.Cp, 85.30.Mn, 03.65.Yz, 03.67.-a

Citation: W. Chen, J. Z. Pan, Z. Y. Xu, Y. Y. Lv, X. J. Zhou, X. C. Tu, J. Li, G. Z. Sun, and H. B. Wang, Fabrication of Al/AlOx/Al Josephson junctions on
silicon and sapphire substrates using a cold-development technique, Sci. China-Phys. Mech. Astron. 62, 067011 (2019), https://doi.org/10.1007/
s11433-018-9298-3

1 Introduction herence time is the key, because only when it is long enough
can a system have sufficient time to process quantum in-
Josephson junctions have attracted considerable attention, formation. The coherence time has a very close relationship
both because of their intriguing properties and their potential to the substrate materials and the fabrication process. In
applications as superconducting electronic devices. Such general, high-resistivity silicon and sapphire substrates are
devices include Josephson parametric amplifiers (JPAs) [1], promising candidates due to their small dielectric loss tan-
superconducting quantum interference devices (SQUIDs) gents (tanδ). In particular, junctions on sapphire substrates
[2], rapid single-flux-quantum (RSFQ) devices [3], single- can achieve relatively longer coherence times than those on
electron transistors (SETs) [4], superconducting quantum silicon substrates [13]. The Dolan bridge technique [14] is
bits (qubits) [5,6], and so on. Due to their long coherence the major fabrication process generally employed. However,
times and simple fabrication processes, Al/AlOx/Al Jo- a bridge-free technique has recently been proposed [15] that
sephson junctions are frequently used in superconducting appears strongly competitive, due to the absence of bridge
circuits and quantum computation systems [7-12]. The co- collapse. Electron-beam lithography (EBL) is usually used as
the nanopatterning technique, and methylmethacrylate
(MMA) and poly (methylmethacrylate) (PMMA) are nor-
*Corresponding authors (XueCou Tu, email: tuxuecou@nju.edu.cn; HuaBing Wang,
email: hbwang@nju.edu.cn) mally used as the bilayer electron-beam resists.

© Science China Press and Springer-Verlag GmbH Germany, part of Springer Nature 2018 phys.scichina.com link.springer.com
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-2

For practical applications, e.g., for superconducting qubits,


the sizes of the Al/AlOx/Al Josephson junctions are typically
a few hundred nanometers or even less. It is essential to
improve the fabrication process, especially for geometry
control and reliability. While resist development is generally
performed at room temperature, cold development can be a
promising alternative technique [16]. In a low-temperature
development process, the viscosity of PMMA is con-
siderably enhanced, and the dissolution rate of the PMMA
molecules is accordingly suppressed [17]. Consequently, one
expects fewer vanishing PMMA molecules at trench edges
than at room temperature, leading to a superior nano-
patterning quality [18]. In fact, cold development has been
applied to many nanofabrication processes, including the
fabrication of ultra-narrow silicon carbon nitride (SiCN)
resonators, 10-nm soft-X-ray zone plates, sub-10-nm elec-
tron-beam lithography, dense and high-aspect-ratio nanos-
tructures, etc. [19-23]. However, to our knowledge, cold
development has not yet been tried as a promising nano-
patterning technique for fabricating aluminum junctions.
In this work, we first fabricated a relatively large (246 nm×
275 nm) Al/AlOx/Al Josephson junction to test a bridge-free
technique. We connected the junction to a microwave an-
tenna and placed it in the middle of a 3D cavity resonator,
forming a 3D transmon qubit with a relaxation time T1∼2.2 µs.
To improve the geometry control and reliability of junction
fabrication, we employed the cold-development technique in
our fabrication process on both silicon and sapphire sub-
Figure 1 (Color online) (a) Schematic view of the double-angle alumi-
strates. We studied the development conditions system- nium-deposition process using a bridge-free technique. (b) The cross-
atically with 800 junctions and determined the optimum shaped gap after development. (c) Bottom layer of Al deposited at an angle
conditions under which one can achieve well-defined geo- θ1, covered with an in-situ oxidized layer. (d) Top Al layer deposited at an
angle θ2. (e) The as-prepared Al/AlOx/Al Josephson junction after lift-off of
metries and increased dose margins, even for samples down the resist.
to 100 nm×100 nm.

heat-treated it at 180°C for 210 s. We used an electron-beam


2 Junction fabrication and characterization writer (Raith EBPG5200) to pattern the resists. To define the
nano-scaled pattern accurately, we performed the EBL at an
We used a bridge-free technique to fabricate aluminium- accelerating voltage of 100 keV, with a beam resolution of
2
based Josephson junctions. Compared to the well-known 5 nm and a dose of 2000 μC/cm . In superconducting
Dolan bridge technique that employs a suspended resist, this quantum computing (SQC) applications, Al/AlOx/Al junc-
technique has no risk of bridge collapse [15]. In our ex- tions with lateral sizes of 200 nm have often been chosen by
periment, we used bilayer electron-beam resists to enable many groups in order to achieve a good balance between
easy lift-off of the resist. Figure 1 shows the concept of the fabrication difficulty and long coherence times for a two-
fabrication process and the main steps involved. The sub- level artificial atom [24]. At the beginning of the present
strates were 0.5 mm-thick, high-resistivity silicon. We used research, we also patterned our cross junctions with nominal
Micro Chem MMA(8.5)MAA EL11 and Micro Chem areas of 200 nm×200 nm. After EBL exposure, we immersed
950PMMA A4 for the bottom and top resists, respectively, the samples in the developer (methyl isobutyl ketone:iso-
marked as MMA and PMMA in Figure 1. After the sub- propyl alcohol=MIBK:IPA=1:3) for 90 s. The final pattern is
strates were cleaned, we first spun the bottom layer (MMA) shown in Figure 1(a). Due to the absence of a suspended
onto the substrate at 3000 r/min for 1 min (to a thickness of bridge, we can clean the substrate surface by applying argon-
~300 nm) and then baked it at 180°C for 4 min. We then spun plasma etching before the deposition procedure. We fabri-
the top layer (PMMA) onto the sample at the same speed and cated the aluminum film in an electron-beam-deposition
with the same time interval (to a thickness of ~200 nm) and facility. The double-angle aluminum-deposition process we
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-3

used is shown schematically in Figure 1, with the aluminum


film deposited along the directions of the grooves at an angle
of 45°. Because the total thickness of the bilayer electron-
beam resists (MMA and PMMA) is up to 500 nm, we can
avoid junction shorts with such a deposition angle. The
thicknesses of the bottom and top aluminum films were 30
and 70 nm. Before depositing the top layer, we oxidized the
bottom Al layer in pure oxygen for 20 min at a pressure of
50 Pa. Note that the electron-beam deposition, ion-beam
etching, and oxidation facilities are connected together as an
in-situ fabrication system (AdNaNo-Tek Ltd.). Since the Figure 2 (Color online) (a) Optical image of a 3D transmon qubit. (b)
connecting tubes are maintained under high-vacuum condi- Optical microscope image of the microwave antenna integrated with the
−10 Josephson junction. (c) Scanning electron microscope (SEM) image of the
tions (<10 Torr), interfacial degeneration between differ- Josephson junction with the size of 246 nm×275 nm.
ent materials can be reduced to some degree. We placed the
as-prepared samples in N-methyl pyrrolidone for lift-off of
the resist. Finally, we fabricated the Al/AlOx/Al Josephson
junction on the silicon substrate, with a real area of
246 nm×275 nm, which is larger than the design sizes. Fig-
ure 2 shows the 3D transmon qubit, which consists of a
Josephson junction, a 3D cavity, and a microwave antenna to
couple them together.
We measured the quantum properties of the 3D transmon
qubit at 20 mK. We confirmed the coherence properties of
this qubit using standard time-domain measurements
[25,26]. Typical Rabi oscillations and the relaxation time (T1)
are shown in Figure 3. The energy relaxation time is about
2.2 µs, which is comparable to that of other devices with the
same structure and similar sizes [15]. However, we re-
cognized that there was considerable room for improving the
repeatability and reliability of junction fabrication and for
increasing the coherence time. We therefore decided to de-
vote additional effort to exploring better lithographic con-
ditions. In the following experiments, we also fabricated
smaller samples, with sizes down to 100 nm×100 nm, to
reduce the decoherence caused by the tunnel barriers of the
Josephson junctions [24].

3 Cold development of resist


Figure 3 (Color online) Time-domain measurement of the coherence of a
3D transmon qubit. (a) Rabi oscillation and (b) relaxation from the first
We applied cold development in the fabrication process, excited state |1>.
using as substrates either 0.5 mm-thick, high-resistivity si-
licon or 0.4 mm-thick sapphire. The procedure we used for
spin-application of the MMA/PMMA resist are the same as temperatures. Because the ambient humidity is controlled at
those described in the previous section. We subsequently about 50% and the development time is only 90 s for each
exposed the substrates to electron beams in doses varied sample array, the effect of humidity can be ignored. The
2 2
from 300 to 5250 μC/cm in steps of 50 μC/cm . This wide process we used to fabricate junctions on the sapphire sub-
range of exposure doses enabled a detailed study of the cold- strates was basically the same as for silicon, but a conducting
development process. We patterned all the samples as 10×10 layer is necessary on the surfaces of the resists to avoid
arrays of 100 nm×100 nm cross junctions, and we used de- charge accumulation on the sapphire substrates [27]. A few-
velopment temperatures of 22, 6, −10, and −20°C, respec- nm-thick metallic layer like aluminum has usually been ap-
tively. We pre-packed the developing solution in sealed plied as the conducting layer. However, compared with a
beakers and stored them separately at the corresponding conducting polymer layer, a metallic layer causes significant
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-4

forward scattering, which lowers the nanopatterning quality normalized the measured areas (Wav×Lav) with respect to the
[28]. In our experiment, we therefore spun a conducting layer nominal value (100 nm×100 nm). Figure 4(b) shows the
of a water-soluble polymer (ALLRESIST Electra 92) onto dependence of the normalized junction area on the exposure
the sapphire substrates at 2000 r/min for 1 min (to a thick- dose and development temperature. The junction areas de-
ness of ~60 nm) and baked it at 90°C for 2 min. Before pend linearly on the exposure dose and are fitted with solid
development, we removed the conducting layer by immer- lines at the different temperatures. At 22°C, all data are
sing the sample in deionized water for 60 s at room tem- larger than the nominal area (the dotted horizontal line),
perature. indicating that we were not able to obtain the nominal
Using the same process as shown in Figure 1, we fabri- junction area (100 nm×100 nm) at room temperature. How-
cated 800 Al/AlOx/Al Josephson junctions with nominal ever, by developing the resists at lower temperatures, we
areas of 100 nm×100 nm. To evaluate the junction properties successfully obtained the nominal junction area with ex-
2
as qubits, the most direct method is obviously to measure the posure doses of 1353, 2081, and 3767 μC/cm at 6, −10, and
coherence time. However, due to the large number of arrayed −20°C, respectively. Additionally, the slopes of the fitted
junctions in the experiment, it is impossible to measure them lines show that lower development temperatures result in
individually and make a comprehensive comparison. Instead, lower deviations of the areas from the nominal value. In
we optimized the fabrication process and qualified the other words, there is great merit in using low-temperature
junctions by analyzing other important parameters, such as development to control the junction geometry. We found that
the junction geometry, consistency, and reliability. To this development at −20°C was sufficient to minimize the area
end, we mainly evaluated the lateral sizes and surface deviation, and it is easy to operate at this temperature in most
morphologies of the Al/AlOx/Al Josephson junctions to de- laboratories.
termine the optimum lithographic conditions. The junction area is sensitive to the experimental condi-
We observed the geometries of the Al/AlOx/Al Josephson tions. Thus, it is certainly helpful if the tolerance for the
junctions with a scanning electron microscope (SEM). For exposure-dose range is sufficiently large. In order to de-
each development temperature, we fabricated 100 junctions termine this relationship, we define an acceptable dose
2
under different exposure doses from 300 to 5250 μC/cm . window to be one for which the deviations of the real
Figure 4(a) shows SEM images of four typical Al/AlOx/Al junction areas range from 90% to 110% of the nominal value.
Josephson junctions on silicon substrates with the same ex- Figure 4(c) shows the dose windows at different develop-
2
posure dose (3500 μC/cm ) but different development tem- ment temperatures. We find that the dose window at −20°C
2
peratures. The horizontal and vertical lines in the middle area can be up to 3302-4206 μC/cm for silicon substrates, which
2
are the marks left by measuring the junction sizes. Clearly, is considerably larger than that at 6°C (1116-1637 μC/cm ).
the junction sizes and morphologies depend strongly on both Lower development temperatures can therefore enlarge the
the development temperature and the exposure dose. As the dose window and consequently reduce the requirement on
development temperature and exposure dose decrease, the exposure doses.
areas of the Al/AlOx/Al Josephson junctions decrease as As mentioned above, Al/AlOx/Al Josephson junctions on
well. As usual, the junctions developed at room temperature sapphire substrates have longer coherence times than those
had large size deviations from the nominal value. On the on silicon substrates. However, the insulating properties of
contrary, the cold-developed samples exhibited considerably sapphire substrates prevent the EBL technique from produ-
reduced deviations. In the lower-temperature development cing good patterning, so it is difficult to fabricate the nominal
process, the diffusion coefficient D of the PMMA molecules pattern without a conducting layer. To solve this problem, we
decreases as [29]: sprayed an additional water-soluble conducting polymer
E ad / RT onto the resist to release charges before patterning with EBL.
D = Ae ,
Other than this, we followed the same process as we used for
where, A, ΔEad, R, and T are the diffusion constant, a positive the silicon substrates.
parameter with the dimensions of energy, the ideal gas Shown in Figure 5 are the results for samples on sapphire
constant, and the absolute temperature, respectively. The substrates. We obtained samples with the nominal junction
2
quantity ΔEad depends on the minimum kinetic energy re- area for exposure doses of 1353, 2081, and 3767 μC/cm at 6,
quired for PMMA molecules to push past some of their −10, and −20°C, respectively. We did not use any conducting
nearest neighbors and move into the next cage. Accordingly, layer for imaging, so the SEM images in Figure 5(a) look
the loss of PMMA molecules at trench edges is less than at somewhat blurred. However, the junction geometry is still
room temperature, as we have noted previously [17,18]. well-defined, indicating that the fabrication conditions used
In order to quantify the control of junction geometry in our for the silicon substrates can be adopted for samples on
process, we measured the junction sizes four times and then sapphire substrates as well. Note that the slopes of the fitted
obtained the averaged width (Wav) and length (Lav). We lines in Figure 5(b) are larger than those in Figure 4(b) for the
W. Chen, et al. Sci. China-Phys. Mech. Astron. June (2019) Vol. 62 No. 6 067011-5

Figure 4 (Color online) (a) SEM images of four typical Al/AlOx/Al Josephson junctions on silicon substrates. The four figures correspond to the same
2
exposure dose (3500 μC/cm ) but to the different development temperatures of 22, 6, −10, and −20°C, respectively. (b) Dependence of the normalized
junction area on the development temperature. The dotted horizontal line represents the nominal area of 100 nm×100 nm. (c) The acceptable dose windows at
different development temperatures for the junctions on silicon substrates.

Figure 5 (Color online) (a) SEM images of four typical Al/AlOx/Al Josephson junctions on sapphire substrates. The four figures correspond to the same
2
exposure dose of 3500 μC/cm but to the different development temperatures of 22, 6, −10, and −20°C, respectively. (b) Dependence of the normalized
junction area on the development temperature. The dotted horizontal line represents the nominal area of 100 nm×100 nm. (c) The acceptable dose windows at
different development temperatures for the junctions on sapphire substrates.

same development temperatures, meaning that the accep- mising way to fabricate Al/AlOx/Al Josephson junctions for
table dose window is relatively narrower for the sapphire superconducting qubits for quantum information technology.
substrates.
This work was supported by the National Natural Science Foundation of
China (Grant Nos. 61727805, 61771234, 61501220, 61611130069, and
4 Summary 61521001), the National Key Research and Devlopment Programme of
China (Grant No. 2016YFA0301802), Jiangsu Provincial Natural Science
The cold-development technique has obvious advantages Fund (Grant Nos. BK20150561, and BK20160635), the Fundamental Re-
search Funds for the Central Universities, and Nanjing University In-
compared to the standard technique. It can dramatically en-
novation and Creative Program for PhD Candidate (Grant No. CXCY17-
hance geometry control and reliability, as it considerably 15). We thank Haifeng Yu for his valuable discussion.
reduces the junction-area deviations from the nominal value.
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