T1-3
Nanosheet-based Complementary Field-Effect Transistors (CFETs)
at 48nm Gate Pitch, and Middle Dielectric Isolation to enable
CFET Inner Spacer Formation and Multi-Vt Patterning
H. Mertens, M. Hosseini, T. Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Y. Oniki,
A. Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, K. Vandersmissen,
J.P. Soulie, A. De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G.T. Martinez, J. Geypen,
F. Seidel, K. Paulussen, P. Favia, J. Boemmels, R. Loo, P. Wong, A. Sepulveda Marquez, B.T. Chan, J. Mitard,
S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans
Imec, Leuven, Belgium, E-mail: hans.mertens@imec.be
Abstract
We report on Si nanosheet monolithic Complementary Field-Effect
Transistors (CFETs) at industry-relevant 48nm gate pitch, with
source-drains (SDs) and SD contacts formed for either bottom or top
devices. SD epi patterning at 30nm vertical N-P space and high-
aspect-ratio SD contact formation are successfully demonstrated.
Functional devices with excellent subthreshold slope (SSSAT=70-
75mV/dec) are reported for bottom and top devices, for both N- and
PMOS. Middle dielectric isolation (MDI) formed by SiGe
replacement processing is introduced as an enabler for monolithic
CFET inner spacer formation and multi-Vt patterning.
Introduction
Complementary Field-Effect Transistors (CFETs) with n- and
pFETs stacked on top of each other (Fig. 1a) have the potential to
reduce CMOS technology footprint compared to conventional CMOS
with n- and pFETs placed side by side [1]. Functional monolithic
CFET inverters have been reported for wide gate pitch [2-4]. In
addition, bottom p- and top nFETs have been demonstrated at 90nm
gate pitch [5], and top nFETs down to 55nm gate pitch [6], as
steppingstones towards CFET integration at scaled dimensions.
In this work, we address a subset of monolithic CFET integration
challenges at industry-relevant 48nm gate pitch: (1) bottom and top
source-drain (SD) epi integration and (2) high-aspect-ratio SD contact
(M0) formation. This enables device demonstration at 48nm gate pitch
for CFET configurations with either top or bottom device contacted
(Figs. 1b and c). To address limitations of the fabricated CFET
structures, middle dielectric isolation (MDI) is introduced and
morphologically demonstrated.
Device fabrication
The process flows for the device configurations depicted in Figs.
1b and c consist of a common backbone based on EUV patterning
(Fig. 2a) and two distinct branches for bottom- and top-device SD epi
integration (Figs. 2b and c, resp.). The active-area SiGe/Si epitaxial
layer stack contains a 30nm SiGe middle layer defining the separation
between bottom and top Si channels (Figs. 3-5). Dummy gates
patterned at 48nm pitch exhibit straight gate profiles both above and
adjacent to 75nm tall SiGe/Si nanosheet (NS) stacks (Fig. 3).
Bottom-device SDs were formed by partitioning the SD recess to
introduce a 3nm SiN cover spacer (CSP) that shields the top device
during bottom-device SD epi growth. SD recess 1 determines the CSP
bottom edge placement (Fig. 4a). SD recess 2 defines the cavity (Fig.
4b) for SD epitaxial growth (Fig. 4c). Top-device SDs were formed
after introducing an SiO2 isolation (ISO) layer that shields the bottom
device during top-device SD epi growth. A SiN liner (Fig. 5a) limits
oxidation of the underlying device structures during ISO fill and
densification. ISO etchback defines the ISO layer top level (Fig. 5b)
for top-device SD epitaxial growth (Fig. 5c).
M0 was formed by non-self-aligned patterning to circumvent the
complexity of gate plug formation required for self-aligned contact
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(SAC) patterning. End-of-process cross-sectional images show well-
defined M0 SD contacts for both bottom and top devices (Fig. 6).
Bottom-device M0 is as tall as 60nm. The physical gate length (27nm)
is longer than the patterned gate length, attributed to tapered SD recess
and to the absence of inner spacers. nFETs feature in-situ doped Si:P
SD epi. pFETs are based on undoped Si SD epi with boron HDD I/I
because the SDs are (without inner spacers) in contact with the SiGe
sacrificial layer (Fig. 4c), which complicates SiGe:B SD integration.
Electrical characteristics
IS-VGS characteristics for bottom p- and top nFETs (Fig. 7a) and for
top p- and bottom nFETs (Fig. 7b) confirm device functionality for
all four device configurations. The increasing drive current with
increasing M0 CD, including device failure for M0 top CD > 24nm
(Figs. 8a and b) emphasizes the importance of M0 CD and overlay
control. SAC patterning can alleviate these requirements [7].
RON,LIN is substantially higher for pFET than for nFET (Fig. 9),
attributed to the use of Si:B instead of in-situ doped SiGe:B SD for
pFET, motivated by the absence of inner spacers.
Middle Dielectric Isolation (MDI)
For the applied CFET epi stack with a thick SiGe sacrificial middle
layer, inner spacer formation based on lateral SiGe etch followed by
dielectric deposition and etchback is nontrivial (Fig. 10). A possible
solution is to segment the vertical N-P space into a SiGe1/SiGe2 stack
with higher Ge% for SiGe2 than for SiGe1. SiGe2 can be replaced by
MDI (e.g., SiN) to create a geometry with identical SiGe1 thicknesses
for inner spacer formation (Fig. 11). An additional benefit is that MDI
can simplify multi-Vt patterning by eliminating the need for lateral
recess of a soft mask below the top-device channel (Fig. 12). An MDI
formation feasibility demonstration is shown in Fig. 13. This structure
has segmented MDI and 66nm N-P space to create process margin for
independently contacting bottom and top devices (Fig. 1a).
Conclusions
We have demonstrated Si nanosheet n- and pFETs in a CFET
configuration with SDs formed for either bottom or top devices at
30nm vertical N-P space and 48nm gate pitch. In addition, we have
introduced MDI to enable inner spacer formation and multi-Vt
patterning. The reported concepts can contribute to the realization of
monolithic CFETs at industry-relevant dimensions.
Acknowledgements
The imec core program members, the European commission, local
authorities, and the imec pilot line are acknowledged for their support.
References
[1] J. Ryckaert et al., VLSI 2018, pp. 141-142.
[2] X. Wu et al., IEEE TED vol. 52, pp. 1998-2003, 2005.
[3] S.-W. Chang et al., IEDM 2019, pp. 254-257.
[4] C.-Y. Huang et al., IEDM 2020, pp. 425-428.
[5] S. Subramanian et al., VLSI 2020, pp. 1-2.
[6] M. Radosavljević et al., IEDM 2021, pp. 721-725.
[7] C.-H. Chang et al., IEDM 2022, pp. 623-626.
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 (a) Target (b) This work: (c) This work: (a) (b)
Bottom device Top device
M1

V0 M0
M0 Top
Bot. SD (c)
SD
Top NS
Bot. Top Bot.
dev. dev. NS Gate Gate
Fig. 1. Schematic representation of CFET structures with (a) both bottom and top
devices contacted, (b) bottom device contacted, and (c) top device contacted. Fig. 2. Monolithic CFET process flows for bottom- and top-
Source-drain (SD) epitaxy vertical patterning is required 2 for (a) and 1 for (b,c). device fabrication on separate wafers (bulk Si).
(a) (b) (c) (a) (b) (c)

ISO etchback
GSP

a-Si
a-Si
a-Si gates CSP

Si:P SD
Si SiN
48nm

30nm
30nm

SiGe
SiGe liner
sacr.

Si:B SD
Si
30nm

75nm

ISO
SiGe

ISO
SiGe/Si fin STI ISO ISO
Fig. 3. HAADF- Fig. 4. HAADF-STEM images after (a) SD recess Fig. 5. HAADF-STEM images after (a) SiN liner deposition, (b)
STEM image after 1, (b) SiN cover spacer (CSP) formation and SD isolation (ISO) etchback including removal of the SiN liner, and (c)
gate patterning recess 2, and (c) bottom Si SD epi + B HDD I/I. top-device in-situ doped Si:P SD epitaxy for NMOS.
(a) 18nm (b) 21nm (a) Bottom (b)
Top Top Bottom
M0

48nm 48nm 10-4 10-4

pFET nFET pFET nFET
60nm

Gate M0 Gate 10-5 10-5

IS (A/mm)
IS (A/mm)

18nm Floating
Si:P
Si:P
Si:P

Channel Channel
c

CSP
73 m

V/de

c
10-6 10-6

V/de
Ti/TiN LG,PHYS=27nm
V/de

70 m

74 m
Gate Gate

74 m
LG,PHYS=27nm 6.5nm 10-7 30nm 10-7
ISO
ISO

ISO

48nm CPP
c

V/d
Si:B

Si:B
Si:B

Channel Channel 10-8 |VD,LIN|=0.05V 10-8 |VD,LIN|=0.05V

ec
pFET
Gate |VD,SAT|= 0.7V |VD,SAT|= 0.7V
Gate 48nm CPP
10-9 10-9
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8
ABF-STEM HfO2 TEM HfO2 VGS (V) VGS (V)
Fig. 6. End-of-process cross sectional images for (a) Fig. 7. IS-VGS for (a) top nFET and bottom pFET, and (b) for bottom nFET and top
bottom pFET and (b) top nFET (LG,PHYS=27nm). pFET (all from separate wafers). Inset: TEM across nanosheets inside metal gate.
70
ION,LIN @ VT,LIN+0.5V(mA/mm)

Short (a) Bottom nFET LG,TOP=17nm 4.5 Si SD with

1000
60 48nm CGP
(b)
B HDD I/I
RON,LIN (kW.mm)

VD,LIN=0.05V 4.0
M0-Gate shorts

800
IS,SAT (mA/mm)

50
In-situ
SiGe:B SD

600 40 3.5 doped

30 Si:P SD
400 Bottom nFET
48nm CGP 20 1.0
200 LG,PHYS=25nm VD,LIN=0.05V
VD=0.7V 10 0.5 48nm CGP
0
High resistance
0 LG,PHYS=25nm Fig. 10. Thick SiGe complicates (1)
0.4 0.6 0.8 1.0 1.2 14 16 18 20 22 24 0.0 uniform cavity etch and (2) inner
VGS (V) Bottom-device M0 top CD (nm) Bottom nFET Bottom pFET
spacer dielectric fill and etchback.
Fig. 8. (a) IS-VGS for bottom nFETs with varying M0 CDs, and (b) Fig. 9. High RON for bottom pFET
ION,LIN versus M0 top CD for bottom nFETs. attributed to Si:B iso SiGe:B SD. a-Si SiN
Si channel
SiGe1
SiN MDI
N-P space

SiGe1
66nm

SiN MDI
SiGe1
SiN MDI
SiGe1
Si channel
SiGe1
TEM
Fig. 11. Inner spacer (ISP) formation for a CFET stack with Fig. 12. Schematic view across sheets Fig. 13. CFET stack with segmented
equal SiGe1 thicknesses, enabled by middle dielectric inside RMG trench illustrating multi-VT MDI and 66nm N-P space to create
isolation (MDI) formed by replacing SiGe2 with SiN. patterning (a) w/o and (b) w/ MDI. margin for dual SD contacts.

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