IEEE 2015 International 3D Systems Integration Conference

Advanced 2.5D/3D Hetero-Integration Technologies

at GINTI, Tohoku University

K.W. Lee, J.C. Bea, M. Koyanagi T. Fukushima, T. Tanaka

Global Integration Initiative (GINTI) Global Integration Initiative (GINTI)
New Industry Creation Hatchery Center (NICHe) Dept. of Biomedical Engineering
Tohoku University Tohoku University
Sendai, 980-8579, Japan Sendai, 980-8579, Japan
kriss@bmi.niche.tohoku.ac.jp

Abstract— The Global Integration Initiative (GINTI) is 8/12- 2.5D/3D integration technologies into electronic industries to
inch R&D foundry fab for the research and development of new accelerate the commercialization of innovative 3D technologies
2.5D/3D integration technologies and creative applications. and applications into real, manufacturing-ready technology
GINTI offers a broad range of services to meet the mounting solutions.
R&D needs of the semiconductor industry and related industries.
GINTI provides a cost-competitive process development
infrastructure in a manufacturing-like fab environment and a
low-cost, short TAT prototyping of proof of concepts using
commercial/customized 2D chip/wafer, and a base-line process
set-up for the pilot production of creative 3D systems. GINTI
aims to provide Tohoku University`s advanced 2.5D/3D
integration technologies into electronic industries to accelerate
the commercialization of innovative 3D technologies and
applications into real, manufacturing-ready technology solutions
with FAST. This paper introduces advanced 2.5D/3D hetero-
integration technologies developed by GINTI/Tohoku University.

Keywords—3-D heterogeneous integration, chip self-assembly,

backside TSV

I. 8/12-INCH 2.5D/3D INTEGRATION PROCESS FACILITIES

The Global Integration Initiative (GINTI) is 8/12-inch
R&D foundry fab for the research and development of new
2.5D/3D integration technologies and creative applications.
GINTI provides a cost-competitive process development
infrastructure in a manufacturing-like fab environment and a
low cost, short TAT prototyping of proof of concepts using
commercial/customized 2D chip/wafer, and a base-line process
set-up for the pilot production of creative 2.5D/3D systems. Fig.
1 shows 8/12-inch 2.5D/3D integration process facilities at
GINTI. GINTI provide one-stop solution from concept and
design to fabrication and testing. Detail state-of-the
technologies are design, layout and mask making to wafer
thinning, forming of TSV on chip/wafer (front side/backside
TSV), redistribution routing, both side micro-bump formation,
chip/wafer stacking, failure analysis, and reliability testing.
Especially, GINTI can provide 3D stacking LSIs prototype
manufacturing service using commercial/customized 2D chips
by die-level 3D hetero-integration, backside TSV formation Fig.1. 8/12-inch 2.5D/3D integration process facilities at GINTI
and various stacking (CtC CtW, WtW, and self-assembly)
technologies. GINTI support small-volume, special customized In next chapters, we introduce a couple of advanced
3D productions by base-line process set-up for the pilot 2.5D/3D hetero-integration technologies developed by
production to facilitate customer`s product development. GINTI/Tohoku University.
GINTI aims to provide Tohoku University`s advanced

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II. ADVANCED 2.5D/3D HETEROGENEOUS INTEGRATION
TECHNOLOGIES
(A) TSV (through-silicon via) formation technology
TSV formation is a key technology for the 3D-IC
fabrication, because TSV is an important factor to determine
3D-IC performance. We have developed a couple of TSV
formation technologies as shown in Fig. 2 ; poly-Si TSV with
2.5μm dia. for via first approach [1], CVD-W TSV with 0.7μm
dia. [2], electroplated Cu TSV (front via) with 3μm dia. for via
middle approach, and electroplated Cu TSV (back via) with
7μm dia. for via last approach [3], respectively.
Fig.2. Various TSV formation technologies with applications
GINTI mainly focus on via-last backside TSV approach,
because it has attracted attention as a better solution to
heterogeneously integrate different function, size, and material
devices, with high flexibility to apply commercial chip/wafer,
better reliability, and lower cost process [4-5]. Fig. 3 shows the
configuration of via-last backside TSV fabrication process.
Fig.3. Configuration of via-last backside TSV fabrication process
Incoming LSI device wafer with metal bumps is temporarily
bonded onto a support wafer. Then the Si substrate is thinned
to target thickness from the backside by grinding and CMP
processes. After via patterning on the grinded surface, the deep
Si trench is formed from the backside by reactive-ion-etching
(RIE) process until to expose the first level metallization layer
(M1). The oxide liner is deposited into via holes and the
bottom oxide liner in via hole is selectively etched by dry
FS2.2
etching to expose again M1 layer. Next, the deep trench is
filled with Cu by electroplating after the formation of barrier
and sees metal layers. Re-distribution layer (RDL) is formed on
the backside. Then metal bumps are formed on the RDL by
electroplating process. Finally, the support wafer is de-bonded
from the thinned LSI wafer.
(B) Self-assembly and electrostactic (SAE) bonding
technologies
A new 3D hetero integration technology using self-
assembly and electrostactic (SAE) bonding has been developed,
which can provide high production throughput. This
technology has been named reconfigured wafer-to-wafer
(RW2W) 3D integration technology [6-9]. Fig. 3 shows the
configuration of hybrid 3D integration technology using SAE
bonding techniques.
Fig.3. Configuration of hybrid 3D integration technology using self-assembly
and electrostatic (SAE) temporary bonding techniques.
More than several hundred known good dies (KGDs),
which are sorted from several device wafers, are temporary
bonded onto an electrostatic carrier (e-carrier) wafer by
electrostatic force with a high alignment accuracy of 1μm by
self-assembly methods. The surface tension of a liquid is
utilized in self-assembly to simultaneously align many dies in
parallel. Hydrophilic areas and hydrophobic areas are formed
on the surface of SAE carrier wafer. Many liquid droplets are
simultaneously supplied on the hydrophilic areas (bonding
areas), and then many KDGs are simultaneously supplied onto
the hydrophilic areas in the self-assembly process with high
alignment accuracy. After chip self-assembly and evacuation of
liquid droplets, the electrostatic force is generated by applying
a high voltage of 200 V to the electrodes embedded in the e-
carrier for temporary bonding of many chips. This SAE carrier
wafer, which consists of many KGDs, is called a reconfigured
wafer, and it exhibits very high production yield because of the
KGDs. Another reconfigured wafer is fabricated by
simultaneously by bonding many KGDs onto another carrier
wafer. Many KDGs are de-bonded from the SAE carrier by
applying a voltage with opposite polarity then transferred to a
target interposer/LSI wafers. This RW2W integration
technology can give high production throughput and low cost.
The temporary bonding and de-bonding processes are very
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important steps in RW2W integration technology. Fig. 4 shows

the photograph of simultaneously hetero-integrated chips with
different sizes on 8-inch interposer by SAE bonding
technology

Fig.6. Photograph of microelectromechanical system (MEMS) chip stacked on

CMOS chip by chip self-assembly and sidewall interconnection technologies

Fig. 6 shows a 3D stacked MEMS-LSI module where a CMOS

chip is stacked on an LSI wafer and a pressure sensor MEMS
chip is integrated onto the CMOS chip by chip self-assembly
technique. Fig.7 shows the magnified optical image of the
Fig.4. The photograph of simultaneously hetero-integrated chips with different heterogeneous MEMS–LSI multi-chip module where LSIs,
sizes on 8-inch interposer by SAE bonding technology passives and MEMS chips were integrated onto the surface of
the electrical interposer. LSIs and passives chips with 100µm
(C) Opto-electronics 3D hetero-integration technology thickness were connected by Cu-sidewall interconnection and a
MEMS chip with 350µm thickness was connected by the
A very attractive feature in 3D LSI is the capability of cavity-chip interconnection.
heterogeneous integration. Especially, heterogeneous
integration involving CMOS, MEMS, and photonic circuits has
attracted much attention owing to its multi functionality, high-
speed communication, and low power consumption. Such
heterogeneous 3D integration provides the possibility to
achieve new functional LSIs [10]. Typical examples of 3D
hetero-integration are the 3D hetero-integrated opto-electronic
module using 2.5D Si interposer with embedded sensor chips,
TSVs and micro-fluidic channels and organic substrate with
optical waveguide (Fig. 5) [11-12], the integration of MEMS
chip on CMOS chip by chip self-assembly and sidewall
interconnection technologies (Fig. 6) [13-14], and the
integration of an optoelectronic chip on a CMOS chip (Fig. 8)
[15].
Fig.7. The optical image of the heterogeneous MEMS–LSI multi-chip module
that was integrated onto the surface of the electrical interposer

Fig.5. Concept of 3D hetero-integrated opto-electronic module using 2.5D Si

interposer with embedded sensor chips, TSVs and micro-fluidic channels and
organic substrate with optical waveguide

Fig. 5 shows a 3D hetero-integrated opto-electronic module

using 2.5D Si interposer. Image sensor stacked on ADC chip is
for high-performance image-processing. An accelerometer
MEMS sensor, optical sensor, and radio-frequency integrated
circuits (RF ICs) are for high-sensitive sensing of the high
moving speed. 3D memory and 3D processor are for high-
performance data computing. Optical interconnection
facilitates high-speed data transmission networking. Micro-
fluidic channels assist in heat sinking from high-power LSIs.
Fig.8. Configuration of 3D optoelectronic LSI, where optoelectronic chip
stacked on CMOS chip (left upper figure). Cross-sectional view of through-Si
photonic via (TSPV) and through-Si via (TSV) (left lower figure), conceptual
structure (right upper figure) and surface views (right middle figure) of optical
grating coupler with a mirror, and 2D map of optical energy propagated from
TSPV to optical grating coupler where the red color indicates higher energy
(simulation) (right lower figure)

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Fig. 8 show a 3-D optoelectronic LSI, where an optoelectronic

integrated circuit chip with Si photonic devices is stacked on
CMOS chips. The respective chip layers are vertically
connected by both optical interconnections (TSPV, through-Si
photonic vias) and electrical interconnections (TSV, through-Si
vias). A Si optical waveguide with an oxide cladding layer is
used as a TSPV. In order to fabricate TSV and TSPV, a
cylindrical deep trench and a ring-type deep trench are
simultaneously formed by RIE. Then The Cu-TSV is formed
by the process described earlier, whereas the Si-TSPV is
formed by filling the ring-type deep trench with silicon oxide
or organic material. Thus, the Si-TSPV and Cu-TSV are
simultaneously fabricated. We confirmed that an optical signal
is effectively guided by the TSPV. An optical grating coupler
with a mirror was used to change the propagation direction of Fig.10. Photograph of fabricated 3D stacked image sensor chip with 3 tires
the optical signal. A high coupling efficiency of more than (CIS, CDS, ADC layers)
80% in this optical grating coupler was obtained, which is
sufficient for high speed optical data transfer. Continuous
propagation of the optical signal from the vertical TSPV to the Fig. 11 show SEM cross-section (a) and X-Ray CT scan image
horizontal Si waveguide through the optical grating coupler has (b) of fabricated 3D stacked image sensor with 4-layers. A
been confirmed. number of Cu TSVs with 5μm dia. and 50μm length, RDLs,
metal micro-bumps, and BEOL interconnects are clearly seen
[18].
(D) Die-level 3D hetero-integration technology
To realize new architecture 3D hetero-integrated systems
with low-cost, high flexibility, and rapid prototyping time, we
have developed a die-level 3D integration technology. Fig. 9
shows a novel die-level 3D integration technology for high
performance, multi-functionality hetero-integrated systems.
The commercially available 2D chips with different functions
and sizes such as those of sensor, logic, and memories with
different functions and sizes, which were fabricated by
different technologies, are processed to form TSVs and metal
micro-bumps and integrated to form a 3D stacked chip in die-
level. Fig.11. SEM cross-section (a) and X-Ray CT scan image (b) of fabricated 3D
stacked image sensor with 4-layers

CONCLUSIONS
GINTI support electronic industry partners to accelerate the
commercialization of innovative 3D technologies and
applications into real, manufacturing-ready technology
solutions by providing Tohoku University`s advanced 2.5D/3D
hetero-integration technologies such as novel RW2W
integration using SAE bonding technique, 2.5D interposer,
backside TSV, die-level 3D hetero-integration, and opto-
electronics 3D hetero-integration using cost-competitive
process infrastructure in a manufacturing-like fab environment.
Fig.9. Schematic of die-level 3-D integration technology for hetero-integrated
systems using different functional chips
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