In the name of ALLAH, the most Gracious, the Most Merciful

NSE – 847
Essentials of NEMS/MEMS
Course Instructor: Dr. Amna Safdar

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 What are we up in coming Lectures?

Special (Advanced) Topics: LIGA, HEXSIL, DRIE

(including Bosch etching),
MicroFabrication
• MEMS-CMOS Processing
• MEMS-CMOS Integration Techniques
• Patented Industry Processes e.g., MUMPS, iMEMS,
SUMMiT, and ASIM-X.
• MEMS Structures
• Cantilever: Singly-Clamped Beams and Doubly-
Clamped Beams, Plates
The substrate and adding material to it.

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 Process flow part 2

Develop a basic-level process flow for creating a simple MEMS device

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 MEMS pressure detector
Consists of two components:
• Fixed electrode
• Flexible diaphragm forming a moving
electrode
• Sealed vacuum cavity between the two
electrodes

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 State and explain the principles involved in attaining good mask
alignment

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 Identify and explain the various issues involved with designing good process
flows

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 Other issues in process flow
Other issues in designing good process flows
System partitioning:
• Whether or not to integrate the MEMS device and any necessary electronics on the same chip
• Integration limits MEMS process steps due to temperature, materials, etc.

Process partitioning:
• Material used in one process bond with and/or affect the properties of materials in another processes?
• If so, the order of the process steps may matter significantly.

Backside processing
• Makes many fabrication processes easier, but alignment is more difficult
• Also must take into account which steps affect both sides of wafer and which ones affect only one side

Thermal constraints
• E.g., photoresist cannot withstand high temperatures,
• High temperatures further drive-in dopants
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 Other issues in process flow
Other issues in designing good process flows
Device geometry
• Hard to visualize the 2-D and 3-D aspects of devices  Solid-modeling, CAD software
developed specifically for MEMS
• Combination of conformal deposited layers with directional etching can result in stringers

stringer

• Can use planarization to avoid stringers,

depth of focus problems, and other issues
arising from large changes in topography An example of a “floating stringer” (Courtesy of
Sandia National Laboratory

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 Other issues in process flow

Other issues in designing good process flows

Mechanical stability:
Fabrication can result in the formation of different stresses
C in structural layers, causing them
to bend or break
Coming up next!
Process accuracy:
• Expansion or shrinkage of photoresist
• Variations in the thickness of layers Design rules
• Presence of photoresist in structural layers
• Mask misalignment between layers

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 Other issues in process flow
C

A MEMS wheel and hub

If using a wet etchant in step 7

isotropic
C or anisotropic

Undercutting

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 MOSFETs created using different process flows:

(a) (b)
h
 MOSFETs created using different process flows:

(a) In these devices the n+ regions were diffused first, after

which a metal was deposited and patterned for the gate.
An overlap between the gate and the n+ regions was
h purposely built into the process flow in order to
minimize the likelihood of the type of photolithographic
misalaignment discussed in the last section. This overlap
causes an unwanted increase in device capacitance, one
which reduces transistor switching speed.

An obvious tradeoff between

manufacturability and device
performance.
 MOSFETs created using different process flows:

(b) a polysilicon gate electrode is deposited and patterned

h The implantation is followed by a high temperature
Rather than a tradeoff between
performance and manufacturability
we have a “win-win” situation. It has
changed the manufacture of integrated
circuits significantly.
first, and then the doped regions are created using ion
implantation using the polysilicon electrode as a mask.
drive-in. Polysilicon is used for the device in Fig. 4.20 (b)
instead of a metal since metals can’t handle the high
temperature drive-in step. The smaller electrical
conductivity of polysilicon compared to metals causes a
decrease in device performance. However, for the device
in Fig. 4.20 (b) there is virtually no overlap between the
electrode and the doped regions. (This is why it has
become known as a self-aligned gate.) This results in a
much smaller capacitance, which leads to much faster
transistor switching speeds. The corresponding increase
in device performance dwarfs any drawbacks of the
polysilicon electrode material, and the process flow is
somewhat simpler too.
 A win-win process flow
The self-aligned gate transistor
use poly as electrode and as
metal poly Si mask for doping
electrode electrode

n+ doping
p type virtually no gap increases in
wafer switching speed significantly
overlap causes unwanted
increase in capacitance,
slower switching speed

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