In the name of ALLAH, the most Gracious, the Most Merciful

NSE – 847
Essentials of NEMS/MEMS
Course Instructor: Dr. Amna Safdar

Lecture#22&23-02 29/04/2020 1
 What are we up in coming Lectures?

Special (Advanced) Topics: LIGA, HEXSIL, DRIE

(including Bosch etching),
MicroFabrication
• MEMS-CMOS Processing
• MEMS-CMOS Integration Techniques
• Patented Industry Processes e.g., MUMPS, iMEMS,
SUMMiT, and ASIM-X.
• MEMS Structures
• Cantilever: Singly-Clamped Beams and Doubly-
Clamped Beams, Plates

Lecture#22&23-02 29/04/2020 2
 A win-win process flow
The self-aligned gate transistor
use poly as electrode and as
metal poly Si mask for doping
electrode electrode

n+ doping
p type virtually no gap increases in
wafer switching speed significantly
overlap causes unwanted
increase in capacitance,
slower switching speed

Lecture#22&23-02 29/04/2020 3
MEMS: Fabrication

MultiUser MEMS Process

(MUMPS)

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  Pressure sensor: full fabrication animation
 MUMPS
 Details of PolyMUMPs process
 Design rules
 Ledit software to develop your device by polyMUMPs process
 Examples of the devices made by polyMUMPS

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 Fabrication steps for a piezoresistive gauge or
differential, bulk micromachined pressure sensor

Metal

Insulator

n-type epitaxial layer

p-type diffusion
p-type substrate

Silicon nitride
Glass

1: Deposit Insulator 2: Diffuse piezoresistors

3: Deposit and pattern material
4: Electrochemical etch of backside cavity
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5: Anodic Glass bonding
 Silicon-Silicon Fusion Bonding
Two silicon wafer with/without SiO2 can be bonded

• Advantages:
No thermal mismatch
• Needs contamination free, smooth, and flat wafers (e.g. surface
roughness ~5°A)
• Process Flow
– Clean wafers
– Make the surfaces hydrophilic (e.g. dip in Nitric Acid)
– Rinse-Dry
– Place the wafers together apply pressure
– H2 or N2 anneal at 800-1000°C

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 Electrostatic Bonding
Glass-Silicon Bonding

• Field assisted anodic

bonding
• Glass & metal bonding
to silicon
• Glasses

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 MUMPs Process

 Multi User MEMS process

 Company MEMSCAP: offers PolyMUMPS, MetalMUMPS, and
SOIMUMPS
 Developed at BSAC (Berkeley Sensors and Actuators Center) in late
80’s

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 We will study PolyMUMPs a 3 level polysilicon
micromachining process

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 Cleaned Silicon Wafer

Clean Silicon Wafer

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 Doping of Phosphorous on
silicon wafer

Using Standard diffusion furnace

using POCL3 as Dopant source
Clean Silicon Wafer

phosphorus oxychloride

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 Deposition of Silicon Nitride
layer of thickness 600nm

Using Standard LPCVD (Low

Pressure Chemical Vapor
Clean Silicon Wafer deposition)
Silicon Nitride layer
Acts as insulation layer

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 Deposition of polysilicon
film
Thickness 500nm

Using Standard LPCVD (Low

Pressure Chemical Vapor
Clean Silicon Wafer deposition)
Silicon Nitride layer
Poly0 layer

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 Deposition of
Photo resist
Thickness 500nm

Spin Coating method

Clean Silicon Wafer

Silicon Nitride layer
Poly0 layer
Photo resist layer

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 Mask

Masking process
Thickness 500nm

UV Source and Mask

Clean Silicon Wafer

Silicon Nitride layer
Poly0 layer
Photoresist layer

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 Mask

Masking and Exposure with

UV source followed with
development of photoresist
Thickness 500nm

Clean Silicon Wafer

Silicon Nitride layer
Poly0 layer
Photoresist layer

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 Etching of poly0 layer
Thickness 500nm

Reactive Ion Etching (RIE)

After etching photoresist is stripped
Clean Silicon Wafer in solvent bath
Silicon Nitride layer
Poly0 layer

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 Deposition of PSG
(Phosphosilicate Glass)
layer
Thickness 2 μm

LPCVD process is used to deposit

PSG (1st Oxide Layer) layer this is
Clean Silicon Wafer first sacrificial layer
Silicon Nitride layer
Poly0 layer
PSG layer (1st Oxide)

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 Lithographic patterning of
DIMPLE
Depth 750 nm

Dimples

Wafer is coated with photoresist

and second level (DIMPLE) is
Clean Silicon Wafer lithographically patterned. Dimples
Silicon Nitride layer are reactive ion etched. After
Poly0 layer etching photoresist is stripped
PSG layer (1st Oxide)

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 Lithographic patterning of
ANCHOR1

Dimples Anchor 1 Etch

Wafer is coated with photoresist

and second level (ANCHOR1) is
Clean Silicon Wafer lithographically patterned. Anchor1
Silicon Nitride layer is reactive ion etched. After etching
Poly0 layer photoresist is stripped
PSG layer (1st Oxide)

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 Deposition of POLY1 Layer
along with PSG hard mask

PSG Mask

Clean Silicon Wafer

Silicon Nitride layer
Poly0 layer
PSG layer (1st Oxide)
Poly1 Layer

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 Lithographic patterning of
POLY1 layer

2nd Oxide Layer

Wafers are recoated with

photoresist and third level (Poly1)
Clean Silicon Wafer is lithographically patterned. PSG
Silicon Nitride layer is first etched to create a hard
Poly0 layer mask and then poly1 is etched by
PSG layer (1st Oxide) RIE after etching photoresist and
Poly1 Layer
PSG mask are removed
2nd Oxide layer

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 Deposition of 2nd oxide
layer

2nd Oxide Layer

Second oxide layer 0.75 μm of

PSG is deposited on water. This
Clean Silicon Wafer layer is patterned twice to allow
Silicon Nitride layer contact to both poly1 and substrate
Poly0 layer layers.
PSG layer (1st Oxide)
Poly1 Layer
2nd Oxide layer

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 Lithographic patterning of
P1_P2_Via Etch

P1-P2 Via Etch

P1-P2 Via Etch

Wafer is coated with photoresist

and fifth level (POLY1_POL2_VIA)
Clean Silicon Wafer is lithographically patterned.
Silicon Nitride layer Unwanted second oxide is etched
Poly0 layer in RIE, stopping on POLY1 and
PSG layer (1st Oxide) photoresist is stripped
Poly1 Layer
2nd Oxide layer

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 Lithographic patterning of
using ANCHOR2 Etch

Anchor 2 Etch

Wafer is coated with photoresist

and sixth level (ANCHOR2) is
Clean Silicon Wafer lithographically patterned. Second
Silicon Nitride layer and first oxide are etched in RIE,
Poly0 layer stopping on either POLY0 or
PSG layer (1st Oxide) Nitride and photoresist is stripped
Poly1 Layer
2nd Oxide layer

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 Deposition of polysilicon
and PSG hard mask
dopping process

PSG Mask

A 1.5 μm undoped polysilicon layer

is deposited followed by 200 nm
Clean Silicon Wafer PSG hard mask layer. The wafers
Silicon Nitride layer are annealed at 10500C for one hr
Poly0 layer and dope the polysilicon and
PSG layer (1st Oxide) reduce residual stress
Poly1 Layer
2nd Oxide layer
Poly2 Layer
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 Lithographic patterning of
POLY2

Wafer is coated with photoresist

and seventh level (POLY2) is
Clean Silicon Wafer lithographically patterned. PSG
Silicon Nitride layer hard mask and Poly2 layers are
Poly0 layer etched in RIE,
PSG layer (1st Oxide)
Poly1 Layer
2nd Oxide layer
Poly2 Layer
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 Deposition of Metal Layer

Metal Layer

Wafer is coated with photoresist

and eighth level (METAL) is
Clean Silicon Wafer Metal Layer lithographically patterned. Metal
Silicon Nitride layer (gold with this adhesion layer) is
Poly0 layer deposited by lift off patterning.
PSG layer (1st Oxide)
Poly1 Layer
2nd Oxide layer
Poly2 Layer
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 Releasing a structure

Metal Layer

The structure are released by

immersing the chip in 49 % HF
Clean Silicon Wafer Metal Layer solution. POLY1 “rotor and POLY2
Silicon Nitride layer “hub” are relesed.
Poly0 layer
PSG layer (1st Oxide)
Poly1 Layer
2nd Oxide layer
Poly2 Layer
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 PolyMUMPs Process Flow (1)
• n+ doping
• Silicon nitride (Nitride) deposition (600 nm)
• 500 nm polysilicon (Poly 0) deposition
• Photoresist coating
• Photolithography using first level mask (POLY0)
• RIE Poly0
• Photoresist stripping (in a solvent)

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 PolyMUMPs Process Flow (2)
• 2.0 µm LPCVD PSG deposition (the first
sacrificial layer)
• Second mask (DIMPLE) patterned
• The dimples, 750 nm deep, are etched
(RIE) into the first oxide layer.
• Third mask (ANCHOR1) patterned

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 PolyMUMPs Process Flow (3)
• A blanket 2.0 µm layer of undoped polysilicon is
deposited by LPCVD followed by the deposition of 200
nm PSG and a 1050° C/1 hour anneal.

The anneal serves to both dope the polysilicon and

reduce its residual stress.

• The fourth mask (POLY1) is lithographically patterned.

The PSG is first etched to create a hard mask and then
Poly 1 is etched by RIE.
• After the etch is completed, the photoresist and PSG
hard mask are removed.

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 PolyMUMPs Process Flow (4)

• The Second Oxide layer, 0.75 µm of PSG, is deposited on the

wafer.
This layer is patterned twice to allow contact to both Poly 1 and
substrate layers.
• The fifth mask (POLY1_POLY2_VIA) is
lithographically patterned.
• The unwanted Second Oxide is
RIE etched, stopping on Poly 1,
and the photoresist is stripped.

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 PolyMUMPs Process Flow (5)
• The sixth mask (ANCHOR2) is
lithographically patterned.
• Second and First Oxides are RIE
etched, stopping on either Nitride or
Poly 0, and photoresist is stripped.
• The ANCHOR2 level provides
openings for Poly 2 to contact with
Nitride or Poly 0.
• A 1.5 µm un-doped polysilicon
layer is deposited followed by a
200 nm PSG hardmask layer. The
wafers are annealed at 1050°C for
one hour to dope the polysilicon
and reduce residual stress.

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PolyMUMPs Process Flow (6)
• The seventh mask (POLY2) is
lithographically patterned.
• The PSG hard mask and Poly 2 layers
are RIE etched and the photoresist and
hard mask are removed.
• All mechanical structures have now been
fabricated. The remaining steps are to
deposit the metal layer and remove the
sacrificial oxides
• The eighth mask (METAL) is patterned. The
metal (gold with a thin adhesion layer) is
deposited by lift-off patterning.
• The photoresist and unwanted metal (atop
the hotoresist) are then removed in a solvent
bath.
• The process is now complete and the wafers
can be coated with a protective layer of
photoresist and diced. The chips are sorted
and shipped.
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 PolyMUMPs Process Flow (7)
•The structures are released by immersing the chips in a 49%
HF solution.
•The Poly 1 ``rotor'' can be seen around the fixed Poly 2 hub.
•The stacks of Poly 1, Poly 2 and Metal on the sides represent
the stators used to drive the motor electrostatically.

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 Example Devices by PolyMUMPs

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 Summary: MUMPs
MUMPs® (Multi-User MEMS Processes) consists of
standardized building blocks for MEMS processing and
MEMS components
• MUMPs® is a well-established, commercial program
that provides customers with cost-effective access to
MEMS prototyping and a seamless transition into
volume manufacturing.
• There are now three flavors of MUMPs®:
Features:
PolyMUMPs, SOIMUMPs, and MetalMUMPs. ‰ •Structural material: Polysilicon
MUMPs® is part of MEMSCAP’s complete •Sacrificial layer: Deposited oxide
manufacturing offer, ranging from prototyping (PSG) •Electrical isolation: silicon
(MUMPs) to mass production.
nitride
•3 polysilicon layers

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 Mask Conventions
Mnemonic Level Name Field Type Purpose
POLY0 light pattern ground plane

ANCHOR1 dark open holes for POLY1 to nitride or POLY0 connection

DIMPLE dark create dimples/bushings for POLY1

POLY1 light pattern POLY1

POLY1_POLY2_VIA dark open holes for POLY1 to POLY2 connection

ANCHOR2 dark open holes for POLY2 to nitride or POLY0 connection

POLY2 light pattern POLY2

METAL light pattern METAL

HOLE0 dark provide holes for POLY0

HOLE1 dark provide release holes for POLY1

HOLE2 dark provide release holes for POLY2

HOLEM dark provide release holes in METAL

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 MUMPs Process

 Software Ledit for developing your own designs: Demo

 Some designs in the software
 How they look like after fabrication!!

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 Design I

Poly0
Anchor1
Poly1
Poly1-Poly2 via
Poly2
Metal

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 MUMPs Designs and
Products
 Comb actuators by
PolyMUMPS

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 Pressure sensor with diffused piezoresistive sense elements

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 HEXSIL Process

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 Fabrication sequence for a conventional hexsil process.

(a) Wafer is patterned and etched with a network of

deep trenches.

(b) A sacrificial SiO2 layer is deposited.

(c) A structural poly-Si layer is deposited.
(d) The poly-Si "face sheet" is patterned and etched.
(e) Gold bumps are electroplated onto the poly-Si
structure.
(f) The structure is released in HF and transferred to
a target substrate.

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