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PN JUNCTION
FABRICATION

CO-ORDINATOR
Dr TARUN CHAUDHARY

Presented by
BIYYAPU SAI VAMSI
20204005.
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FABRICATION STEPS FOLLOWED

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(a) First mask exposure (b) Post-exposure and development of photoresist

(c) After SiO2 etch (d) After implantation/diffusion of acceptor dopant.
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(e) Exposure of contact opening mask, (f) after resist development and etching of contact openings,
(g) exposure of metal mask, and (h) After etching of aluminum and resist removal.
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Top view of an integrated pn diode.

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BJT FABRICATION
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The Physical Structure (NMOS)

Gate oxide
Polysilicon Gate
Al Al
SiO2 SiO2 SiO2
Field Oxide
S D
Field Oxide
n+ channel n+
L
P Substrate

contact Metal

(G)
L
(S) n+ n+ (D)
W

Poly
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3D Perspective
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Fabrication Process

•Crystal Growth

•Doping / Diffusion

•Deposition

•Patterning

•Lithography

•Oxidation

•Ion Implementation
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Fabrication- CMOS Process

Starting Material Preparation

1. Produce Metallurgical Grade Silicon (MGS)

SiO2 (sand) + C in Arc Furnace
Si- liquid 98% pure

2. Produce Electronic Grade Silicon (EGS)

HCl + Si (MGS)
Successive purification by distillation
Chemical Vapor Deposition (CVD)
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Fabrication: Crystal Growth

Czochralski Method
 Basic idea: dip seed crystal into
liquid pool
 Slowly pull out at a rate of

0.5mm/min
 controlled amount of

impurities added to melt

 Speed of rotation and pulling

rate determine diameter of the

ingot
 Ingot- 1to 2 meter long
 Diameter: 4”, 6”, 8”
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Fabrication: Wafering
 Finish ingot to precise diameter
 Mill “ flats”
 Cut wafers by diamond saw: Typical
thickness 0.5mm
 Polish to give optically flat surface
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FLATS :
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Contamination
• Human hair at the
same scale as the
integrated circuit with
10 m feature size
• Today’s feature size
100 nm - 100 times
smaller!
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Clean Room Specifications

Table 2.1 Clean Room Ratings by Class of Filtration

Class Number of 0.5-m Number of 5-m

particles per ft3 (m3) particles per ft3 (m3)

10,000 10000 (350,000) 65 (23,000)

1,000 1000 (35,000) 6.5 (2,300)
100 100 (3,500) 0.65 (230)
10 10 (350) 0.065 (23)
1 1 (35)* 0.0065 (2.3)

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*It is very difficult to measure particulate counts below 10/ft
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Wafer Cleaning
• Wafers must be cleaned of chemical and particulate contamination
before photo processing
• Example of “RCA” cleaning procedure in table below
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Fabrication: Oxidation
Silicon Dioxide has several uses:
- mask against implant or
diffusion
- device isolation
- gate oxide Quartz Tube
-isolation between
-layers O2 or Water
Pump Wafers Vapor

Quartz Carrier
 SiO2 could be thermally
generated or through CVD
Oxidation consumes silicon Resistance Heater
Wet or dry oxidation
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Fabrication: Diffusion
 Simultaneous creation of p-n junction
over the entire surface of wafer
 Doesn’t offer precise control
 Good for heavy doping, deep junctions
 Two steps:
Temp: 1000

Dopant Gas wafers

Pre-deposition
Dopant mixed with inert gas
introduced in to a furnace at 1000 oC. Resistance Heater
Atoms diffuse in a thin layer of Si
surface
Drive-in
Wafers heated without dopant
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Fabrication: Ion Implantation

 Precise control of dopant
 Good for shallow junctions and threshold adjust
 Dopant gas ionized and accelerated
 Ions strike silicon surface at high speed
 Depth of lodging is determined by accelerating field
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Fabrication: Deposition
 Used to form thin film of Polysilicon,
Silicon dioxide, Silicon Nitride, Al.

 Applications: Polysilicon, interlayer

oxide, LOCOS, metal. Loader

0.1 -1 Torr
Pump

Reactant

 Common technique: Low Pressure

Chemical Vapor Deposition (CVD).

 SiO2 and Polysilicon deposition at

300 to 1000 oC.
 Aluminum deposition at lower
temperature- different technique
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Fabrication: Metallization
 Standard material is Aluminum

 Low contact resistance to p-type and n-type

 When deposited on SiO2, Al2O3 is formed: good adhesive

 All wafer covered with Al

 Deposition techniques:
Vacuum Evaporation
Electron Beam Evaporation
RF Sputtering

 Other materials used in conjunction with or replacement to Al

In today’s technology are cupper and its alloys.
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Fabrication: Etching
Wet Etching
 Etchants: hydrofluoric acid (HF), mixture of nitric acid and HF
 Good selectivity
 Problem:
- under cut
- acid waste disposal

Plasma Reactive species

Dry Etching RF
 Physical bombardment with atoms or ions
 good for small geometries.
 Various types exists such as:
Planar Plasma Etching
Reactive Ion Etching
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Oxide Etching Profiles

(a) Isotropic etching - wet chemistry - mask undercutting
(b) Anisotropic etching - dry etching in plasma or
reactive ion etching system

Mask Undercut
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Fabrication: Lithography
Mask making
 Most critical part of lithography is conversion from layout to
master mask

 Masking plate has opaque geometrical shapes corresponding

to the area on the wafer surface where certain photochemical
reactions have to be prevented or taken place.

 Masks uses photographic emulsion or hard surface

 Two types: dark field or clear field

 Maskmaking: optical or e-beam

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Lithography: Mask making

Optical Mask Technique

1. Prepare Reticle
Use projection like system:
-Precise movable stage
-Aperture of precisely rectangular size and angular orientation
-Computer controlled UV light source directed to photographic plate
After flashing, plate is developed yielding reticle
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Fabrication: Lithography

Step & Repeat

Printing

Printing
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Lithography: Mask making

Electron Beam Technique

 Main problem with optical

technique: light diffraction

 System resembles a
scanning electron microscope +
beam blanking and computer
controlled deflection
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Minimum Feature Size

and Depth of Field


Minimum Feature Size F  0.5
NA


Depth of Field DF = 0.6
 
2
NA

Numerical Aperture NA  sin 

  wavelength of exposure source


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Phase Shifting Masks

Pattern transfer of two
closely spaced lines
(a) Conventional mask
technology - lines not
resolved
(b) Lines can be resolved
with phase-shift
technology
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Patterning/ Printing
 Process of transferring mask features to surface of the
silicon wafer.
 Optical or Electron-beam

 Photo-resist material (negative or positive):synthetic

rubber or polymer upon exposure to light becomes
insoluble ( negative ) or volatile (positive)

 Developer: typically organic solvent- e.g. Xylene

 A common step in many processes is the creation and

selective removal of Silicon Dioxide
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Patterning: P-well mask

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Patterning/ Printing

SiO2

substrate
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DIFFUSED Sb
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DIFFUSION
• As the given wafer is P type so we need to diffuse N type impurity into
the wafer to create P-N junction and we take Boron (P type) impurity
for diffusion.
• Material used for
• Antimony diffusion Sb3Cl5 (antimony penta chloride)
• Arsenic diffusion As2O3 (arsenic tri oxide)
• Phosphorus diffusion POCl3 (phosphorus oxi chloride)
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METALLIZATION

Metallization is the final step in the wafer processing sequence.

Metallization is the process by which the components of IC’s are
interconnected by aluminium conductor. This process produces a
thin-film metal layer that will serve as the required conductor
pattern for the interconnection of the various components on the
chip. Another use of metallization is to produce metalized areas
called bonding pads around the periphery of the chip to produce
metalized areas for the bonding of wire leads from the package
to the chip
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Fabrication Steps

Inspect, measure

Post bake
Etch

Develop, rinse, dry

Strip resist
Printer align expose
mask
Deposit or grow layer
Pre-bake

Apply PR
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Fabrication Steps
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3D Perspective
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The Physical Structure (NMOS)

Gate oxide
Polysilicon Gate
Al Al
SiO2 SiO2 SiO2
Field Oxide
S D
Field Oxide
n+ channel n+
L
P Substrate

contact Metal

(G)
L
(S) n+ n+ (D)
W

Poly