Integrated Circuit

(IC) Fabrication
 Introduction
 Integrated circuit: An integrated circuit or monolithic integrated
circuit (also referred to as an IC, a chip, or a microchip) is a set
of electronic circuits on one small flat piece (or "chip")
of semiconductor material that is normally silicon.

 The integration of large numbers of tiny MOS transistors into a small

chip results in circuits that are orders of magnitude smaller, faster,
and less expensive than those constructed of discrete electronic
components. 

 ICs are now used in virtually all electronic equipment and have
revolutionized the world of electronics. Computers, mobile phones,
and other digital home appliances are now inextricable parts of the
structure of modern societies, made possible by the small size and
low cost of ICs.

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IC fabrication
process

SAND  Step 1: Sand is taken as raw material. Available

in abundant and low cost.

INGOT  Step 2: Ingot is formed out of the polycrystalline

sand by the help of chemical reactions and
technique called Czochralski method.
WAFER

 Step 3: Ingot is sliced down to obtain single

DIES crystal wafer.

IC
 Step 4: Dies/chips are formed with the wafers.

 Step 5: Finally IC is fabricated on the dies.

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INGOT WAFER DIE

IC

Fig.1. Structure from INGOT to IC

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 The whole IC formation is done in 2 basic steps:
1. Wafer preparation 2. Wafer fabrication
Wafer preparation:
This Wafer must be:
 highly purified silicon (Impurities in parts per billion)
 single crystal silicon
 Smooth surface of silicon
 Sand: polycrystalline silicon of structures <100>, <111>, <110>
(a) Metallurgical grade silicon (b) electronic grade silicon

Formation of metallurgical grade silicon

 Reduction of silicon
 SiO2 + C SiC + O2
 SiC + SiO2 Si(l) + SiO(g) + CO(g)
Metallurgical grade silicon (impurity high in ppm) 5
 Purification of silicon
 Si (s) + 3HCL SiHCL3 (g)+ H2 (g) + Heat
 SiC + SiO2 Si(l) + SiO(g) + CO(g)

Fractional distillation
 2SiHCL3 + 2H2 (g) 2Si (s) + 6HCL
Electronic grade silicon - impurity in ppb

High purity silicon is obtained, now single crystal silicon is needed

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Conversion of silicon from polycrystalline to single crystal
Czochralski method

Process
1.The molten state silicon is kept in
the chamber and rotated with the
help of shaft.

2. Now the single crystals are

grown into the upper chamber
according to the seed crystal
provided.

3. This is formed as ingot with the

single crystal silicon.

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 Ingot formed in the silicon growing chamber as shown
below

 Ingot is now cut down with a diamond cutter to obtain this single
crystal silicon wafer.
 This silicon wafer obtained is-
 Highly purified electronic grade silicon
 Single crystal
 Impurities in ppb (very less).

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 The surface of the wafer must be smooth and with no impurity left.
For this, a process called chemical mechanical polishing is done to
get a smoother and clean surface.

Cross sectional view 9

 Chemical mechanical polishing process

 The slurry consisting of SiO2 and NaOH solution is poured slowly

onto the edges of wafer and then whole table is rotated with help of
rotating shaft.

 This creates friction at the complete surface of the wafer which

smoothens the same surface.

 Thus a wafer with a smooth surface is obtained by this process.

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Now the wafer obtained by this whole process is:
 Highly purified
 Single crystal
 Impurities in the order of ppb.
 Smooth and clean surface.
Now we need to fabricate CMOS/NMOS/PMOS on the wafer.

Wafer fabrication
Steps involved in wafer fabrication
 Layering
 Lithography
 Heat treatment
 Doping

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 Layering
Addition of new layer on silicon wafer
Grown
 Layering consumes silicon
from the underlying substrate
(wafer).
 Used to grow thick oxide
 Provides poor dielectric
Deposition
 Layering consumes silicon from
the underlying substrate (wafer).
 Used to grow thin oxide
 Used to form capacitor
 Provides good dielectric with
better electrical properties.
 Deposition :
 CVD (chemical vapor
deposition)
 PVD (physical vapor
deposition)
 Sputtering
 Electroplating
 Thermal evaporation
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 Need of oxidation/layering
 It is protective layer or mask against diffusion or ion implantation.
 While doping N+ region (addition of extra impurities), selective
region is doped and other regions are masked with the help of
oxidation process by creating a layer of SiO2.

 Protective layer/Isolator against the active circuits (PMOS, NMOS).

 Provides physical/mechanical support and chemical protection.

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 Oxidation types
Wet oxidation Dry oxidation

 Si + 2H2O SiO2 + 2H2  Si + O2 SiO2

(s) (g) (s)
(s) (g) (s) (g)
 Used to grow thick oxide for
 Used to grow thin oxide to form
masking. capacitor.
 Growth rate very high
 Growth rate very low (100nm/hr)
(1µm/hr)  Used to form capacitor
 Provides leakages as  Provides no leakages as
compared to dry oxidation compared to wet oxidation
 Provides poor dielectric  Provides good dielectric
 Poor electrical behavior  Better electrical behavior

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 Nitridation
Formation of Si3N4 (silicon nitride)

 Used to mask the outer layer of the wafer. This is called

passivation.
 Protective layer against external impurities and materials.

Properties of Si3N4:
 High melting point so that withstands the heat treatment at
very large temperature.
 Corrosion free against sodium and moisture.

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 Deposition
No consumption of silicon from the underlying substrate
Types of deposition:

CVD (chemical vapor deposition) PVD (physical vapor deposition)

 Chemical process involved to or sputtering
 A physical external force
the formation of vapor and
then the vapor is deposited (voltage or current) is applied
onto the wafer to create the ions and the ions
are deposited onto the wafer

 CVD:
 Used to form polysilicon (used to place just above this thin
oxide)

 Used to form Si3N4

 Used to form SiO2 16

 Chemical process involved in CVD
Formation of polysilicon
 SiH4 Si + 2H2
(silane)(g) polysilicon

Formation of Si3N4

 SiCl2H2 + 4NH3 SiN4 + 6HCl+6H2

Dichlorosilane Nitride for outer masking

Formation of SiO2
 SiH4 + O2 SiO2 + 2H2
Silane SiO2 for isolation and dielectric

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 Sputtering (PVD-physical vapor deposition)
Layering of the metal onto the surface by sputtering process under
deposition technique
 Used to deposit metals for interconnects.

 Electrodes are connected to the source, gate and drain through this
metals (interconnects) so that whatever potential is applied at the
electrode, its effect comes to the n+ region or oxide respectively.

 This method of depositing metal layer to form interconnects is

known as metallization or PVD.

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Arrangement for sputtering/metallization

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 Process involved in sputtering/metallization
 The argon gas (inert gas) is introduced into the metallization
chamber.
 Argon having high kinetic energy when enters into the chamber
comes under the influence of electric field and forms a plasma.
 This plasma consists of ions, molecules, radicals etc. The positive
ions will be moving towards the cathode and negative electrons or
radicals will move towards the anode.
 As this gas is having high kinetic energy when it is interacted with
the target metal, it ejects the metal atoms from the metal surface
and leads to gets sputter onto the substrate/wafer.

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 This sputtered metal atoms onto the substrate is only the metal
layer deposited onto the wafer.

Thus sputtering/metallization is the process where removal or

dislodging of metal atoms is done from its surface by using high
kinetic energy argon gas.

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 Photolithography
The transfer of image from photo-mask to the surface of wafer i.e.,
patterning/designing of the wafer.
Photo litho graphy
light rays stone writing
 UV rays are used to pattern the wafer which is required for doping at
the selective area.

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 Process involved in the photolithography
1. Photoresist coating
Coat the oxidized wafer with light sensitive material called
photoresist (liquid polymer which has the property of changing its
chemical property when exposed to light).
 Drop the photoresist onto the surface and let it spin at 3000 rpm.
 This leads to spread the phtoresist onto the wafer surface.

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 Process involved in the photolithography
2. Depolymerization of the photoresist.
 Expose the wafer coated with photoresist with UV radiations by the
help of a photomask.
Photomask is the glass material coated with chromium through
which UV rays are exposed.
 This mask is selectively transparent and opaque.

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 The photoresist area which is under the transparent section when
illuminated with UV rays gets depolymerized i.e., changes its
chemical properties.

3. Removal of depolymerized area from the surface of the wafer to

make space for the doping.
 A developer chemical (aquous) solution is used to remove the
depolymerized area from the photoresist.
 The wafer is put into the developers solution and the photoresist
comes into the contact of developers solution it gets dissolved and
removed easily.

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 Now the structure will look like-

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Photoresist types based on chemical properties
Positive photoresist
 Photoresist exposed to UV
radiations are removed for the
wafer surface.
 Easier to process.
 Surface resolution is better
than negative PR.
 Less leakege
Negative photoresist
 Photoresist unexposed to UV
radiations are removed for the
wafer surface.
 Complicated
 Surface resolution is poor as
compared to positive PR
 More leakages.
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 Heat treatment (at 100-120oc)
Need of the heat treatment
 To provide the cross linkages between the different materials as well
as photoressist polymer itself (as many polymers are combined to
form a single polymer).
 To provide chemical stability so that desired material only is
removed not the neighbor material.
 To provide thermal stability (so that after one heat treatment no
effect does happen for further external heat exposure)

 To provide better adhesion of SiO2 with the substrate.

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Etchnig of SiO2 from the wafer surface to
create space for doping

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 Plasma etching process
Removal of material from the surface
 Argon gas is introduced in the chamber shown.
 Under the influence high electric field the argon gas forms a plasma
which gains high kinetic energy and is bombarded to the wafer
surface.
 This plasma reacts with the surface material and the material to be
removed gets dissolve with this gas and then is removed easily.

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 Types of etching
Dry etching Wet etching
 Etchnig takes place from one  Etchnig takes place from all the
particular direction. directions (randomly).

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 Types of etching
Dry etching
 Etchnig done at plasma
phase.
 Uses gaseous from chemical
solution.
 Provides precise structure.
 Expensive (specialized
equipments are needed).
 Much safer process than wet
etching.
 Poor selectivity: (sometimes
also selects another area to
remove which is not required)
Wet etching
 Etchnig done at liquid phase.
 Uses liquid chemical solution.
 Provides non- precise structure.
 Less expensive (use only
chemical bath).
 Not safe as the disposing of
hazardous chemicals cause
water contamination.
 Good selectivity: (no other area
is removed which is not required.
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 Doping
Creating a junction in the wafer by adding external impurities.
There are 2 ways of processing this. (1) Diffusion (2) Ion
implantation
Diffusion takes place in two steps:
 Predeposition
 Drive-in
 In predeposition process fixed number of impurity atoms are
deposited onto the wafer surface.
 In drive in process the deposited impurity is driven into the silicon
to form junctions.

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 Arrangement for diffusion process
 Plasma of inert gas and dopant gas is introduced inside the
chamber at a temperature of 1200oC
 This works on the principle of movement of carriers from high
potential to low potential (diffusion)
 This gets deposited at the surface of the wafer. This is called
predeposition.

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 Once the predepositipn is done, the valve is closed and then again
operated at a particular temperature for given time.
 Now the deposited atoms will diffuse inside the wafer forming the n
well.
 The time taken for the drive in process will define the depth of the
junction. Longer is the operation time, deeper will be the junction
created.

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 Ion implantation
 Requires electric field to provide high kinetic energy for the plasma
of inert gas and dopant gas to get introduced inside the chamber.

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 Process of Ion implantation
 A magnetic plate is connected to separate the lighter and heavier
ions and allows only the desired atoms (n+ for NMOS) inside the
chamber.
 These atoms at high kinetic energy gets implanted into the silicon
wafer.
 Thus the n+ well is created in the wafer.
Ion implantation depends upon two factors.
 Depth of the junction depends upon the kinetic energy provided
and that is decided by the electric field provided.
 Concentration in the n+ region depends upon the ion beam
concentration injected inside the chamber.
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Comparison between diffusion and ion implantation
Diffusion Ion implantation
 Principle: diffusion from low  Principle: bombardment of ion
conc. to high conc. beam at high kinetic energy in
 Temperature required: 1200oC electric field.
 Not precise structure.  No temp. required, only
 Provides isotropic junction acceleration voltage is required.
profile.  Provides anisotropic junction
 No surface defects profile.
 Surface defects present. Due to
bombarding of ions.

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Thank you…