Chap 3:

CMOS
Processing
Technology
CMOS Processing Technology 1
 Outline
 Wafer formation
 Photo lithography
 Oxidation
 Source drain formation (ion implantation)
 Contacts and metallization (PVD)
 Layout Design rules
 CAD

CMOS Processing Technology CMOS VLSI Design 4th Ed. 2

 Why do I care how transistors are made?

 Underlying design rules and in turn use this

knowledge to create a better design.
 Debugging some difficult chip failures
 Fabs are enormously expensive, therefore we need
to improve yield.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 3

CMOS Processing Technology CMOS VLSI Design 4th Ed. 4
 Wafer Formation
 The basic raw material used in CMOS fabs is a
wafer or disk of silicon, roughly 75 mm to 300 mm
(12”- a dinner plate!) in diameter and less than 1 mm
thick.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 5

 Photolithography
 Greek photo (light), lithos (stone), and graphe
(picture), which literally means “carving pictures in
stone using light.”
 Select areas of interest … The wafer is coated with
the photoresist and subjected to selective
illumination through the photomask.
 polycrystalline silicon, silicon dioxide, or silicon
nitride can be used as physical masks on the chip
 A photomask is constructed with chromium (chrome)
covered quartz glass

CMOS Processing Technology CMOS VLSI Design 4th Ed. 6

 Photolithography

CMOS Processing Technology CMOS VLSI Design 4th Ed. 7

 Photolithography
 The UV light floods the mask from the backside and
passes through the clear sections of the mask to
expose the organic photoresist (PR) that has been
coated on the wafer.
 A developer solvent is then used to dissolve the
soluble unexposed photoresist, leaving islands of
insoluble exposed photoresist. This is termed a
negative photoresist. A positive resist is initially
insoluble, and when exposed to UV becomes
soluble.
 Positive resists provide for higher resolution than
negative resists, but are less sensitive to light.
CMOS Processing Technology CMOS VLSI Design 4th Ed. 8
 Photolithography
 As feature sizes become smaller, the photoresist
layers have to be made thinner.
 In turn, this makes them less robust and more
subject to failure which can impact the overall yield
of a process and the cost to produce the chip.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 9

 Well and Channel Formation
n-well process - pMOS transistors are built in a n-well
p-well process - nMOS transistors are built in a p-well
twin-well process – nMOS in p-well, pMOS in n-well
triple-well process – Additional deep well

CMOS Processing Technology CMOS VLSI Design 4th Ed. 10

 Well and Channel Formation
 Wells and other features require regions of doped
silicon. Varying proportions of donor and acceptor
dopants can be achieved using epitaxy, deposition,
or implantation

 Epitaxy involves growing a single-crystal film by

subjecting the silicon wafer surface to an elevated
temperature and a source of dopant material.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 11

 Well and Channel Formation
 Deposition involves placing dopant material onto the
silicon surface. Chemical Vapor Deposition (CVD)
occurs when heated gases react in the vicinity of the
wafer and produce a product that is deposited on the
silicon surface.

 Ion implantation involves bombarding the silicon

substrate with highly energized donor or acceptor
atoms

CMOS Processing Technology CMOS VLSI Design 4th Ed. 12

 Well and Channel Formation
 Transistors near the edge of a retrograde well (e.g., within
about 1 um) may have different threshold voltages than those
far from the edge because ions scatter off the photoresist mask
into the edge of the well, as shown in Figure This is called the
well-edge proximity effect.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 13

 Silicon Dioxide (SiO2)
 Various thicknesses of SiO2 may be required,
depending on the particular process. Thin oxides are
required for transistor gates;
 thicker oxides might be required for higher voltage
devices,
 while even thicker oxide layers might be required to
ensure that transistors are not formed unintentionally
in the silicon beneath polysilicon wires
Oxidation of silicon is achieved by heating silicon wafers
in an oxidizing atmosphere.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 14

 Silicon Dioxide (SiO2)
 Wet oxidation––oxidizing atmosphere contains water
vapor. Temperature 900 °C - 1000 °C. Rapid Process

 Dry oxidation––oxidizing atmosphere is pure oxygen.

Temperatures around 1200 °C. Dry oxidation forms a
better quality oxide than wet oxidation. It is used to
form thin, highly controlled gate oxides, while wet
oxidation may be used to form thick field oxides.

CMOS Processing Technology CMOS VLSI Design 4th Ed. 15

 Gate Oxide
 The oxide structure is called the gate stack. This
term arises because current processes prefer to
produce a stack that consists of a few atomic layers,
each 3–4 Å thick, of SiO2 for reliability, overlaid with
a few layers of an oxynitrided oxide (one with
nitrogen added).

CMOS Processing Technology CMOS VLSI Design 4th Ed. 16

 Gate and Source/Drain Formations

 Grow gate oxide wherever transistors are required

(area = source + drain + gate)–– elsewhere there
will be thick oxide or trench isolation
 Deposit polysilicon on chip
 Pattern polysilicon (both gates and interconnect)
 Etch exposed gate oxide—i.e., the area of gate
oxide where transistors are required that was not
covered by polysilicon
 Implant pMOS and nMOS source/drain regions

CMOS Processing Technology CMOS VLSI Design 4th Ed. 17

 Gate and Source/Drain Formations

CMOS Processing Technology CMOS VLSI Design 4th Ed. 18