Fabrication Process

•Crystal Growth
•Doping
•Deposition
•Patterning
•Lithography
•Oxidation
•Ion Implementation
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VLS I DES IGN LAB
 Fabrication- CMOS Process

Starting Material Preparation

1. Produce Metallurgical Grade Silicon (MGS)

SiO2 (sand) + C in Arc Furnace
Si- liquid 98% pure

2. Produce Electronic Grade Silicon (EGS)

HCl + Si (MGS)
Successive purification by distillation
Chemical Vapor Deposition (CVD)

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VLS I DES IGN LAB
 Fabrication: Crystal Growth

Czochralski Method
 Basic idea: dip seed crystal into
liquid pool
 Slowly pull out at a rate of

0.5mm/min
 controlled amount of

impurities added to melt

 Speed of rotation and pulling

rate determine diameter of the

ingot
 Ingot- 1to 2 meter long
 Diameter: 4”, 6”, 8”
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VLS I DES IGN LAB
 Fabrication: Wafering

 Finish ingot to precise diameter

 Mill “ flats”
 Cut wafers by diamond saw:
Typical thickness 0.5mm
 Polish to give optically flat
surface

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VLS I DES IGN LAB
 Fabrication: Oxidation

Quartz Tube
 Silicon Dioxide has several uses:
- mask against implant O 2 or Water
Pump Wafers
or diffusion Vapor
- device isolation
- gate oxide
- isolation between layers Quartz Carrier

 SiO2 could be thermally generated Resistance Heater

 or through CVD

 Oxidation consumes silicon

 Wet or dry oxidation

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VLS I DES IGN LAB
 Fabrication: Diffusion
 Simultaneous creation of p-n junction over
the entire surface of wafer
 Doesn’t offer precise control
Temp: 1000
 Good for heavy doping, deep junctions
 Two steps: wafers
Dopant Gas
Pre-deposition
Dopant mixed with inert gas introduced
in to a furnace at 1000 oC.
Atoms diffuse in a thin layer of Si surface Resistance Heater
Drive-in
Wafers heated without dopant

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VLS I DES IGN LAB
 Fabrication: Ion
Implantation
 Precise control of dopant
 Good for shallow junctions and threshold adjust
 Dopant gas ionized and accelerated
 Ions strike silicon surface at high speed
 Depth of lodging is determined by accelerating field

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VLS I DES IGN LAB
 Fabrication: Deposition
 Used to form thin film of Polysilicon,
Silicon dioxide, Silicon Nitride, Al.

 Applications: Polysilicon, interlayer Loader

oxide, LOCOS, metal.
0.1 -1 Torr
Pump Reactant
 Common technique: Low Pressure
Chemical Vapor Deposition (CVD).

 SiO2 and Polysilicon deposition at

300 to 1000 oC.
 Aluminum deposition at lower
temperature- different technique

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VLS I DES IGN LAB
 Fabrication:
Metallization
 Standard material is Aluminum

 Low contact resistance to p-type and n-type

 When deposited on SiO2, Al2O3 is formed: good adhesive

 All wafer covered with Al

 Deposition techniques:
Vacuum Evaporation
Electron Beam Evaporation
RF Sputtering

 Other materials used in conjunction with or replacement to Al

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VLS I DES IGN LAB
 Fabrication: Etching
Wet Etching
 Etchants: hydrofluoric acid (HF), mixture of nitric acid and
HF
 Good selectivity
 Problem:
- under cut
- acid waste disposal

Dry Etching Plasma Reactive species

 Physical bombardment with atoms or ions
 good for small geometries.
 Various types exists such as:
Planar Plasma Etching RF
Reactive Ion Etching
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VLS I DES IGN LAB
 Fabrication:
Lithography
Mask making
 Most critical part of lithography is conversion from layout to
master mask

 Masking plate has opaque geometrical shapes corresponding

to the area on the wafer surface where certain photochemical
reactions have to be prevented or taken place.

 Masks uses photographic emulsion or hard surface

 Two types: dark field or clear field

 Maskmaking: optical or e-beam

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VLS I DES IGN LAB
 Lithography: Mask
making
Optical Mask Technique

1. Prepare Reticle
Use projection like system:
-Precise movable stage
-Aperture of precisely rectangular size and angular orientation
-Computer controlled UV light source directed to photographic plate
After flashing, plate is developed yielding reticle

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VLS I DES IGN LAB
 Fabrication:
Lithography

Step & Repeat

Printing

Printing
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VLS I DES IGN LAB
 Lithography: Mask
making
Electron Beam Technique

 Main problem with optical

technique: light diffraction

 System resembles a
scanning electron microscope +
beam blanking and computer
controlled deflection

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VLS I DES IGN LAB
 Patterning/ Printing
 Process of transferring mask features to surface of the silicon wafer.

 Optical or Electron-beam

 Photo-resist material (negative or positive):synthetic rubber or

polymer upon exposure to light becomes insoluble ( negative ) or
volatile (positive)

 Developer: typically organic solvant-e.g. Xylen

 A common step in many processes is the creation and selective

removal of Silicon Dioxide

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VLS I DES IGN LAB
 Patterning: Pwell mask

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VLS I DES IGN LAB
 Patterning/ Printing

SiO2

substrate

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 Fabrication Steps
Inspect, measure

Post bake
Etch

Develop, rinse, dry

Strip resist
Printer align expose
mask

Deposit or grow layer

Pre-bake

Apply PR
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VLS I DES IGN LAB
 Fabrication Steps

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VLS I DES IGN LAB
 Fabrication Steps: P-
well Process
VDD
Diffusion
P+

P+
Vin
P well Vo
n+ n+ p+
p+ p+ p+

n+
n+
Substrate n-type
P well
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VLS I DES IGN LAB
 Fabrication Steps: P-
well Process
VDD
Diffusion
P+

P+
Vin
P well Vo
n+ n+ p+
p+ p+ p+

n+
n+
Substrate n-type
P well
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VLS I DES IGN LAB
 Fabrication Steps

n+ n+
p+ p+
P well

n+ n+ p+ p+

P well

Substrate n-type

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VLS I DES IGN LAB
 Fabrication Steps
Oxidation oxide

Substrate n-type

Patterning of P-well mask

Substrate n-type

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VLS I DES IGN LAB
 Fabrication Steps
Diffusion: p dopant,
Removal of Oxide
P-well

Si3N4

Deposit Silicon Nitride

P-well

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VLS I DES IGN LAB
 Fabrication Steps
Patterning: Diffusion (active)
mask
P-well

substrate

FOX FOX FOX

Oxidation

substrate
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VLS I DES IGN LAB