The Mainstreaming of SOI

G. K. Celler and Andrew Wittkower

Soitec USA
2 Centennial Drive, Peabody, MA 01960, USA

Christophe Maleville
Soitec S. A.
Parc Technologique des Fontaines
38926 Crolles Cedex, France

Geoffrey Ryding and Peter Rose

Applied Materials
66 Cherry Hill Drive, Beverly, MA 01915, USA

Abstract— Silicon-on-Insulator (SOI) technology has recently
moved from niche applications into the mainstream of the IC
industry. Circuits built on SOI substrates provide higher
switching speed and/or reduced power consumption. As device
dimensions are reduced into sub-50nm regime, proper device
scaling will increasingly rely on SOI structures.
Keywords- SOI; Silicon-on-Insulator; Smart Cut; layer
transfer; silicon wafers
I. INTRODUCTION
After years of discussions and arguments, the major players in
Si chip manufacturing have embraced SOI as the wafer
technology for high performance ICs. Device scientists and
circuit designers learned to fully utilize unique properties of
the new substrates for improved circuit performance. IBM,
backed by a large design effort, started commercial
manufacturing of microprocessors on SOI in 1999. Other large
IC suppliers, including AMD, Motorola, Philips, and Intel,
have publicly announced that they will launch future
generations of their ICs on SOI.
SOI wafers consist of a layer of device quality single
crystalline Si that is separated from a Si substrate by an
insulating film of SiO2 [1]. Building active devices in this top
Si film provides many advantages, the most obvious one being
reduced parasitic capacitance of the source and drain of MOS
transistors, which in turn leads to higher switching speeds [2].
Commercial methods of SOI wafer fabrication are based
predominantly on ion implantation. The main approach is a
technology known as the Smart Cut process, in which ion
implantation, typically of hydrogen, defines the thickness of the
top Si layer [3]. Many hundreds of thousands Unibond®
wafers are produced annually by this method that involves
transfer of thin Si films to “handle” wafers in order to form SOI
wafers.
Another important method involves direct synthesis of
buried oxide under a superficial film of Si. Oxygen
implantation and high temperature annealing, in a process that
is commonly known as SIMOX, lead to formation of a buried
SiO2 film [4]. Properties of this SiO2 are similar to that of
thermal SiO2 but some differences remain. High temperature
internal oxidation further improves the buried oxide [5].
II. SMART CUT FABRICATION PROCESS
SOI wafers are produced by the Smart Cut process in a
state-of-the-art Soitec factory in Bernin, outside of Grenoble,
France. The production facility is within a Class 1 cleanroom,
and processing is done predominantly with standard equipment
from the semiconductor equipment suppliers.
Conventional bulk Si wafers are used as the starting
material for both the handle and the Si film of the final SOI
product. The characteristics of these two wafer groups are often
different. Crystalline quality of the Si film that will be
transferred to a handle wafer is of utmost importance. For that
reason, “seed” or “donor” wafers must have the minimum of
defects of any kind. Conventional CZ material has COP
(crystal originated particle) defects that are formed by
agglomeration of vacancies during crystal pulling from the
melt. With the steady shrinkage of device design rules, the
deleterious impact of COP defects has been increasing. Special
techniques have been developed by the leading Si suppliers to
produce nearly COP-free Si wafers. Unibond® wafers are
typically made by transferring Si layers from the COP-free Si

- 637 - 0-7803-7155-0/02/$10.00 © 2002 IEEE

seed wafers. An alternative is to transfer epitaxially grown Si make sure that the wafer surfaces are hydrophilic and free of
films, since they do not contain any COPs. particles. The surface conditioning is very important for the
initial room temperature bonding since hydrogen bridges to
The requirements for handle wafers are less stringent. water molecules trapped between wafers provide the adhesion.
Wafer flatness and lack of contamination are important, but
crystalline quality and dopant concentration are of less
significance.
Seed and handle wafers are brought together for alignment
and bonding in commercial fully automated cassette-to-cassette
bonding systems. A robotic arm that applies light pressure at
After wet cleaning, the incoming seed Si wafers are one point, initiates adhesion of two wafers, and the “bonding
oxidized in vertical furnaces to obtain very uniform oxide wave” rapidly spreads across the entire wafer surface.
thickness. This oxide helps to dechannel hydrogen ions during
implantation and later becomes the buried oxide (BOX) of the
SOI structure. Typical 200 nm thick oxide films are grown with
a uniformity of ±4% (6 σ). Wafer splitting along the hydrogen-rich zone is the next
step. This is done in a batch mode in a horizontal furnace, in
which wafer pairs are heated to about 500°C. The heat
treatment causes growth of some hydrogen filled voids and
The next step is a key to the process and an original use of
microcracks at expense of others that disappear, in a process
implantation. Hydrogen ions are implanted through the oxide
that is known as Ostwald ripening. Molecular hydrogen
and into the underlying silicon where they stop at a distance
segregates into the growing microcracks and the pressure
determined by the initial energy of the ions. Here, near the end
buildup inside these hydrogen filled cavities leads to splitting
of the range there is a concentration of damage and hydrogen
of the entire layer of Si, with thickness uniformity determined
that provides the means to separate a thin silicon slice from the
by the depth uniformity of the implant.
bulk of the wafer as will be described below. For various
reasons the proton energy required by the process is higher than
the range tables would predict for a given BOX and silicon
thickness and the dose required to produce consistent After splitting, the SOI wafers undergo cleaning, surface
separation is in the mid 1016 ions/cm2. As devices become smoothing by CMP and more cleaning. Si and BOX thickness
smaller, the silicon and BOX layers will become thinner and and thickness uniformity are measured simultaneously at 1500-
the implant energy must be correspondingly reduced. The 3000 points per wafer by spectroscopic reflectometry. Other
process requires an ion implanter that will provide protons optical tools that are adjusted to compensate for non-standard
from 60 keV to as low as 25 keV or have twice that energy reflectivity of SOI wafers, detect particles on the surface.
range if H2+ is used. To achieve reasonable throughputs, beam
currents in excess of 30mA are required and standard
implanters with a slightly modified ion source can provide Standard semiconductor processing equipment is used in
these currents. An immediate advantage provided by these 200mm and 300mm Smart Cut production lines. For example,
machines is the well-developed tilt and twist control with wafer 300mm wafers are oxidized in A412 vertical furnaces from
cooling and the automated wafer handling that is needed for ASM. Quantum ion implanters from Applied Materials implant
throughput and process consistency. It is tempting to consider hydrogen into batches of 13 300 mm wafers that are mounted
an improved implanter incorporating a long lived hydrogen ion on a spinning wheel. Preclean before bonding is done in
source delivering more than 100 mA so that the implanter cassette-less Megasonic systems that process 25 wafers at a
would operate at its maximum mechanically limited throughput time. Bonding of the seed and handle wafers proceeds in
circa 200 wafers per hour, however this is for the future. commercial systems from EVG, which are compatible with
both 300 and 200 mm wafer formats. Wafer splitting occurs in
horizontal furnaces with low cost of ownership.
Presently, batches of wafers are loaded into the selected
implanter by placing them on a large wheel that spins in front TABLE I. SOITEC ULTRATHIN PRODUCTS ROADMAP
of an oval-shaped ion beam. A suitably chosen wafer tilt and
twist minimize ion channeling. Hydrogen implantation induced Time line 2000 2001 2002 2003 2004
damage zone includes various defects, among them a Process generation PD FD UT1 UT2 XUT
significant density of voids and microcracks. A large fraction
of hydrogen is chemically bound to the dangling Si bonds at Silicon Layer Thickness 1000 500-700 200-700 200-300 200
(Å)
the interfaces of the voids and microcracks, and it passivates
6σ (Å)
Si unif 6σ 150 100 70 30 10
these internal surfaces. This passivation effect prevents healing
of the microcracks during the early phase of thermal annealing. 6σ; all wrs all
Si unif 6σ ±7% ±7% ±6% ±5% ± 2.5 %
sites (%)
In addition to H atoms that are tied to Si, some molecular
Roughness AFM(RMS)
hydrogen fills the microcracks and voids [6]. • 1x1 µm 1Å 1Å 1.5 Å 2Å 2Å
• 10x10 µm 1.5 Å 1.5 Å 3Å 4Å 5Å
Box Layer Thickness (Å) 1500-2000 1000-1500 1000-1500 800-1500 800-1500
To prepare wafers for bonding, both the seed and the handle Box Layer TTV ± 4% ± 4% ± 3% ± 3% ± 3%
wafers go through multiple phases of wet cleaning, in order to

- 638 - 0-7803-7155-0/02/$10.00 © 2002 IEEE

 If CMP is needed, Reflexion CMP units from Applied
Materials are used. These are dry-in dry-out systems with in- Volume or Surface
situ post-polishing cleaning and with integrated closed loop
thickness control. contamination
COP's
Scratches
III. EVOLUTION OF COMMERCIAL SPECS
Device scaling that is required to continue the progression
along the Moore’s curve has a strong impact on SOI wafer
parameters as well. As we move from 130 to 90 to 65 nm
device generation, Si film thickness has to scale as well. A
transition from partially depleted (PD) to fully depleted (FD) SiO2 Precipitates
device designs that is likely to occur in the next few years,
further accelerates the demand for thinner Si films. Buried
oxide also needs to scale down in thickness, although not as
rapidly. Table I lists five progressively thinner SOI wafer
categories and their specifications. PD, FD, and UT1
(UltraThin 1) wafers are in production, UT2 and XUT in Figure 2. Defects delineated by 15 min immersion in HF
prototyping. A matrix of currently available film thicknesses is
also shown in Figure 1. SOI wafers with 500Å of Si on 1000Å
of BOX are in full production, while 200Å Si films are
available as prototypes. A feasibility of producing even thinner Standard particle measurement tools, when applied to SOI
films, such as 100Å of Si on 200Å of oxide has been wafers, detect not only dust particles but also light scattering by
established. COPs. For very clean SOI wafers most of the counts come
from crystalline defects. In Fig. 4, which represents data
obtained from about 50,000 200 mm wafers measured over 47
weeks, defect densities for SOI wafers made of COP-free
material are significantly below those of CZ wafers (the first
data point on the left), and slightly above those of epi wafers
(the last data point). It is also worth noting that the median
densities of defect counts are consistently low at about
20/wafer.

Figure 1. A matrix of available Si and BOX thicknesses. Production,

prototyping, and feasibility capabilities are identified.

1
IV. DEFECT CONTROL
HFD Density (/cm²)

0,8
Voids at the bonding interface that were observed during the 0,6
early years of wafer bonding, are now extremely rare. Other
0,4
major defects are best revealed by the HF acid test. Immersion
of SOI wafers for 15-30 min in HF reveals all sites where the 0,2

acid can penetrate through the Si film to the buried oxide, as 0

shown in Fig. 2. CZ Low Cops
CZ Perfect
Starting Silicon crystal

Since scratches and contamination have been largely

eliminated in the automated SOI process lines, COPs are the
main source of HF-revealed defects. In Fig. 3, the density of Figure 3. HF induced defect densities in SOI for two types of seed wafers.
such defects is compared for two SOI wafers, where the seed
wafer was either a CZ-type wafer or a perfect crystal (free of
COPs).

- 639 - 0-7803-7155-0/02/$10.00 © 2002 IEEE

 provider of SOI material, has just opened a second fab, Bernin
II, which will increase company’s capabilities to 2 million
wafers per year (200 mm equivalent) when fully equipped. If
On the way down to Epi spec the IC industry projections hold true, many new factories will
need to be built in the coming decade by Soitec and by others.
CZ
CZ Sum of Defects / Week
200 EPI
Epi
180

160 REFERENCES
140 [1] Jean-Pierre Colinge, Silicon-on-Insulator Technology: Materials to
VLSI, 2nd edition (Kluwer, Boston 1997).
1100/2000 Å
Sum of defects (counts)

120

100 Unibond [2] Jean-Luc Pelloie and André Auberton-Hervé, “A new generation of IC
processing: low-power, high-performance SOI CMOS.” Solid State
80
Technology, Vol. 44, 63 (Nov. 2001).
60
[3] B. Aspar, H. Moriceau, E. Jalaguier, C. Lagahe, A. Soubie, B. Biasse, A.
40 M. Papon, A. Claverie, J. Grisolia, G. Benassayag, F. Letertre, O.
20
Rayssac, T. Barge, C. Maleville, and B. Ghyselen, “The generic nature
of the Smart- Cut® process for thin film transfer,” J. Electronic
0 Materials, Vol. 30, 834 (2001).
W k
[4] S. Krause, M. Anc, and P. Roitman, “Evolution and Future Trends of
Figure 4. Weekly distributions of defect counts per 200 mm wafer at a SIMOX Material” MRS Bulletin, Vol. 23(12), 25 (1998).
detection level >0.16 µm [5] S. Nakashima, T. Katayama, Y. Miyamura, A. Matsuzaki, M. Kataoka,
D. Ebi, M. Imai, K. Izumi, N. Ohwada, “Investigations on High-
Temperature Thermal Oxidation Process at Top and Bottom Interfaces
of Top Silicon of SIMOX Wafers, ” J. Electrochem. Soc., Vol. 143, 244
(1996).
V. CONCLUSIONS
[6] M. K. Weldon, V. E. Marsico, Y. J. Chabal, A. Agarwal, D. J.
The consumption of SOI wafers is expected to grow Eaglesham, J. Sapjeta, W. L. Brown, D. C. Jacobson, Y. Caudano, S. B.
rapidly, with independent industry analysts forecasting usage of Christman, and E. E. Chaban, “On the Mechanism of the Hydrogen-
Induced Exfoliation of Silicon” J. Vac. Sci. Technol. Vol. B 15, 1065
up to 30 million wafers in 2008. To satisfy this demand, the (1997).
SOI wafer suppliers are converting to 300 mm wafers and
ramping up their output capabilities. Soitec, already the largest

- 640 - 0-7803-7155-0/02/$10.00 © 2002 IEEE