Level-4, Term-2 (‘16th Batch)

EEE-489: VLSI Technology

Introduction

Dr. Sampad Ghosh

Assistant Professor
Department of Electrical and Electronic Engineering
Faculty of Electrical and Computer Engineering
Chittagong University of Engineering and Technology (CUET)

March 22, 2021

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KYUSHU UNIVERSITY
Syllabus
EEE 489: VLSI Technology (Credit 3.0)
Introduction to MOS devices: design of inverters, static and dynamic
logic circuits, Domino and zipper logic, Custom, semi-custom and cell library
based design, Design of analog building backs, Effect of device scaling on
circuit performance. Overview of IC Technology and its requirements.
Unit steps used in IC Technology: Wafer cleaning, photo-lithography, wet
and dry etching, oxidation and diffusion, ion implantation, CVD and LPCVD
techniques for deposition of poly silicon, silicon nitride and silicon di-oxide,
Metallization and passivation.
Special techniques for modern processes: self-aligned silicides, shallow
junction formation, nitride oxides etc. Process flows for CMOS and bipolar IC
processes. Introduction to process, device, circuit logic and timing
simulation, Hardware description languages for high level design.

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Reference books

1. Gary S. May and Simon M. Sze, Fundamentals of Semiconductor

Fabrication, John Wiley & Sons Inc.

2. Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated

Circuits: Analysis and Design, 3rd ed., McGraw-Hill.

3. James D. Plummer, Silicon VLSI Technology: Fundamentals,

Practice and Modeling, Pearson Education.

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 Topics Reference
Introduction

Semiconductor materials, Semiconductor process

S.M. Sze
technology, Basic fabrication steps

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What is Semiconductors?
❑ Semiconductors are materials which have a conductivity between conductors
(e.g., metals) and nonconductors or insulators (e.g., ceramics).
o Semiconductors can be pure elements (e.g., silicon or germanium), or compounds
(e.g., gallium arsenide or cadmium selenide).
❑ Advantages
o Doping provision
o Ability to conduct electrical current
o Regulated conductivity
❑ Si is most widely used
o Can be obtained very easily
❑ Early developments semiconductor – 1600s to 1800s.

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Semiconductor Process Technology
❑ Many important semiconductor technologies have been derived from
processes invented centuries ago.
o Growth of metallic crystals in a furnace was pioneered by Africans living on the
western shores of Lake Victoria more than 2000 years ago.
o Lithography process was invented in 1798 (Originally the pattern or image was
transferred from a stone plate or litho).

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Semiconductor Process Technology…
❑ Technologies applied for the 1st time to semiconductor processing for device
fabrication.
Sl. Year Technology 1. Czochralski technique is used to grow most of
1 1918 Czochralski crystal growth the Si crystal wafers.
2 1925 Bridgman crystal growth 2. Bridgman process used for growth of gallium
3 1952 III-V compounds
arsenide and related compound semiconductor
4 1952 Diffusion
crystals.
5 1957 Lithographic photoresist
3. Welker proved gallium arsenide and III-V
compounds are semiconductor.

4. Basic diffusion theory was considered by Fick in 1855. Alter the type of conductivity using
diffusion was patented by Pfann.
5. Andrus used photosensitive polymer for pattern transfer.

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Semiconductor Process Technology…
Sl. Year Technology 6. Frosch and Derrick found an oxide layer can

6 1957 Oxide masking prevent most impurity atoms from diffusing

7 1957 Epitaxial CVD growth through it.
8 1958 Ion implantation 7. Sheftal et al. describes a technique to form thin
9 1959 Monolithic IC layer of semiconductor materials.
10 1960 Planar process 8. Ion implantation was introduced by Shockley.

9. Noyce proposed monolithic IC by fabricating all devices in a single semiconductor substrate and
connecting devices by Al metallization.
10. In planar process developed by Hoemi, an oxide layer is formed on a semiconductor surface.
With the help of lithography process, portions of the oxide can be removed and windows cut in
the oxide. Impurity atoms will diffuse only through the exposed surface and p-n junctions will
form in the oxide window areas.

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Semiconductor Process Technology…
Sl. Year Technology 11. As the complexity of IC increased, technology

11 1963 CMOS moved from MOSFET to CMOS, and it’s proposed

12 1969 Polysilicon self-aligned gate by Wanlass and Sah. It consumes less power and
13 1971 Dry etching the dominant technology for advanced ICs.
14 1971 Molecular beam epitaxy 12. To improve device performance, polysilicon self-
15 1993 Copper interconnect aligned gate was proposed by Kerwin et al. It
improved device reliability and reduced parasitic
capacitance.

13. As device dimensions were reduced, dry etching technique was developed by Irving et al. to
replace wet etching.
14. MBE by Cho used for vertical control of composition and doping down to atomic dimensions.
15. Cu interconnect introduced by Paraszczak et al. to replace Al for minimum feature lengths
(100nm).

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Basic Fabrication Steps
❑ Today, planar technology is used extensively for IC fabrication.
❑ There are more than 200 processing steps. Major steps are:
✓ Oxidation
✓ Photolithography
✓ Etching
✓ Diffusion and Ion Implantation
✓ Metallization

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Basic Fabrication Steps…
❑ Oxidation
o Development of high quality SiO2 helped to establish the dominance of Si in the
production of commercial ICs.
o SiO2 functions as an insulator in a number of device structures or as a barrier to
diffusion or implantation during device fabrication.

❑ Two methods
1. Dry oxidation 2. Wet oxidation
Cleaned Si wafer
o Dry O2 is used o Water vapor is used
o Used to form thin oxides o Used for thicker layers
because of its good Si-SiO2 because of its higher
interface characteristics growth rate
After oxidation

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Basic Fabrication Steps…
❑ Photolithography
o Used to define the desired geometry.
o After formation of SiO2, wafer is coated with UV light sensitive
polymer (photoresist). Application of resist

o Wafer baked at 80°C to 100°C to evaporate solvent and to

harden resist for improved adhesion.
o Exposed region of photoresist coated wafer undergoes a
chemical reaction depending on type of resist.
o Area exposed to light becomes polymerized and difficult to
remove in an etchant. Resist exposure via mask

o Polymerized region remains when wafer placed in developer,

and unexposed region dissolves and washes away.

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Basic Fabrication Steps…
❑ Etching
o Wafer is again baked at 120°C to 180°C to enhance adhesion and improve resistance
to the subsequent etching process.
o Etching is used to remove materials from the wafer.
o An etch using BHF acid removes unprotected SiO2 surface.
o Resist is stripped away by a chemical solution or O2 plasma system.

Wafer after development After SiO2 removal After resist removal

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Basic Fabrication Steps…
❑ Diffusion and Ion Implantation
o Both are used for adding impurities to the wafer.
o In diffusion method, wafer surface not protected by oxide is exposed to a source with a
high concentration of opposite type impurity. Dopant gas or
accelerated impurity ions
o Impurity moves into wafer crystal by solid state diffusion.

o In ion implantation, impurities introduced by accelerating impurity

ions to a high energy level and then implanting the ions in wafer.
o SiO2 layer serves as barrier to impurity diffusion or ion
implantation.
o Due to lateral diffusion of impurities or lateral straggle of Diffusion or ion
Implantation process
implanted ions, width of p-region slightly wider than window
opening.

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Basic Fabrication Steps…
❑ Metallization
o Used to form ohmic contacts and interconnections.
o Metal films can be formed by physical vapor deposition
(PVD) or chemical vapor deposition (CVD).
o Here, photolithography technique is used to define front
After metallization
contact.
o Similarly back contact formed without using lithography
process.
o A low temperature (≤500°C) anneal also performed to
promote low resistance contact between metal layers and
semiconductor.
PN junction after
complete process

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Summary
❑ Described key semiconductor technologies
❑ Introduced with basic fabrication steps

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