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Silicon on insulator (SOI) technology refers to the use of a layered
silicon-insulator-silicon substrate in place of conventional silicon substrates
in semiconductor manufacturing to reduce parasitic device capacitance,
thereby improving performance. The first industrial implementation of SOI
was
announced by IBM in August 1998.

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Reported benefits of SOI technology relative to conventional
silicon (bulk CMOS) processing include:
Lower parasitic capacitance due to isolation from the bulk silicon,
which improves power consumption at matched performance between
the two technologies.
Resistance to latchup due to complete isolation of the n- and p-well
structures (see next slide).

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 Integration Density

The implementation of SOI technology is one of several manufacturing

strategies
employed to allow the continued miniaturization of microelectronic devices
(Moore's Law).

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Poly, M1 and M2 are runners outside the active area and measured caps are
w.r.t. the substrate. Gain in caps are related to the BOX series cap.
Gate cap with inverted channel.

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The floating body shape looks like that shown in the slide. High depletion near
the drain and lower near the source. The vertical depletion of the drain and
source sidewalls interact with the gate induced depletion region to result in the
shown shape.
The parasitic base is floating. Once Vbe reaches 0.6 V the BJT conducts and a
kink appears. This is known as the floating body effect.

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In saturation most Vds drop is near the drain (pinch-off region).
The BJT needs 0.6 V for Vbe to conduct and this low voltage needs high drain
voltage.
If we can access the bulk and force it to zero potential then the BJT will be
OFF
and no kink is obtained. This type of SOI MOSFETs is partially depleted
below
the channel, i.e. bulk region or neutral region exists since the active top silicon
is considered thick enough.
If the top layer is made thinner, a fully depleted transistor is obtainable.
In this case we eliminate the BJT (no p-type base which is fully depleted).

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 Body

Top Si p- makes full depletion possible at low voltages. It also enhances the
mobility. No parasitic BJT when the MOSFET is ON and no floating body
effect.
Also in sub Vth operation we may not have full depletion (low VGS) and the
exponential BJT current appears.
Since the body (base) is p- then good BJT is obtained (lower recombination).
In full depletion the depletion charge remains constant hence better control of
the gate on the channel.

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IBM began to use SOI in the high-end RS64-IV "Istar" PowerPC-AS
microprocessor in 2000.
Other examples of microprocessors built on SOI technology include AMD's
130 nm, 90 nm,
65 nm, 45 nm and 32 nm single, dual, quad, six and eight core processors since
2001.
Freescale adopted SOI in their PowerPC 7455 CPU in late 2001,
Freescale was shipping SOI products in 180 nm, 130 nm, 90 nm and 45 nm
lines.
The 90 nm Power Architecture based processors used in the Xbox
360, PlayStation 3
use SOI technology as well. Competitive offerings from Intel, however, such
as the 65 nm
Core 2 and Core 2 Duo microprocessors, are built using conventional
bulk CMOS technology.
Then Intel announced its SOI at 22 nm processor but due to cost issues, instead
has
used FinFET technology.

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The slide presents a simplified explanation.

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The slide presents a simplified explanation.

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From a manufacturing perspective, SOI substrates are compatible with most
conventional
fabrication processes. In general, an SOI-based process may be implemented
without
special equipment or significant retooling of an existing factory.
Among challenges unique to SOI are requirements on the uniformity of
buried oxide layer and concerns about differential stress in the silicon top
layer.
The primary barrier to SOI implementation is the drastic increase in substrate
cost,
which contributes an estimated 10–15% increase to total manufacturing costs.

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The epitaxial growth of silicon on sapphire wafers faces the problems of lattice
mismatch and difference in TCE. A relatively thick defective region is present
at the Si–sapphire interface. The density of defects is reduced by implantation
of Si to amorphize the bottom of the film followed by solid-phase epitaxial
regrowth (SPEAR).

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- heya kant crystal bs feha defects
- 3a4an nrf3ha bn3ml oxidation
fa el oxide hyakol mn el Si layer
el t7t w b3dha n3mel etching lel
SiO2 layer fa ytl3lna el SOI layer
el heya very thin over el sapphire

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Also expensive as we one wafer is lost.

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 High Current Implanter
el dose a3la bkteer mn el btost5dm fel Doping (low current implanter)

BOX

Buried SiO2 layer with the excellent characteristic by implantation of oxygen

into silicon at an acceleration voltage 150 kV and a dose of 1.2 1018 cm-2 with
the annealing temperature of 1150 deg C. This process will left a thin layer of
single-crystal silicon on the surface.
Notice the very high dose used (compared to those used for doping). This high
dose requires a high current implanter (for doping we use low current
implanters).
Also notice how the growth of oxide (BOX) makes the SOI layer thinner.

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Wafer B is reused which makes this technology more cost effective when
compared to BESOI.

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An exhaustive review of these various manufacturing processes may be found
in reference:
Celler, G. K.; Cristoloveanu, S. (2003). "Frontiers of silicon-on-insulator". J
Appl Phys 93 (9): 4955.

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The 2-step LOCOS is to reduce dimensions (similar to the Bausch process
described as deep multi-step etching).
The reason is that the active oxide is relatively thick and a single LOCOS
will consume large area to separate the N and P islands.
Trench isolation can replace this 2 step LOCOS.
This allows going deeper in oxide isolation without too much lateral separation
between the two islands.

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Why the surface is flat?
The depth of the 1st LOCOS and the sidewall nitride result in 2nd vertical
LOCOS to a certain height. The lower part of the 2nd LOCOS (2 times the
consumed Si) reaches the BOX and the upper part lifts the buffer oxide to a
flat surface. Avoiding CMP enhances the yield.

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Backend OL

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Angle Due to LOCOS

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